DISCONTINUED PRODUCT
— FOR REFERENCE ONLY
Recommended replacement — A6810
BiMOS II 10-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS FOR -40
°
C T O +85
°
C OPERATION
Always order by complete part number, e.g., UCQ5810AF .
The UCQ5810AF and UCQ5810LWF combine a 10-bit CMOS shift
register and accompanying data latches, control circuitry, bipolar sourcing
outputs with DMOS active pull-downs. Designed primarily to drive vacuum-
fluorescent displays, the 60 V and -40 mA output ratings also allow these
devices to be used in many other peripheral power driver applications. The
UCQ5810AF/LWF feature reduced supply requirements (active DMOS pull-
downs) and lower saturation voltages when compared with the original
UCQ5810A.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Use with TTL may
require appropriate pull-up resistors to ensure an input logic high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCQ5811A (12 bits), UCQ5812AF/EPF (20 bits), and UCQ5818AF/EPF (32
bits).
The UCQ5810AF/LWF output source drivers are npn Darlingtons
capable of sourcing up to 40 mA. The DMOS active pull-downs are capable
of sinking up to 15 mA. For inter-digit blanking, all of the output drivers can
be disabled and the DMOS sink drivers turned on by the BLANKING input
high.
The UCQ5810AF is furnished in an 18-pin dual in-line plastic package.
The UCQ5810LWF is furnished in a wide-body, small-outline plastic package
(SOIC) with gull-wing leads. Copper lead frames, reduced supply current
requirements, and lower output saturation voltages allow all devices to source
25 mA from all outputs continuously, over the entire operating temperature
range.
FEATURES
■High-Speed Source Drivers
■60 V Minimum
Output Breakdown
■Improved Replacements
for TL4810B
UCQ5810AF
Data Sheet
26182.25C
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
BLANKING
LOGIC
SUPPLY
STROBE
GROUND
CLOCK CLK
V
ST
BLNK
DD
BB
V
OUT
9
OUT
10
OUT
1
OUT
2
OUT
3
Dwg. PP-029
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
1
LATCHES
REGISTER
REGISTER
LATCHES
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD.....................15 V
Driver Supply Voltage, VBB ....................60 V
Continuous Output Current Range,
IOUT.......................... -40 mA to +15 mA
Input Voltage Range,
VIN ........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD
(UCQ5810AF)........................... 2.08 W*
(UCQ5810LWF)........................ 1.33 W*
Operating Temperature Range,
TA.................................. -40°C to +85°C
Storage Temperature Range,
TS................................ -55°C to +150°C
*Derate linearly to 0 W at +150°C.
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCQ5810AF (dual in-line package)
and UCQ5810LWF (small-outline IC package)
are electrically identical and share a common
terminal number assignment.
■Low Output Saturation Voltages
■Low-Power CMOS Logic
and Latches
■To 3.3 MHz Data Input Rate
■Active DMOS Pull-Downs
5810-F
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
MOS
BIPOLAR
OUT
1
OUT
2
GROUND
Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
FUNCTIONAL BLOCK DIAGRAM
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
Dwg. No. A-14,219
11
12
13
14
15
17
10
16
18
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
BLANKING
OUT
9
OUT
10
OUT
1
OUT
2
OUT
3
Dwg. PP-029-1
1
2
3
8
9
4
5
6
7
LOGIC
SUPPLY
STROBE
GROUND
CLOCK CLK
V
ST
BLNK
DD
BB
V
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
LATCHES
REGISTER
REGISTER
LATCHES
UCQ5810LWF
V
OUT
BB
N
Dwg. EP-010-4A
IN
VDD
Copyright © 1988, 2004 Allegro MicroSystems, Inc.
50 75 100 125 150
2.5
0.5
0
AMBIENT TEMPERATURE IN °°
°°C
2.0
1.5
1.0
25
Dwg. GP-018C
SUFFIX 'A', R = 60°C/W
θJA
SUFFIX 'LW', R = 94°C/W
θJA
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
www.allegromicro.com
ELECTRICAL CHARACTERISTICS over operating temperature range, VBB = 60 V unless other-
wise noted.
Limits @ VDD = 5 V Limits @ VDD = 12 V
Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current ICEX VOUT = 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA
Output Voltage VOUT(1) IOUT = -25 mA 58 58.5 — 58 58.5 — V
VOUT(0) IOUT = 1 mA — 1.0 1.5 — — — V
IOUT = 2 mA — — — — 1.0 1.5 V
Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB 2.0 3.5 — — — — mA
VOUT = 20 V to VBB ——— 8.013— mA
Input Voltage VIN(1) 3.5 — 5.3 10.5 — 12.3 V
VIN(0) -0.3 — +0.8 -0.3 — +0.8 V
Input Current IIN(1) VIN = VDD — — 100 — — 240 µA
IIN(0) VIN = 0.8 V — -0.05 -0.5 — -0.1 -1.0 µA
Serial Data Output Voltage VOUT(1) IOUT = -200 µA 4.5 4.7 — 11.7 11.8 — V
VOUT(0) IOUT = 200 µA — 200 250 — 100 200 mV
Maximum Clock Frequency fclk 3.3* — — — — — MHz
Supply Current IDD(1) All Outputs High — 100 300 — 200 500 µA
IDD(0) All Outputs Low — 100 300 — 200 500 µA
IBB(1) Outputs High, No Load — 0.7 2.0 — 0.7 2.0 mA
IBB(0) Outputs Low — 10 100 — 10 100 µA
Blanking to Output Delay tPHL CL = 30 pF, 50% to 50% — 2000 — — 1000 — ns
tPLH CL = 30 pF, 50% to 50% — 1000 — — 850 — ns
Output Fall Time tfCL = 30 pF, 90% to 10% — 1450 — — 650 — ns
Output Rise Time trCL = 30 pF, 10% to 90% — 650 — — 700 — ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranted.
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INBlanklng I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNLP
1P2P3... PN-1 PN
X X X ... X X H L L L ... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time).......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) .............................................................................75 ns
C. Minimum Data Pulse Width ................................................................150 ns
D. Minimum Clock Pulse Width............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion .........................................................................500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
Dwg. No. A-12,649A
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
www.allegromicro.com
UCQ5810AF
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 21 devices.
0.355
0.204
7.62
BSC
Dwg. MA-001-18A mm
10.92
MAX
18
19
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC 0.13
MIN
3.81
2.93
10
23.37
22.35
0.014
0.008
0.300
BSC
Dwg. MA-001-18A in
0.430
MAX
18
19
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC 0.005
MIN
0.150
0.115
10
0.920
0.880
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCQ5810LWF
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 41 devices or add “TR” to part number for tape and reel.
0°
TO
8°
1 2 3
0.020
0.013
0.0040
MIN.
0.0125
0.0091
0.050
0.016
D
wg. MA-008-18A in
0.050
BSC
18 10
0.419
0.394
0.2992
0.2914
0.4625
0.4469
0.0926
0.1043
0°
TO
8°
1
18
23
0.51
0.33
0.10
MIN.
0.32
0.23
1.27
0.40
Dwg. MA-008-18A mm
1.27
BSC
10
7.60
7.40 10.65
10.00
11.75
11.35
2.65
2.35
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
www.allegromicro.com
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
