IPD85P04P4L-06 OptiMOS(R)-P2 Power-Transistor Product Summary VDS -40 V RDS(on) 6.4 mW ID -85 A Features * P-channel - Logic Level - Enhancement mode * AEC qualified PG-TO252-3-313 * MSL1 up to 260C peak reflow Tab * 175C operating temperature * Green package (RoHS compliant) 1 3 * 100% Avalanche tested Source pin 3 Gate pin 1 Type Package Marking IPD85P04P4L-06 PG-TO252-3-313 4P04L06 Drain pin 2/Tab Maximum ratings, at T j=25 C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions T C=25C, V GS=-10V T C=100C, Value -85 V GS=-10V2) -66 Unit A Pulsed drain current2) I D,pulse T C=25C -340 Avalanche energy, single pulse2) E AS I D=-42.5A 30 mJ Avalanche current, single pulse I AS - -85 A Gate source voltage V GS - +5/-16 V Power dissipation P tot T C=25 C 88 W Operating and storage temperature T j, T stg - -55 ... +175 C IEC climatic category; DIN IEC 68-1 - - 55/175/56 Rev. 1.1 page 1 2019-07-04 IPD85P04P4L-06 Parameter Symbol Values Conditions Unit min. typ. max. Thermal characteristics2) Thermal resistance, junction - case R thJC - - - 1.7 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area3) - - 40 K/W Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0V, I D= -1mA -40 - - Gate threshold voltage V GS(th) V DS=V GS, I D=-150A -1.2 -1.7 -2.2 Zero gate voltage drain current I DSS V DS=-32V, V GS=0V, T j=25C - -0.05 -1 T j=125C2) - -20 -200 V DS=-32V, V GS=0V, V A Gate-source leakage current I GSS V GS=-16V, V DS=0V - - -100 nA Drain-source on-state resistance R DS(on) V GS=-4.5V, I D=-50A - 7.7 10.3 mW V GS=-10V, I D=-85A - 5.3 6.4 Rev. 1.1 page 2 2019-07-04 IPD85P04P4L-06 Parameter Symbol Values Conditions Unit min. typ. max. - 5060 6580 - 1520 2280 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 60 120 Turn-on delay time t d(on) - 17 - Rise time tr - 10 - Turn-off delay time t d(off) - 62 - Fall time tf - 39 - Gate to source charge Q gs - 19 25 Gate to drain charge Q gd - 13 26 Gate charge total Qg - 80 104 Gate plateau voltage V plateau - -3.5 - V - - -85 A - - -340 - -1 -1.3 V - 56 - ns - 64 - nC V GS=0V, V DS=-25V, f =1MHz V DD=-20V, V GS=-10V, I D=-85A, R G=3.5W pF ns Gate Charge Characteristics2) V DD=-32V, I D=-85A, V GS=0 to -10V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25C V GS=0V, I F=-85A, T j=25C V R=-20V, I F=-50A, di F/dt =-100A/s 1) Current is limited by bondwire; with an R thJC = 1.7K/W the chip is able to carry -94A at 25C. 2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 2019-07-04 IPD85P04P4L-06 1 Power dissipation 2 Drain current P tot = f(T C); V GS -6V I D = f(T C); V GS = -10V 100 80 80 60 60 -ID [A] Ptot [W] 100 40 40 20 20 0 0 0 50 100 150 200 0 50 100 TC [C] 150 200 TC [C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 1 s 100 0.5 10 s 100 0.1 ZthJC [K/W] -ID [A] 100 s 1 ms 10-1 0.05 0.01 10 10-2 1 10-3 0.1 1 10 100 -VDS [V] Rev. 1.1 single pulse 10-6 10-5 10-4 10-3 10-2 10-1 100 tp [s] page 4 2019-07-04 IPD85P04P4L-06 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 C R DS(on) = (I D); T j = 25 C parameter: -V GS parameter: -V GS 40 360 2.8V 3V 5V 3.5V 35 300 30 RDS(on) [mW] 240 -ID [A] 4.5V 10V 180 25 20 4V 120 15 60 3.5V 4V 10 4.5V 3V 5V 10V 0 0 2 4 5 6 0 20 40 -VDS [V] 60 80 -ID [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = -6V R DS(on) = f(T j); I D = -85 A; V GS = -10 V parameter: T j 8 280 7 -ID [A] RDS(on) [mW] 210 140 6 5 70 -55 C 175 C 25 C 4 0 1.6 2.6 3.6 -60 4.6 20 60 100 140 180 Tj [C] -VGS [V] Rev. 1.1 -20 page 5 2019-07-04 IPD85P04P4L-06 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: -I D 2.5 105 2 104 Ciss 1.5 C [pF] -VGS(th) [V] -1500A -150A Coss 103 102 1 Crss 101 0.5 -60 -20 20 60 100 140 0 180 5 10 Tj [C] 15 20 25 30 140 180 -VDS [V] 11 Typical forward diode characteristicis 12 Drain-source breakdown voltage IF = f(VSD) V BR(DSS) = f(T j); I D = -1 mA parameter: T j 45 103 44 43 42 -IF [A] -VBR(DSS) [V] 102 175 C 25 C 101 41 40 39 38 37 36 35 100 0 0.4 0.8 1.2 1.6 -VSD [V] Rev. 1.1 -60 -20 20 60 100 Tj [C] page 6 2019-07-04 IPD85P04P4L-06 13 Typ. gate charge 14 Gate charge waveforms V GS = f(Q gate); I D = -85 A pulsed parameter: V DD 10 V GS 9 Qg 8 -8V 7 -32V -VGS [V] 6 5 4 3 2 Q gate 1 Q gs Q gd 0 0 30 60 90 Qgate [nC] Rev. 1.1 page 7 2019-07-04 IPD85P04P4L-06 Published by Infineon Technologies AG 81726 Munich, Germany (c) Infineon Technologies AG 2019 All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.1 page 8 2019-07-04 IPD85P04P4L-06 Revision History Version Rev. 1.1 Date Changes 1.0 14.03.2011 Final Data Sheet 1.1 04.07.2019 VGS changed page 9 2019-07-04