TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 FAMILY OF MICROPOWER RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS FEATURES D BiMOS Rail-to-Rail Output D Input Bias Current . . . 1 pA D High Wide Bandwidth . . . 160 kHz D High Slew Rate . . . 0.1 V/s D Supply Current . . . 7 A (per channel) D Input Noise Voltage . . . 89 nV/Hz D Supply Voltage Range . . . 2.7 V to 16 V D Specified Temperature Range D DESCRIPTION The TLV27Lx single supply operational amplifiers provide rail-to-rail output capability. The TLV27Lx takes the minimum operating supply voltage down to 2.7 V over the extended industrial temperature range, while adding the rail-to-rail output swing feature. The TLV27Lx also provides 160-kHz bandwidth from only 7 A. The maximum recommended supply voltage is 16 V, which allows the devices to be operated from (8-V supplies down to 1.35 V) two rechargeable cells. - -40C to 125C . . . Industrial Grade - 0C to 70C . . . Commercial Grade Ultra-Small Packaging - 5 Pin SOT-23 (TLV27L1) The rail-to-rail outputs make the TLV27Lx good upgrades for the TLC27Lx family--offering more bandwidth at a lower quiescent current. The TLV27Lx offset voltage is equal to that of the TLC27LxA variant. Their cost effectiveness makes them a good alternative to the TLC/V225x, where offset and noise are not of premium importance. APPLICATIONS D Portable Medical D Power Monitoring D Low Power Security Detection Systems D Smoke Detectors The TLV27L1/2 are available in the commercial temperature range to enable easy migration from the equivalent TLC27Lx. The TLV27L1 is not available with the power saving/performance boosting programmable pin 8. The TLV27L1 is available in the small SOT-23 package --something the TLC27(L)1 was not--enabling performance boosting in a smaller package. The TLV27L2 is available in the 3mm x 5mm MSOP, providing PCB area savings over the 8-pin SOIC and 8-pin TSSOP. SELECTION GUIDE DEVICE VS [V] IQ/ch [A] VICR [V] VIO [mV] IIB [pA] GBW [MHz] SLEW RATE [V/s] Vn, 1 kHz [nV/Hz] TLV27Lx TLV238x 2.7 to 16 11 2.7 to 16 10 -0.2 to VS+1.2 5 60 0.18 0.06 89 -0.2 to VS-0.2 4.5 60 0.18 0.06 TLC27Lx 4 to 16 90 17 -0.2 to VS-1.5 10/5/2 60 0.085 0.03 68 OPAx349 OPAx347 1.8 to 5.5 2 -0.2 to VS+0.2 10 10 0.070 0.02 300 2.3 to 5.5 34 -0.2 to VS+0.2 6 10 0.35 0.01 60 TLC225x 2.7 to 16 62.5 0 to VS-1.5 1.5/0.85 60 0.200 0.02 19 NOTE: All dc specs are maximums while ac specs are typicals. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2001-2012, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE SYMBOL TLV27L1CD SOIC 8 SOIC-8 D 27V1C SPECIFIED TEMPERATURE RANGE 0C to 70C TLV27L1CDBV SOT 23 SOT-23 DBV VBIC TLV27L1ID SOIC 8 SOIC-8 D 27V1I TLV27L1IDBV SOT 23 SOT-23 DBV VBII TLV27L2CD SOIC 8 SOIC-8 D 27V2C SOIC 8 SOIC-8 D TRANSPORT MEDIA TLV27L1CD Tube TLV27L1CDR Tape and Reel TLV27L1CDBVR Tape and Reel TLV27L1CDBVT -40C 40C to 125C TLV27L2ID ORDER NUMBER TLV27L1ID Tube TLV27L1IDR Tape and Reel TLV27L1IDBVR Tape and Reel TLV27L1IDBVT 27V2I 0C to 70C -40C 40C to 125C TLV27L2CD Tube TLV27L2CDR Tape and Reel TLV27L2ID Tube TLV27L2IDR Tape and Reel absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 125C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Relative to GND pin. DISSIPATION RATING TABLE PACKAGE JC (C/W) JA (C/W) TA 25C POWER RATING TA = 85C POWER RATING D (8) 38.3 176 710 mW 370 mW DBV (5) 55 324.1 385 mW 201 mW DBV (6) 55 294.3 425 mW 221 mW recommended operating conditions MIN Supply voltage voltage, (VS) Dual supply Single supply Input common-mode voltage range Operating free-air free air temperature temperature, TA 2 C-suffix I-suffix www.ti.com MAX 1.35 8 2.7 16 -0.2 VS-1.2 0 70 -40 125 UNIT V V C TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 10 V (unless otherwise noted) dc performance PARAMETER TEST CONDITIONS VIO Input offset voltage VIO Offset voltage drift CMRR Common mode rejection ratio Common-mode VIC = 0 V to VS-1.2 1.2 V, RS = 50 AVD Large signal differential voltage Large-signal amplification VO(PP)=VS/2, RL = 100 k /2 VIC = VS/2, RL = 100 k, k VO = VS/2, /2 RS = 50 VS = 2.7 V, 5V VS = 5 V TA MIN 25C TYP MAX 0.5 5 Full range 7 25C 1.1 25C 71 Full range 70 25C 80 Full range 77 25C 77 Full range 74 UNIT mV V/C 86 dB 100 dB 82 Full range is -40C to 125C for I suffix. input characteristics PARAMETER TEST CONDITIONS TA MIN 25C IIO Input offset current VIC = VS/2, RL = 100 k, IIB VO = VS/2, RS = 50 Input bias current ri(d) Differential input resistance CIC Common-mode input capacitance f = 1 kHz TYP MAX 1 60 70C 100 125C 1000 1 25C UNIT pA 60 70C 200 125C 1000 pA 25C 1000 G 25C 8 pF power supply PARAMETER TEST CONDITIONS IQ Quiescent current (per channel) VO = VS/2 PSRR Power supply rejection ratio (VS/VIO) VS = 2.7 V to 16 V, VIC = VS/2 V TA MIN 25C TYP MAX 7 11 Full range No load, 16 25C 74 Full range 70 82 UNIT A A dB Full range is -40C to 125C for I suffix. www.ti.com 3 TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 5 V (unless otherwise noted) (continued) output characteristics PARAMETER TA TEST CONDITIONS VS = 2 2.7 7V VIC = VS/2, IO OL = 100 A VO VS = 5 V Output voltage swing from rail VS = 5 V VS = 5 V VIC = VS/2, IO OL = 500 A IO Output current VS = 5 V VO = 0.5 V from rail VS = 2.7 V MIN 25C TYP MAX 160 200 Full range UNIT 220 25C 85 Full range 120 200 25C 50 Full range 120 150 25C 420 Full range mV 800 900 25C 200 Full range 400 500 25C 400 A Full range is -40C to 125C for I suffix. dynamic performance PARAMETER GBP SR Gain bandwidth product Slew rate at unity gain TEST CONDITIONS RL = 100 k, CL = 10 pF, TA f = 1 kHz VO(pp) = 1 V V, CL = 50 pF RL = 100 k, k CL = 50 pF M Phase margin RL = 100 k, ts Settling time (0.1%) (0 1%) V(STEP)pp = 1 V, AV = -1, 1, CL = 50 pF, RL = 100 k Rise Fall MIN TYP 25C 160 25C 0.06 -40C 0.05 125C 0.8 25C 62 MAX kHz V/s 62 25C UNIT ss 44 noise/distortion performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Vn Equivalent input noise voltage f = 1 kHz 25C 89 nV/Hz In Equivalent input noise current f = 1 kHz 25C 0.6 fA/Hz 4 www.ti.com TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage IIB/IIO Input bias and offset current vs Free-air temperature 1, 2, 3 VOH High-level output voltage vs High-level output current 5, 7, 9 VOL Low-level output voltage vs Low-level output current 6, 8, 10 IQ Quiescent current 4 vs Supply voltage 11 vs Free-air temperature 12 Supply voltage and supply current ramp up 13 AVD Differential voltage gain and phase shift vs Frequency 14 GBP Gain-bandwidth product vs Free-air temperature 15 m Phase margin vs Load capacitance 16 CMRR Common-mode rejection ratio vs Frequency 17 PSRR Power supply rejection ratio vs Frequency 18 Input referred noise voltage vs Frequency 19 SR Slew rate vs Free-air temperature 20 VO(PP) Peak-to-peak output voltage vs Frequency 21 Inverting small-signal response 22 Inverting large-signal response 23 Crosstalk vs Frequency INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE V IO - Input Offset Voltage - A V IO - Input Offset Voltage - A 1500 1000 500 0 -500 VS = 2.7 V TA = 25C 1000 500 0 -500 -2000 0 0.5 1 1.5 2 2.5 VIC - Common-Mode Input Voltage - V Figure 1 3 1000 500 0 -500 -1500 -1500 -1500 VS = 5 Vdc TA = 25C 1500 -1000 -1000 -1000 2000 2000 V IO - Input Offset Voltage - A VS = 2.7 V TA = 25C INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 2000 1500 24 -2000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VIC - Common-Mode Input Voltage - V Figure 2 www.ti.com -2000 -5.2 -3.6 -2 -0.4 1.2 2.8 4.4 VIC - Common-Mode Input Voltage - V Figure 3 5 TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS 5 VS = 5 V VIC = 2.5 VO = 2.5 70 60 50 40 30 IIB 20 IIO 10 0 45 65 85 105 TA - Free-Air Temperature - C 125 0C 2 25C 1 25C 0 -1 -2 125C -3 -4 -5 25 -40C 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 VS = 5 V 4 0C 25C 3 70C 2.5 2 1.5 125C 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 4 70C 3.5 3 25C 2.5 0C 2 1.5 1 -40C 0.5 0 25C 0C 0.9 0.6 0 -40C 0 0.2 0.4 0.6 -4 -5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.8 1 1.2 Figure 10 1.4 5 0C 25C 3 2 0 2 4 6 8 10 12 VS - Supply Voltage - V Figure 11 www.ti.com 0C 25C 1.8 1.5 70C 1.2 0.9 125C 0.6 0.3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 QUIESCENT CURRENT vs FREE-AIR TEMPERATURE 14 16 16 V 10 V 7 70C 6 0 -40C 2.1 8 125C 4 VS = 2.7 V 2.4 Figure 9 QUIESCENT CURRENT vs SUPPLY VOLTAGE -40C HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT IOH - High-Level Output Current - mA 1 IOL - Low-Level Output Current - mA 6 -40C -3 0 8 I (Q) - Quiescent Currenr - A V OL- Low-Level Output Voltage - V 125C 70C 0.3 -2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 7 2.1 1.2 0C Figure 8 VS = 2.7 V 1.5 0 -1 IOL - Low-Level Output Current - mA LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 1.8 25C 2.7 125C Figure 7 2.4 70C 1 Figure 6 VS = 5 V IOH - High-Level Output Current - mA 2.7 2 IOL - Low-Level Output Current - mA LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4.5 -40C 3.5 125C 3 Figure 5 V OL- Low-Level Output Voltage - V VOH - High-Level Output Voltage - V 5 VS = 5 V IOH - High-Level Output Current - mA Figure 4 4.5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VOH - High-Level Output Voltage - V 80 5 VS = 5 V 4 I (Q) - Quiescent Currenr - A 90 VOH - High-Level Output Voltage - V I IB and I IO - Input Bias and Input Offset Currents - pA 100 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT V OL- Low-Level Output Voltage - V INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 5V 6 5 2.7 V 4 3 2 1 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C Figure 12 TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 15 40 120 10 5 A VD - Differential Voltage Gain - dB VS VO 0 VS = 0 to 15 V, RL = 100 , CL = 10 pF, TA = 25C 15 IQ 10 5 0 5 10 15 20 25 0 30 VS = 5 V RL = 100 k CL = 10 pF TA = 25C 100 80 60 40 90 20 120 0 150 -20 0.1 1 t - Time - ms 10 100 Figure 14 VS = 2.7 V VS = 5 V 130 120 110 60 50 40 30 20 10 0 10 20 35 50 65 80 95 110 125 100 Figure 15 70 60 50 40 30 20 10 10 100 1k 10 k f - Frequency - Hz Figure 18 100 k 90 80 70 60 50 40 30 20 10 0 1M 100 1k VS = 5 V, G = 2, RF = 100 k 100 SR+ 0.06 SR- 0.05 0.04 0.03 0.01 10 100 1M 0.07 0.02 50 1 100 k 0.09 0.08 150 0 10 k SLEW RATE vs FREE-AIR TEMPERATURE 250 200 10 Figure 17 SR - Slew Rate - V/ s Hz VS =2.5 V TA = 25C VS = 5 V TA = 25C f - Frequency - Hz INPUT REFERRED NOISE VOLTAGE vs FREQUENCY Vn- Input Referred Noise Voltage - nV/ PSRR - Power Supply Rejection Ratio - dB 100 0 110 100 Figure 16 POWER SUPPLY REJECTION RATIO vs FREQUENCY 80 120 CL - Load Capacitance - pF TA - Free-Air Temperature - C 90 1000 CMRR - Common-Mode Rejection Ratio - dB Phase Margin - Degrees GBP - Gain-Bandwidth Product - kHz VS = 5 V RL = 100 k TA = 25C 70 160 COMMON-MODE REJECTION RATIO vs FREQUENCY PHASE MARGIN vs LOAD CAPACITANCE 80 170 100 -40 -25 -10 5 180 10 k 100 k 1 M 1k f - Frequency - Hz GAIN-BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE 140 30 60 Figure 13 150 0 Phase Shift SUPPLY VOLTAGE AND SUPPLY CURRENT RAMP UP DIFFERENTIAL VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY I CC - Supply Current - A VS - Supply Voltage - V/dc TYPICAL CHARACTERISTICS 1k f - Frequency - Hz Figure 19 www.ti.com 10 k 100 k 0 -40 -25 -10 5 VS = 5 V Gain = 1 VO = 1 RL = 100 k CL = 50 pF 20 35 50 65 80 95 110 125 TA - Free-air Temperature - C Figure 20 7 TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS INVERTING SMALL-SIGNAL RESPONSE PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 2 V OPP - Output Voltage Peak-to-Peak - V 16 VS = 15 V 14 VI = 3 VPP 1.5 1 Amplitude - VPP 12 RL = 100 k, CL = 10 pF, THD+N <= 5% 10 8 6 -0.5 -1.5 2 0 0 -1 VS = 5 V 4 Gain = -1, RL = 100 k, CL = 10 pF, VS = 5 V, VO = 3 VPP, f = 1 kHz 0.5 VS = 2.7 V 10 100 1000 1k -2 -100 10 k VO = 3 VPP 0 100 200 300 400 500 600 700 t - Time - s f - Frequency - Hz Figure 22 Figure 21 CROSSTALK vs FREQUENCY INVERTING LARGE-SIGNAL RESPONSE 0.06 0 Gain = -1, RL = 100 k, CL = 10 pF, VS = 5 V, VO = 100 mVPP, f = 1 kHz 0.02 0 -40 Crosstalk - dB Amplitude - VPP 0.04 -0.02 -80 -120 VO = 100 mVPP 0 -140 100 200 300 400 500 600 700 10 t - Time - s 100 1k f - Frequency - Hz Figure 23 8 -60 -100 -0.04 -0.06 -100 VS = 5 V RL = 2 k CL = 10 pF TA = 25C Channel 1 to 2 -20 VI = 100 mVPP Figure 24 www.ti.com 10 k 100 k TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 APPLICATION INFORMATION offset voltage The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB- RG VI + - RS V VO + OO +V IO R 1) R F G "I IB) R S 1) R R F G "I IB- R F IIB+ Figure 25. Output Offset Voltage Model general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 26). RG RF VDD/2 VI V O + V I - VO + R1 f -3dB + 1) R R F G 1 1 ) sR1C1 1 2pR1C1 C1 Figure 26. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 VI R1 R2 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) + _ f C2 RG RF -3dB RG = + ( 1 2pRC RF 1 2- Q ) VDD/2 Figure 27. 2-Pole Low-Pass Sallen-Key Filter www.ti.com 9 TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high performance of the TLV27Lx, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. D Ground planes--It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling--Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets--Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements--Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components--Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. 10 www.ti.com TLV27L1 TLV27L2 SLOS378B - SEPTEMBER 2001 - REVISED MARCH 2012 APPLICATION INFORMATION general power dissipation considerations For a given JA, the maximum power dissipation is shown in Figure 28 and is calculated by the following formula: P D Where: + T PD TMAX TA JA -T MAX A q JA = Maximum power dissipation of TLV27Lx IC (watts) = Absolute maximum junction temperature (150C) = Free-ambient air temperature (C) = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 Maximum Power Dissipation - W 1.75 TJ = 150C PDIP Package Low-K Test PCB JA = 104C/W 1.5 1.25 MSOP Package Low-K Test PCB JA = 260C/W SOIC Package Low-K Test PCB JA = 176C/W 1 0.75 0.5 0.25 SOT-23 Package Low-K Test PCB JA = 324C/W 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 28. Maximum Power Dissipation vs Free-Air Temperature TLV27L1 D PACKAGE (TOP VIEW) TLV27L1 DBV PACKAGE (TOP VIEW) OUT GND IN+ 1 5 VDD 2 3 4 IN - NC IN - IN + GND 1 8 2 7 3 6 4 5 TLV27L2 D PACKAGE (TOP VIEW) NC VDD OUT NC 1OUT 1IN - 1IN + GND 1 8 2 7 3 6 4 5 VDD 2OUT 2IN - 2IN+ NC - No internal connection www.ti.com 11 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV27L1CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L1IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV27L2CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV27L2IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TLV27L1CDBVR SOT-23 DBV 5 3000 180.0 9.0 TLV27L1CDBVT SOT-23 DBV 5 250 180.0 TLV27L1IDBVR SOT-23 DBV 5 3000 180.0 TLV27L1IDBVT SOT-23 DBV 5 250 TLV27L1IDR SOIC D 8 TLV27L2CDGKR VSSOP DGK TLV27L2CDGKR VSSOP DGK TLV27L2CDR SOIC TLV27L2IDGKR TLV27L2IDGKR TLV27L2IDR 3.15 3.2 1.4 4.0 8.0 Q3 9.0 3.15 3.2 1.4 4.0 8.0 Q3 9.0 3.15 3.2 1.4 4.0 8.0 Q3 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV27L1CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV27L1CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV27L1IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV27L1IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV27L1IDR SOIC D 8 2500 340.5 338.1 20.6 TLV27L2CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV27L2CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV27L2CDR SOIC D 8 2500 340.5 338.1 20.6 TLV27L2IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV27L2IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV27L2IDR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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