8-/10-/12-/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5450/AD5451/AD5452/AD5453
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
FEATURES
12 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8-bit
8-lead TSOT and MSOP packages
2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 μA typical current consumption
Guaranteed monotonic
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
04587-001
8-/10-/12-/14-BIT REF
R-2R DAC
DAC REGISTER
INPUT LATCH
POWER-ON
RESET
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
R
I
OUT
1
R
FB
V
DD
V
REF
GND
SDIN
SCLK
SYNC
AD5450/
AD5451/
AD5452/
AD5453
Figure 1.
GENERAL DESCRIPTION
The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/
12-/14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply, making
them suited to several applications, including battery-powered
applications.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. Upon power-up, the internal shift
register and latches are filled with 0s, and the DAC output is at
zero scale.
The applied external reference input voltage (VREF) determines
the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages.
1 U.S. Patent Number 5,689,257.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 15
General Description ....................................................................... 16
DAC Section ................................................................................ 16
Circuit Operation ....................................................................... 16
Single-Supply Applications ....................................................... 18
Adding Gain ................................................................................ 18
Divider or Programmable Gain Element ................................ 19
Reference Selection .................................................................... 19
Amplifier Selection .................................................................... 19
Serial Interface ............................................................................ 21
Microprocessor Interfacing ....................................................... 21
PCB Layout and Power Supply Decoupling ........................... 23
Evaluation Board for the DAC ...................................................... 24
Power Supplies for the Evaluation Board ................................ 24
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
1/10—Rev. B to Rev. C
Changes to DAC Control Bits C1, C0 .......................................... 21
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
3/06—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Features .......................................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 4
Changes to Figure 27 and Figure 28 ............................................. 11
Change to Table 9 ........................................................................... 20
Changes to Table 12 ........................................................................ 26
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
7/05—Rev. 0 to Rev. A
Added AD5453 ................................................................... Universal
Changes to Specifications ................................................................ 4
Change to Figure 21 ....................................................................... 10
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
1/05—Revision 0: Initial Version
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 3 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise
noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
AD5450
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB
AD5451
Resolution 10 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB
AD5452
Resolution 12 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Total Unadjusted Error ±1 LSB
Gain Error ±0.5 LSB
AD5453
Resolution 14 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Total Unadjusted Error ±4 LSB
Gain Error ±2.5 LSB
Gain Error Temperature Coefficient1 ±2 ppm FSR/°C
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, IOUT1
±10 nA Data = 0x0000, TA = −40°C to +125°C, IOUT1
REFERENCE INPUT1
Reference Input Range ±10 V
VREF Input Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
RFB Feedback Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
Input Capacitance
Zero-Scale Code 18 22 pF
Full-Scale Code 18 22 pF
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V
1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V
0.7 V VDD = 2.5 V to 2.7 V
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 μA
V
DD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA
0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 μA
Input Leakage Current, IIL ±1 nA TA = 25°C
±10 nA TA = −40°C to +125°C
Input Capacitance 10 pF
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 4 of 28
Parameter Min Typ Max Unit Conditions
DYNAMIC PERFORMANCE1
Reference-Multiplying BW 12 MHz VREF = ±3.5 V, DAC loaded with all 1s
Multiplying Feedthrough Error VREF = ±3.5 V, DAC loaded with all 0s
72 dB 100 kHz
64 dB 1 MHz
44 dB 10 MHz
Output Voltage Settling Time VREF = 10 V, RLOAD = 100 Ω; DAC latch alternately
loaded with 0s and 1s
Measured to ±1 mV of FS 100 110 ns
Measured to ±4 mV of FS 24 40 ns
Measured to ±16 mV of FS 16 33 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 10 30 ns Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V
Output Capacitance
IOUT1 13 pF DAC latches loaded with all 0s
28 pF DAC latches loaded with all 1s
IOUT2 18 pF DAC latches loaded with all 0s
5 pF DAC latches loaded with all 1s
Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
Analog THD 83 dB VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Digital THD Clock = 1 MHz, VREF = 3.5 V
50 kHz fOUT 71 dB
20 kHz fOUT 77 dB
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
SFDR Performance (Wide Band) Clock = 1 MHz, VREF = 3.5 V
50 kHz fOUT 78 dB
20 kHz fOUT 74 dB
SFDR Performance (Narrow Band) Clock = 1 MHz, VREF = 3.5 V
50 kHz fOUT 87 dB
20 kHz fOUT 85 dB
Intermodulation Distortion 79 dB f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
IDD 0.4 10 μA TA = −40°C to +125°C, logic inputs = 0 V or VDD
0.6 μA TA = 25°C, logic inputs = 0 V or VDD
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%
1 Guaranteed by design and characterization, not subject to production test.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1 V
DD = 2.5 V to 5.5 V Unit Conditions/Comments
fSCLK 50 MHz max Maximum clock frequency
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 8 ns min
SYNC falling edge to SCLK active edge setup time
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 5 ns min
SYNC rising edge to SCLK active edge
t8 30 ns min
Minimum SYNC high time
Update Rate 2.7 MSPS Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
04587-002
SCLK
SYNC
DIN DB15 DB0
t
7
t
3
t
2
t
6
t
5
t
4
t
8
t
1
Figure 2. Timing Diagram
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
VREF, RFB to GND −12 V to +12 V
IOUT1 to GND −0.3 V to +7 V
Input Current to Any Pin Except Supplies ±10 mA
Logic Inputs and Output1 −0.3 V to VDD + 0.3 V
Operating Temperature Range, Extended
(Y Version)
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
8-Lead MSOP 206°C/W
8-Lead TSOT 211°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 7 of 28
04587-003
AD5450/
AD5451/
AD5452/
AD5453
RFB 1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREF 2
VDD 3
SYNC 4
IOUT1
GND
SCLK
SDIN
8
7
6
5
Figure 3. TSOT Pin Configuration
04587-004
AD5452/
AD5453
I
OUT
1
1
R
FB
V
REF
V
DD
8
SYNC
GND
2 7
SCLK
3 6
SDIN
4 5
Figure 4. MSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSOT MSOP Mnemonic Description
1 8 RFB DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external amplifier output.
2 7 VREF DAC Reference Voltage Input.
3 6 VDD Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
4 5 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the
shift register upon the active edge of the following clocks.
5 4 SDIN Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial clock
input. By default, in power-up mode data is clocked into the shift register upon the falling edge of SCLK.
The control bits allow the user to change the active edge to a rising edge.
6 3 SCLK Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge of the serial
clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is
clocked into the shift register upon the rising edge of SCLK.
7 2 GND Ground Pin.
8 1 IOUT1 DAC Current Output.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 32 64 96 128 160 192 224 256
04587-020
CODE
INL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 5. INL vs. Code (8-Bit DAC)
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 128 256 384 512 640 768 896 1024
04587-021
CODE
INL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 6. INL vs. Code (10-Bit DAC)
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0 512 1024 1536 2048 2560 3072 2584 4096
04587-022
CODE
INL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 7. INL vs. Code (12-Bit DAC)
2.0
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
0 2048 4096 6144 8192 10240 12288 14336 16384
04587-023
CODE
INL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 8. INL vs. Code (14-Bit DAC)
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0 32 64 96 128 160 192 224 256
04587-024
CODE
DNL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 9. DNL vs. Code (8-Bit DAC)
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0 128 256 384 512 640 768 896 1024
04587-025
CODE
DNL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 10. DNL vs. Code (10-Bit DAC)
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 9 of 28
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 512 1024 1536 2048 2560 3072 2584 4096
04587-026
CODE
DNL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 11. DNL vs. Code (12-Bit DAC)
2.0
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
0 2048 4096 6144 8192 10240 12288 14336 16384
04587-027
CODE
DNL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
Figure 12. DNL vs. Code (14-Bit DAC)
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
2345678910
REFERENCE VOLTAGE (V)
INL (LSB)
T
A
= 25
°
C
V
DD
= 5V
AD5452
04587-070
MAX INL
MIN INL
Figure 13. INL vs. Reference Voltage
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2345678910
REFERENCE VOLTAGE (V)
DNL (LSB)
T
A
= 25
°
C
V
DD
= 5V
AD5452
04587-071
MAX DNL
MIN DNL
Figure 14. DNL vs. Reference Voltage
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0 32 64 96 128 160 192 224 256
04587-030
CODE
TUE (LSB)
T
A
= 25
°
C
V
REF
= 10V
V
DD
= 5V
AD5450
Figure 15. TUE vs. Code (8-Bit DAC)
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 128 256 384 512 640 768 896 1024
04587-031
CODE
TUE (LSB)
T
A
= 25
°
C
V
REF
= 10V
V
DD
= 5V
AD5451
Figure 16. TUE vs. Code (10-Bit DAC)
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 10 of 28
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 512 1024 1536 2048 2560 3072 2584 4096
04587-032
CODE
TUE (LSB)
T
A
= 25
°
C
V
REF
= 10V
V
DD
= 5V
Figure 17. TUE vs. Code (12-Bit DAC)
2.0
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
0 2048 4096 6144 8192 10240 12288 14336 16384
04587-033
CODE
INL (LSB)
T
A
= 25
°
C
V
REF
= 10V
V
DD
= 5V
Figure 18. TUE vs. Code (14-Bit DAC)
–2.0
–1.5
–1.0
0
1.0
1.5
2.0
2345 8910
REFERENCE VOLTAGE (V)
TUE (LSB)
04587-072
76
MAX TUE
–0.5
0.5
T
A
= 25°C
V
DD
= 5V
AD5452
MIN TUE
Figure 19. TUE vs. Reference Voltage
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 60 80 100 120 140
TEMPERATURE (°C)
GAIN ERROR (LSB)
04587-073
4020
V
DD
= 5V
V
DD
= 3V
Figure 20. Gain Error (LSB) vs. Temperature
–2.0
–1.5
–1.0
0
1.0
1.5
2.0
2345 8910
REFERENCE VOLTAGE (V)
GAIN ERROR (LSB)
04587-074
76
–0.5
0.5
T
A
= 25°C
V
DD
= 5V
AD5452
Figure 21. Gain Error (LSB) vs. Reference Voltage
2.0
1.6
1.2
0.8
0.4
0
–40 –20 0 20 40 60 80 100 120
04587-039
TEMPERATURE (°C)
I
OUT
1 LEAKAGE (nA)
I
OUT
1 V
DD
= 5V
I
OUT
1V
DD
= 3V
Figure 22. IOUT1 Leakage Current vs. Temperature
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 11 of 28
2.5
2.0
1.5
1.0
0.5
0
012345
04587-038
INPUT VOLTAGE (V)
CURRENT (mA)
T
A
= 25°C
V
DD
= 3V
V
DD
= 5V
Figure 23. Supply Current vs. Logic Input Voltage
0.7
0
0.1
0.2
0.3
0.4
0.5
0.6
–40 –20 0 20 40 60 80 100 120
04587-037
TEMPERATURE (°C)
CURRENT (
μ
A)
V
DD
= 5V
V
DD
= 3V
ALL 1s
ALL 0s
Figure 24. Supply Current vs. Temperature
04587-075
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
6
0
1
2
3
4
5
CURRENT (mA)
T
A
= 25°C
AD5452
LOADING 010101010101
V
DD
= 5V
V
DD
= 3V
Figure 25. Supply Current vs. Update Rate
2.5 5.5
VOLTAGE (V)
1.8
1.2
1.0
0.4
0.2
0
V
IH
04587-076
1.6
1.4
0.8
0.6
3.0 3.5 4.54.0 5.0
V
IL
THRESHOLD VOLTAGE (V)
T
A
= 25°C
Figure 26. Threshold Voltage vs. Supply Voltage
10
–80
–70
–60
–50
–40
–30
–20
–10
0
10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
04587-108
ALL ON
DB11
DB10
DB9
DB8
DB6
DB5
DB4
DB3
DB7
DB2
DB12
DB13
V
DD
= 5V
V
REF
= ±3.5V
C
COMP
= 1.8pF
AD8038 AMPLIFIER
T
A
= 25°C
LOADING
ZS TO FS
Figure 27. Reference Multiplying Bandwidth vs. Frequency and Code
0.6
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
04587-109
T
A
= 25°C
V
DD
= 5V
V
REF
= ±3.5V
C
COMP
= 1.8pF
AD8038 AMPLIFIER
Figure 28. Reference Multiplying Bandwidth—All 1s Loaded
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 12 of 28
04587-079
10k 100k 1M 10M 100M
FREQUENCY (Hz)
3
–9
0
GAIN (dB)
T
A
= 25°C
V
DD
= 5V
–6
–3
V
REF
= ±2V, AD8038 C
COMP
= 1pF
V
REF
= ±2V, AD8038 C
COMP
= 1.5pF
V
REF
= ±15V, AD8038 C
COMP
= 1pF
V
REF
= ±15V, AD8038 C
COMP
= 1.5pF
V
REF
= ±15V, AD8038 C
COMP
= 1.8pF
Figure 29. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
04587-080
50 200 225 250
TIME (ns)
0.08
–0.06
OUTPUT VOLTAGE (V)
–0.02
175100 125 15075
0.06
0.04
0.02
0
–0.04
T
A
= 25°C
V
DD
= 0V
AD8038 AMPLIFIER
C
COMP
= 1.8pF
V
DD
=5V
0x7FF TO 0x800
NRG = 2.154nVs
V
DD
= 3V
0x7FF TO 0x800
NRG = 1.794nVs
V
DD
=5V
0x800 TO 0x7FF
NRG = 0.694nVs
V
DD
=5V
0x800 TO 0x7FF
NRG = 0.694nVs
Figure 30. Midscale Transition, VREF = 0 V
50 200 225 250
TIME (ns)
–1.66
–1.80
OUTPUT VOLTAGE (V)
–1.76
175100 125 15075
–1.68
–1.70
–1.72
–1.74
–1.78
TA = 25°C
VDD = 3.5V
AD8038 AMPLIFIER
CCOMP = 1.8pF
VDD =5V
0x7FF TO 0x800
NRG = 2.154nVs
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nVs
VDD =5V
0x800 TO 0x7FF
NRG = 0.694nVs
VDD =5V
0x800 TO 0x7FF
NRG = 0.694nVs
04587-081
Figure 31. Midscale Transition, VREF = 3.5 V
04587-082
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
10
–100
–90
–70
–50
–30
–10
PSRR (dB)
T
A
= 25°C
V
DD
= 3V
AD8038 AMPLIFIER
–80
–60
–40
–20
0
FULL SCALE
ZERO SCALE
Figure 32. Power Supply Rejection Ratio vs. Frequency
04587-083
THD+N(dB)
T
A
= 25°C
V
DD
= 5V
V
REF
= ±3.5V
100 1k 10k 100k
FREQUENCY (Hz)
–
60
–90
–85
–75
–65
–80
–70
Figure 33. THD + Noise vs. Frequency
04587-084
05
f
OUT (kHz)
100
0
SFD
0
R
(dB)
40
20 30 4010
80
60
20
TA = 25°C
VREF = ±3.5V
AD8038 AMPLIFIER
MCLK = 500kHz
MCLK = 1MHz
MCLK = 200kHz
Figure 34. Wideband SFDR vs. fOUT Frequency
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 13 of 28
–120
–100
–80
–60
–40
–20
0
0 500k
T
A
= 25°C
V
DD
= 5V
V
REF
= 3.5V
AD8038 AMPLIFIER
FREQUENCY (Hz)
400k300k200k100k
SFDR (dB)
04587-085
Figure 35. Wideband SFDR, fOUT = 20 kHz, Clock = 1 MHz
–120
–100
–80
–60
–40
–20
0
0 500k
FREQUENCY (Hz)
400k300k200k100k
SFDR (dB)
04587-086
T
A
= 25°C
V
DD
= 5V
V
REF
= 3.5V
AD8038 AMPLIFIER
Figure 36. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz
–120
–100
–80
–60
–40
–20
0
10k 30k
FREQUENCY (Hz)
25k20k15k
SFDR (dB)
04587-087
T
A
= 25°C
V
DD
= 5V
V
REF
= 3.5V
AD8038 AMPLIFIER
Figure 37. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz
–120
–100
–80
–60
–40
–20
0
30k 70k
T
A
= 25°C
V
DD
= 5V
V
REF
= 3.5V
AD8038 AMPLIFIER
FREQUENCY (Hz)
60k50k40k
SFDR (dB)
04587-088
Figure 38. Narrow-Band SFDR , fOUT = 50 kHz, Clock = 1 MHz
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 14 of 28
–100
–90
–80
–60
–40
–20
0
10k 35k
FREQUENCY (Hz)
30k25k20k15k
IMD (dB)
04587-089
–70
–50
–30
–10
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
Figure 39. Narrow-Band IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
–100
–90
–80
–60
–40
–20
0
0 500k
T
A
= 25°C
V
REF
= 3.5V
AD8038 AMPLIFIER
FREQUENCY (Hz)
400k300k200k100k
IMD (dB)
04587-090
–70
–50
–30
–10
Figure 40. Wideband IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
04587-091
100 1k 10k 100k 1M
FREQUENCY (Hz)
80
0
70
50
60
40
20
30
10
FULL SCALE
LOADED TO DAC
MIDSCALE
LOADED TO DAC
ZERO SCALE
LOADED TO DAC
OUTPUT NOISE (nV/ Hz)
TA = 25°C
AD8038 AMPLIFIER
Figure 41. Output Noise Spectral Density
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 15 of 28
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is mea-
sured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature
range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF − 1 LSB. Gain error of the DACs is adjustable to zero with
external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when it is
turned off. For the IOUT1 terminal, it can be measured by loading
all 0s to the DAC and measuring the IOUT1 current.
Output Capacitance
Capacitance from IOUT1 to AGND.
Output Current Settling Time
The amount of time it takes for the output to settle to a specified
level for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground. The settling time specification
includes the digital delay from the SYNC rising edge to the full-
scale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s, depending
on whether the glitch is measured as a current or voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the IOUT pins. This
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
1
5432
V
VVVV
THD
2222
log20 +++
=
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa − fb and 2fb − fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Spurious-Free Dynamic Range (SFDR)
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or fS/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 16 of 28
GENERAL DESCRIPTION
DAC SECTION
The AD5450/AD5451/AD5452/AD5453 are 8-/10-/12-/14-bit
current output DACs, respectively, consisting of a segmented
(4-bit) inverting R-2R ladder configuration. A simplified
diagram for the 12-bit AD5452 is shown in Figure 42.
2R
S1
2R
S2
2R
S3
2R
S12
2R
DAC DATA LATCHES
AND DRIVERS
R
R
FB
I
OUT
1
V
REF
04587-060
RR R
AGND
Figure 42. AD5452 Simplified Ladder
The feedback resistor, RFB, has a value of R. The value of R is
typically 9 kΩ (with a minimum value of 7 kΩ and a maximum
value of 11 kΩ). If IOUT1 is kept at the same potential as GND, a
constant current flows in each ladder leg, regardless of digital
input code. Therefore, the input resistance presented at VREF is
always constant and nominally of value R. The DAC output
(IOUT1) is code-dependent, producing various resistances and
capacitances. When choosing the external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
Access is provided to the VREF, RFB, and IOUT1 terminals of the
DAC, making the device extremely versatile and allowing it to be
configured in several operating modes; for example, it can provide
a unipolar output or can provide 4-quadrant multiplication in
bipolar mode. Note that a matching switch is used in series with
the internal RFB feedback resistor. If users attempt to measure
RFB, power must be applied to VDD to achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide a 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 43. When an output amplifier
is connected in unipolar mode, the output voltage is given by
REF
n
OUT V
D
V×−= 2
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
= 0 to 16,383 (14-bit AD5453).
n is the number of bits.
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
04587-009
R
FB
I
OUT
1
GND
SCLK SDIN
V
REF
V
REF
R1
SYNC
AD5450/
AD5451/
AD5452/
AD5453
V
DD
V
DD
AGND
C1
A1
R2
V
OUT
= 0 TO –V
REF
µCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2
. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 43. Unipolar Mode Operation
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal digital logic to drive the on and off states of the
DAC switches.
These DACs are designed to accommodate ac reference input
signals in the range of −10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 43 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between the digital code and
the expected output voltage for a unipolar operation using the
8-bit AD5450.
Table 5. Unipolar Code Table for the AD5450
Digital Input Analog Output (V)
1111 1111 −VREF (255/256)
1000 0000 −VREF (128/256) = −VREF/2
0000 0001 −VREF (1/256)
0000 0000 −VREF (0/256) = 0
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 17 of 28
Bipolar Mode
In some applications, it may be necessary to generate a full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 44. In
this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from Code 0 (VOUT = − VREF) to midscale
(VOUT − 0 V ) to full scale (VOUT = +VREF).
REF
n
REF
OUT V
D
VV −
⎟
⎠
⎞
⎜
⎝
⎛×= −1
2
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
n is the resolution of the DAC.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. Tabl e 6 shows the relationship between the
digital code and the expected output voltage for a bipolar
operation using the 8-bit AD5450.
Table 6. Bipolar Code Table for the AD5450
Digital Input Analog Output (V)
1111 1111 +VREF (127/128)
1000 0000 0
0000 0001 −VREF (127/128)
0000 0000 −VREF (128/128)
04587-010
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
RFB
IOUT1
GND
SCLK SDIN
VREF
±10V VREF
R1
SYNC
AD5450/
AD5451/
AD5452/
AD5453
VDD
VDD
AGND
C1
A1
A2
R2
VOUT = –VREF TO +VREF
µCONTROLLER
R3
20kΩ
R4
10kΩ
R5
20kΩ
Figure 44. Bipolar Mode Operation (4-Quadrant Multiplication)
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 18 of 28
Stability
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
with RFB for stability, as shown in Figure 43 and Figure 44. Too
small a value of C1 can produce ringing at the output, and too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 45 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin, and
the output voltage is available at the VREF terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (the
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
0
4587-011
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
V
IN
I
OUT
1V
REF
GND
V
DD
V
DD
V
OUT
R1 R2
Figure 45. Single-Supply Voltage-Switching Mode
It is important to note that with this configuration VIN is limited
to low voltages because the switches in the DAC ladder do not
have the same source-drain drive voltage. As a result, their on
resistance differs, which degrades the integral linearity of the
DAC. Also, VIN must not go negative by more than 0.3 V, or an
internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 46.
04587-012
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
I
OUT
1
GND
–5V
+5V
ADR03
GND
V
OUT
V
IN
V
REF
–2.5V
V
DD
V
DD
= +5V
C1
V
OUT
= 0V TO +2.5V
Figure 46. Positive Output Voltage with Minimum Components
ADDING GAIN
In applications in which the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the RFB resistor causes mismatches in the temperature
coefficients and results in larger gain temperature coefficient
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 47. R1, R2, and
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than 1
are required.
04587-013
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
I
OUT
1
GND
R1 V
REF
V
IN
V
DD
V
DD
C1
V
OUT
R3
R2 GAIN = R2 + R3
R2
R1 = R2R3
R2 + R3
Figure 47. Increasing Gain of Current-Output DAC
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 19 of 28
DIVIDER OR PROGRAMMABLE GAIN ELEMENT REFERENCE SELECTION
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor as shown in Figure 48, the output voltage is inversely
proportional to the digital input fraction, D.
When selecting a reference for use with this series of current-
output DACs, pay attention to the reference’s output voltage
temperature coefficient specification. This parameter not only
affects the full-scale error, but also may affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system is required to hold its overall
specification to within 1 LSB over the temperature range 0°C to
50°C, and the system’s maximum temperature drift should be
less than 78 ppm/°C.
For D = 1 − 2−n, the output voltage is
()
n
ININ
OUT
V
D
V
V−
−
−
=
−
=21
As D is reduced, the output voltage increases. For small values
of the digital fraction, D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (00010000), that is, 16 decimal, in the circuit of Figure 48
should cause the output voltage to be 16 times VIN.
A 12-bit system within 2 LSB accuracy requires a maximum
drift of 10 ppm/°C. Choosing a precision reference with a low
output temperature coefficient minimizes this error source.
Table 7 lists some dc references available from Analog Devices
that are suitable for use with this range of current-output DACs.
AMPLIFIER SELECTION
0
4587-014
NOTE
A
DDITIONAL PINS OMITTED FOR CLARIT
Y
R
FB
I
OUT
1V
REF
GND
V
DD
V
DD
V
OUT
V
IN
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the variable
gain of the circuit due to the code-dependent output resistance of
the DAC. A change in this noise gain between two adjacent digital
fractions produces a step change in the output voltage due to the
offset voltage of the amplifier’s input. This output voltage change
is superimposed on the desired change in output between the two
codes and gives rise to a differential linearity error, which if
large enough, could cause the DAC to be nonmonotonic.
Figure 48. Current-Steering DAC Used as a Divider or
Programmable Gain Element The input bias current of an op amp generates an offset at the
voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
However, for 14-bit applications, some consideration should be
given to selecting an appropriate amplifier.
However, if the DAC has a linearity specification of ±0.5 LSB, D
can have weight anywhere in the range of 15.5/256 to 16.5/256.
Therefore, the possible output voltage is in the range of 15.5 VIN
to 16.5 VIN—an error of 3%, even though the DAC itself has a
maximum error of 0.2%.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolutions.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current in the VREF terminal is
routed to the IOUT1 terminal, the output voltage changes as follows: Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-
switching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration, it
is important to minimize capacitance at the VREF node (the voltage
output node in this application) of the DAC. This is done by using
low input-capacitance buffer amplifiers and careful board design.
DRLeakageLeakagetoDueVoltageErrorOutput /)(
=
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. There is a large range of single-supply amplifiers
available from Analog Devices.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 20 of 28
Table 7. Suitable ADI Precision References
Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) ISS (mA) Output Noise (μV p-p) Package
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-23, SC70
ADR02 5 0.06 3 1 10 SOIC-8
ADR02 5 0.06 9 1 10 TSOT-23, SC70
ADR03 2.5 0.10 3 1 6 SOIC-8
ADR03 2.5 0.10 9 1 6 TSOT-23, SC70
ADR06 3 0.10 3 1 10 SOIC-8
ADR06 3 0.10 9 1 10 TSOT-23, SC70
ADR431 2.5 0.04 3 0.8 3.5 SOIC-8
ADR435 5 0.04 3 0.8 8 SOIC-8
ADR391 2.5 0.16 9 0.12 5 TSOT-23
ADR395 5 0.10 9 0.12 8 TSOT-23
Table 8. Suitable ADI Precision Op Amps
Part No. Supply Voltage (V) VOS (Max) (μV) IB (Max) (nA)
0.1 Hz to 10 Hz
Noise (μV p-p) Supply Current (μA) Package
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8
AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8
AD8603 1.8 to 6 50 0.001 2.3 50 TSOT
AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8
Table 9. Suitable ADI High Speed Op Amps
Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package
AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23, MSOP
AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 21 of 28
SERIAL INTERFACE
The AD5450/AD5451/AD5452/AD5453 have an easy-to-use
3-wire interface that is compatible with SPI, QSPI, MICROWIRE,
and most DSP interface standards. Data is written to the device in
16-bit words. This 16-bit word consists of two control bits and 8,
10, 12, or 14 data bits, as shown in Figure 49, Figure 50, Figure 51,
and Figure 52. The AD5453 uses all 14 bits of DAC data, the
AD5452 uses 12 bits and ignores the two LSBs, the AD5451
uses 10 bits and ignores the four LSBs, and the AD5450 uses
8 bits and ignores the six LSBs.
DAC Control Bits C1, C0
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame, and a power recycle is
required to return it to active on the falling edge. A power cycle
resets the core to default condition. On-chip power-on reset
circuitry ensures that the device powers on with zero scale
loaded to the DAC register and IOUT line.
Table 10. DAC Control Bits
C1 C0 Function Implemented
0 0 Load and update (power-on default)
0 1 Reserved
1 0 Reserved
1 1 Clock data to shift register upon rising edge
SYNC Function
SYNC is an edge-triggered input that acts as a frame-
synchronization signal and chip enable. Data can only be
transferred to the device while SYNC is low. To start the serial
data transfer, SYNC should be taken low, observing the
minimum SYNC falling to SCLK falling edge setup time, t4. To
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
upon the falling edge of SYNC. The SCLK and SDIN input
buffers are powered down upon the rising edge of SYNC.
After the falling edge of the 16th SCLK pulse, bring SYNC high
to transfer data from the input shift register to the DAC register.
04587-005
DB0 (LSB)
DB15 (MSB)
C1 C0 XXXXXX
DB7 DB6 DB5 DB4 DB3 DB2 DB0DB1
CONTROL BITS
DATA BITS
Figure 49. AD5450 8-Bit Input Shift Register Contents
04587-006
DB0 (LSB)
DB15 (MSB)
DB5 DB4 DB3 DB2 DB0DB1C1 C0 DB7 DB6DB8DB9 XXXX
CONTROL BITS
DATA BITS
Figure 50. AD5451 10-Bit Input Shift Register Contents
04587-007
DB0 (LSB)
DB15 (MSB)
DB7 DB6 DB5 DB4 DB3 DB2 DB0
DB1C1 C0 DB11 DB10 DB8
DB9 X
X
CONTROL BITS
DATA BITS
Figure 51. AD5452 12-Bit Input Shift Register Contents
04587-008
DB0 (LSB)
DB15 (MSB)
DB9 DB8 DB7 DB6 DB5 DB4 DB2
DB3
C1 C0 DB13 DB12 DB10
DB11 DB0
DB1
CONTROL BITS
DATA BITS
Figure 52. AD5453 14-Bit Input Shift Register Contents
MICROPROCESSOR INTERFACING
Microprocessor interfacing to a AD5450/AD5451/AD5452/
AD5453 DAC is through a serial bus that uses standard protocol
and is compatible with microcontrollers and DSP processors.
The communication channel is a 3-wire interface consisting of
a clock signal, a data signal, and a synchronization signal. The
AD5450/AD5451/AD5452/AD5453 require a 16-bit word, with
the default being data valid upon the falling edge of SCLK, but
this is changeable using the control bits in the data-word.
ADSP-21xx-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-21xx family of DSPs is easily interfaced to a AD5450/
AD5451/AD5452/AD5453 DAC without the need for extra glue
logic. Figure 53 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial data line,
SDIN. SYNC is driven from one of the port lines, in this case
SPIxSEL.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-2191*
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5450/AD5451/
AD5452/AD5453*
04587-100
Figure 53. ADSP-2191 SPI-to-AD5450/AD5451/AD5452/AD5453 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 54. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the SYNC signal.
SCLK
SCLK
SYNC
TFS
SDIN
DT
ADSP-2101/
ADSP-2103/
ADSP-2191*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-051
AD5450/AD5451/
AD5452/AD5453*
Figure 54. ADSP-2101/ADSP-2103/ADSP-2191
SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 22 of 28
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame SYNC delay and frame SYNC setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t4 (SYNC falling edge to SCLK falling edge setup time)
of 13 ns minimum. See the ADSP-21xx User Manual for infor-
mation on clock and frame SYNC frequencies for the SPORT
register. shows the setup for the SPORT control register. Table 1 1
Table 11. SPORT Control Register Setup
Name Setting Description
TFSW 1 Alternate framing
INVTFS 1 Active low frame signal
DTYPE 00 Right justify data
ISCLK 1 Internal serial clock
TFSR 1 Frame every word
ITFS 1 Internal framing signal
SLEN 1111 16-bit data-word
ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin®
processor and the AD5450/AD5451/AD5452/AD5453 DAC is
shown in Figure 55. In this configuration, data is transferred
through the MOSI (master output, slave input) pin. SYNC is
driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5450/AD5451/
AD5452/AD5453*
04587-102
Figure 55. ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 56. When the SPORT is
enabled, initiate transmission by writing a word to the Tx
register. The data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC’s input shift
register upon the falling edge its SCLK. The DAC output is
updated by using the transmit frame synchronization (TFS) line
to provide a SYNC signal.
SCLK
SCLK
SYNC
TFS
SDIN
DT
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-103
AD5450/AD5451/
AD5452/AD5453*
Figure 56. ADSP-BF5xx SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
80C51/80L51-to-AD5450/AD5451/AD5452/AD5453
Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 57. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
to drive SYNC. As data is transmitted to the switch, P1.1 is taken
low. The 80C51/80L51 transmit data only in 8-bit bytes; there-
fore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P1.1 is taken high following
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
input register acquires its data with the MSB as the first bit received.
The transmit routine should take this into account.
SCLK
TxD
8051*
SYNC
P1.1
SDIN
RxD
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-104
AD5450/AD5451/
AD5452/AD5453*
Figure 57. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface
MC68HC11-to-AD5450/AD5451/AD5452/AD5453
Interface
Figure 58 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 23 of 28
SCLK
SCK/RC3
PIC16C6x/PIC16C7x*
SYNC
RA1
SDIN
SDI/RC4
AD5450/AD5451/
AD5452/AD5453*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-107
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5450/AD5451/AD5452/AD5453,
the SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid upon the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
Figure 60. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
AD5450/AD5451/AD5452/AD5453 DAC is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
SCLK
SCK
AD5450/AD5451/
AD5452/AD5453*
SYNC
PC7
SDIN
MOSI
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-105
Figure 58. MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11. In this configuration with SYNC low, the shift
register clocks data out upon the rising edges of SCLK.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
MICROWIRE-to-AD5450/AD5451/AD5452/AD5453
Interface
Figure 59 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
SCLK
SK
MICROWIRE*
SYNC
CS
SDIN
SO
AD5450/AD5451/
AD5452/AD5453*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-106
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
Figure 59. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface
PIC16C6x/PIC16C7x-to-
AD5450/AD5451/AD5452/AD5453 Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
In this example, I/O Port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. shows the connection diagram. Figure 60
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 24 of 28
EVALUATION BOARD FOR THE DAC
The evaluation board consists of an AD5450, AD5451, AD5452,
or AD5453 DAC and a current-to-voltage amplifier, such as an
AD8065. Included on the evaluation board is a 10 V reference,
ADR01. An external reference can also be applied via an SMB
input.
The evaluation kit consists of a CD with PC software to control
the DAC. The software allows the user to write code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and +5 V supplies. The +12 V VDD
and −12 V VSS are used to power the output amplifier; the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
Both supplies are decoupled to their respective ground plane
with 10 μF tantalum and 0.1 μF ceramic capacitors.
V
SS
C7
10µF
+
C7
0.1µF
V
DD
C9
10µF
+
C10
0.1µF
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
P1–3 SCLK
J3
V
OUT
J1
P1–2 SDIN
J4
P1–4 SYNC
J5
R1
10kΩ
V
DD
1
SCLK
SDIN
SYNC
6SCLK
5SDIN
4SYNC
AD5450/
AD5451/
AD5452/
AD5453
U1
3
V
DD
1
R
FB
8
I
OUT
1
7
GND
2
V
REF
C1
0.1µF
C2
10µF
+
C5
0.1µF
C4
0.1µF
+
C3
10µF
V
DD
1
V–
V+
U3
AD8065AR
2
3
6
4
7
C6
1.8pF
TP
LK1
V
REF
J2
V
REF
3V
IN
4
V
OUT
5TRIM 1
GND
U2
2
V
DD
C11
0.1µF
C12
10µF
+
C13
0.1µF
C14
10µF
+
C15
0.1µF
C16
10µF
+
V
DD
V
SS
AGND
P2–3
V
DD
1
P2–4
P2–2
P2–1
04587-056
Figure 61. Schematic of AD5450/AD5451/AD5452/AD5453 Evaluation Board
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 25 of 28
04587-057
Figure 62. Component-Side Artwork
04587-058
Figure 63. Silkscreen—Component-Side View (Top)
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 26 of 28
04587-059
Figure 64. Solder-Side Artwork
Table 12. Overview of AD54xx and AD55xx Devices
Part No. Resolution No. DACs INL (LSB) Interface Package1 Features
AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial
AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial
AD5450 8 1 ±0.25 Serial UJ-8 12 MHZ BW, 50 MHz serial interface
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial
AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width
AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial interface
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial
AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial
AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial
AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width
AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width
AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial
AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial interface
AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width
AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 n WR pulse width
AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock
AD5547 16 2 ±2 Parallel 4 MHz BW, 20 ns WR pulse width
RU-38
1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 27 of 28
OUTLINE DIMENSIONS
13
56
2
8
4
7
2.90 BSC
PIN 1
INDICATOR
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.10 MAX
*0.90
0.87
0.84
SEATING
PLANE
*1.00 MAX 0.20
0.08 0.60
0.45
0.30
8°
4°
0°
2.80 BSC
*COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 65. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 66. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD5450/AD5451/AD5452/AD5453
Rev. C | Page 28 of 28
ORDERING GUIDE
Model1 Resolution INL Temperature Range Package Description Package Option Branding
AD5450YUJZ-REEL 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y
AD5450YUJZ-REEL7 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y
AD5451YUJZ-REEL 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z
AD5451YUJZ-REEL7 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z
AD5452YUJZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70
AD5452YUJZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70
AD5452YRM 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z
AD5452YRM-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z
AD5452YRMZ 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70
AD5452YRMZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70
AD5452YRMZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70
AD5453YUJZ-REEL 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH
AD5453YUJZ-REEL7 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH
AD5453YRM 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26
AD5453YRM-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26
AD5453YRM-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26
AD5453YRMZ 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH
AD5453YRMZ-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH
AD5453YRMZ-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH
EVAL-AD5450EB
Evaluation Kit
EVAL-AD5451EBZ Evaluation Kit
EVAL-AD5452EBZ Evaluation Kit
EVAL-AD5453EBZ Evaluation Kit
1 Z = RoHS Compliant Part.
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04587-0-1/10(C)