To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. HD74BC645A Octal Bus Transceivers With 3 State Outputs REJ03D0291-0200Z (Previous ADE-205-027 (Z)) Rev.2.00 Jul.16.2004 Description The HD74BC645A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC. When the frequency is 10 MHz. The device has eight bus transceivers with three state outputs in a 20 pin package. Each device has an active low enable input (G) and a direction control input, DiR. When DiR is high, data flows from the A inputs to the B outputs. When DiR is high, data flows from the B inputs to the A outputs. When enable inputs (G) is high, disables both A and B ports by placing then in a high impedance. Features * Input/Output are at high impedance state when power supply is off. * Input pins can be open, when not used, owing to built in input pull up circuit. * Input is TTL level. * Wide operating temperature range Ta = -40 to +85C. * Ordering Information Part Name HD74BC645AFPEL Package Type Package Code SOP-20 pin (JEITA) FP-20DAV Package Abbreviation FP Taping Abbreviation (Quantity) EL (2,000 pcs/reel) Function Table Control Inputs G DIR Operation L L B data to A bus L H H X A data to B bus Z H L X Z : : : : High level Low level Immaterial High impedance Rev.2.00, Jul.16.2004, page 1 of 7 HD74BC645A Pin Arrangement DiR 1 20 VCC A1 2 19 G A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 GND 10 11 B8 (Top view) Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage Input diode current VCC IIK -0.5 to +7.0 30 V mA Input voltage Output voltage VIN VOUT -0.5 to +7.5 -0.5 to +7.5 V V Off state output voltage VOUT(off) -0.5 to +5.5 V Storage temperature Tstg -65 to +150 C Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage Input voltage VCC VIN 4.5 0 5.0 -- 5.5 VCC V V Ouput voltage Operating temperature VOUT Topr 0 -40 -- -- VCC 85 V C 8 ns/V Input rise/fall time*1 tr, tf 0 -- Note: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00, Jul.16.2004, page 2 of 7 HD74BC645A Logic Diagram DiR A1 G B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 Electrical Characteristics (Ta = -40 to +85C) Item Symbol VCC (V) Input voltage VIH Min 2.0 Max -- Unit V Test Conditions Output voltage VIL VOH 4.5 -- 2.4 0.8 -- V V IOH = -3 mA VOL 4.5 4.5 2.0 -- -- 0.5 V V IOH = -15 mA IOL = 48 mA Input diode voltage VIK 4.5 4.5 -- -- 0.55 -1.2 V V IOL = 64 mA IIN = -18 mA Input current II 5.5 5.5 -- -- -250 100 A A VIN = 0 V An or Bn, VIN = 5.5 V 5.5 5.5 -- -- 1.0 100 A A DiR or G, VIN = 5.5 V DiR or G, VIN = 7 V Output short circuit current*1 Off state output current IOS IOZH 5.5 5.5 -100 -- -225 -100 mA A VO = 0 V, VIN = 0 or 5.5 V VO = 2.7 V Supply current IOZL ICCL 5.5 5.5 -- -- -250 31.5 A mA ICCH 5.5 -- 0.5 mA ICCZ 5.5 -- 4.5 mA VO = 0.5 V VIN = 0 or 5.5 V All outputs is "L" VIN = 0 or 5.5 V All outputs is "H" VIN = 0 or 5.5 V All outputs is "Z" ICCT*2 5.5 -- 1.5 mA VIN = 3.4 or 0.5 V Notes: 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. 2. When input by the TTL level, it shows ICC increase at per one input pin. Rev.2.00, Jul.16.2004, page 3 of 7 HD74BC645A Switching Characteristics (CL = 50 pF) Ta = 25C VCC = 5.0 V Item Propagation delay time Ta = -40 to +85C VCC = 5.0 V 10% Symbol Min tPLH 3.0 Max 6.0 Min 3.0 Max 7.0 Unit Test Conditions ns An to Bn tPHL tPLH 3.0 3.0 6.0 6.0 3.0 3.0 7.0 7.0 ns Bn to An tPHL tZH 3.0 3.0 6.0 9.0 3.0 3.0 7.0 11.0 ns G to Bn tZL tZH 3.0 3.0 9.0 9.0 3.0 3.0 11.0 11.0 ns G to An tZL tHZ 3.0 3.0 9.0 8.0 3.0 3.0 11.0 10.0 ns G to Bn tLZ tHZ 3.0 3.0 8.0 8.0 3.0 3.0 10.0 10.0 ns G to An 3.0 8.0 3.0 (Typ) 3.0 -- 10.0 Input capacitance tLZ CIN Output capacitance CI/O 15.0 (Typ) -- Output enable time Output disable time Rev.2.00, Jul.16.2004, page 4 of 7 pF VIN = VCC or GND pF VI/O = VCC or GND HD74BC645A Test Circuit VCC VCC G Pulse Generator Zout = 50 Output See Function Table Input A1 S1 500 B1 450 CL = 50 pF OPEN 7V *4 50 Scope DIR Notes: 1. 2. 3. 4. CL includes probe and jig capacitance. A2-B2 to A8-B8 are identical to above load circuit. S1: Input-Output change switch. Open: tPLH, tPHL, tZH tHZ 7 V: tZL, tLZ Waveforms-1 tr Input 10 % tf 90 % 1.5 V 90 % 1.5 V 3V 10 % 0V t PHL t PLH VOH Output Rev.2.00, Jul.16.2004, page 5 of 7 1.5 V 1.5 V VOL HD74BC645A Waveforms-2 tf G tr 90 % 1.5 V 10 % t ZL Waveform - A Notes: 0V 3.5 V 1.5 V VOL + 0.3 V t HZ t ZH Waveform - B 3V 90 % 1.5 V 10 % t LZ 1.5 V VOH - 0.3 V VOL VOH 0V 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveforms: PRR = 1 MHz, duty cycle 50% 3. Waveform-A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform-B shows input conditions such that the output is "H" level when enable by the output control. Rev.2.00, Jul.16.2004, page 6 of 7 HD74BC645A Package Dimensions As of January, 2003 Unit: mm 12.6 13 Max 11 1 10 1.27 *0.40 0.06 0.10 0.10 0.80 Max *0.20 0.05 2.20 Max 5.5 20 0.20 7.80 +- 0.30 1.15 0 - 8 0.70 0.20 0.15 0.12 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 7 of 7 Package Code JEDEC JEITA Mass (reference value) FP-20DAV -- Conforms 0.31 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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