HD74BC645AFP(E) - RENESAS TECHNOLOGY

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Rev.2.00, Jul.16.2004, page 1 of 7

HD74BC645A

Octal Bus Transceivers With 3 State Outputs REJ03D0291–0200Z

(Previous ADE-205-0 27 (Z) )

Rev.2.00

Jul.16.2004

Description

The HD74BC645A provides high drivability and operation equal to or better than high speed bipolar standard logic IC

by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC.

When the frequency is 10 MHz. The device has eight bus transceivers with three state outputs in a 20 pin package.

Each device has an active low enable input (G) and a direction control input, DiR. When DiR is hig h, data flows from

the A inputs to the B outputs. Whe n Di R is high, data flows from the B inp uts to the A outputs. When enable inputs

(G) is high, disables both A and B ports by placing then in a high impedance.

Features

• Input/Output are at high impedance state when power supply is off.

• Input pins can be open, when not used, owing to built in input pull up circuit.

• Input is TTL level.

• Wide operating temperature range

Ta = –40 to +85°C.

• Ordering Infor mation

Part Name Package Type Package Code Package

Abbreviation Taping Abbreviation

(Quantity)

HD74BC645AFPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel)

Function Table

Control Inputs

GDIR Operation

L L B data to A bus

L H A data to B bus

HX Z

H : High level

L : Low level

X : Immaterial

Z : High impedance

HD74BC645A

Rev.2.00, Jul.16.2004, page 2 of 7

Pin Arrangement

(Top view)

10 11

20 V

DiR

GND

Absolute Maximum Ratings

Item Symbol Rating Unit

Supply voltage VCC –0.5 to +7.0 V

Input diode current IIK ±30 mA

Input voltage VIN –0.5 to +7.5 V

Output voltage VOUT –0.5 to +7.5 V

Off state output voltage VOUT(off) –0.5 to +5.5 V

Storage temperature Tstg –65 to +150 °C

Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two

of which may be realized at the same time.

Recommended Operating Conditions

Item Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

Input voltage VIN 0—V

CC V

Ouput voltage VOUT 0—V

CC V

Operating temperature Topr –40 — 85 °C

Input rise/fall time*1tr, tf0—8ns/V

Note: 1. This item guarantees maximum limit when one input switches.

Waveform: Refer to test circuit of switching characteristics.

HD74BC645A

Rev.2.00, Jul.16.2004, page 3 of 7

Logic Diagram

DiR

Electrical Characteristics (Ta = –40 to +85°C)

Item Symbol VCC (V) Min Max Unit Test Conditions

Input voltage VIH 2.0 — V

VIL —0.8V

Output voltage VOH 4.5 2.4 — V IOH = –3 mA

4.5 2.0 — V IOH = –15 mA

VOL 4.5 — 0.5 V IOL = 48 mA

4.5 — 0.55 V IOL = 64 mA

Input diode voltage VIK 4.5 — –1.2 V IIN = –18 mA

Input current II5.5 — –250 µA VIN = 0 V

5.5 — 100 µA An or Bn, VIN = 5.5 V

5.5 — 1.0 µA DiR or G, VIN = 5.5 V

5.5 — 100 µA DiR or G, VIN = 7 V

Output short circuit current*1IOS 5.5 –100 –225 mA VO = 0 V, VIN = 0 or 5.5 V

Off state output current IOZH 5.5 — –100 µA VO = 2.7 V

IOZL 5.5 — –250 µA VO = 0.5 V

Supply current ICCL 5.5 — 31.5 mA VIN = 0 or 5.5 V

All outputs is “L”

ICCH 5.5 — 0.5 mA VIN = 0 or 5.5 V

All outputs is “H”

ICCZ 5.5 — 4.5 mA VIN = 0 or 5.5 V

All outputs is “Z”

ICCT*25.5 — 1.5 mA VIN = 3.4 or 0.5 V

Notes: 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one

second.

2. When input by the TTL level, it shows ICC increase at per one input pin.

HD74BC645A

Rev.2.00, Jul.16.2004, page 4 of 7

Switching Characteristics (CL = 50 pF)

Ta = 25°C

VCC = 5.0 V Ta = –40 to +85°C

VCC = 5.0 V ±10%

Item Symbol Min Max Min Max Unit Test Conditions

Propagation delay time tPLH 3.0 6.0 3.0 7.0 ns An to Bn

tPHL 3.0 6.0 3.0 7.0

tPLH 3.0 6.0 3.0 7 .0 ns Bn to An

tPHL 3.0 6.0 3.0 7.0

Output enable time tZH 3.0 9.0 3.0 11.0 ns G to Bn

tZL 3.0 9.0 3.0 11.0

tZH 3.0 9.0 3.0 11.0 ns G to An

tZL 3.0 9.0 3.0 11.0

Output disable time tHZ 3.0 8.0 3.0 10.0 ns G to Bn

tLZ 3.0 8.0 3.0 10.0

tHZ 3.0 8.0 3.0 10.0 ns G to An

tLZ 3.0 8.0 3.0 10.0

Input capacitan ce CIN 3.0 (Typ) — pF VIN = VCC or GND

Output capacitance CI/O 15.0 (Typ) — pF VI/O = VCC or GND

HD74BC645A

Rev.2.00, Jul.16.2004, page 5 of 7

Test Circuit

C =

50 pF

Input Output

500 Ω

DIR

VCC

Pulse

Generator

Z = 50 Ω

out

VCC

See Function Table

450 Ω

50 Ω

Scope

OPEN

Notes: 1. CL includes probe and jig capacitance.

2. A2-B2 to A8-B8 ar e ident ical to above lo ad circ u it.

3. S1: Input-Output change switch.

4. Open: tPLH, tPHL, tZH tHZ

7 V: tZL, tLZ

Waveforms-1

tPLH tPHL

VOH

VOL

Input

Output

10 % 0 V

1.5 V

90 %

trtf

1.5 V

90 % 3 V

1.5 V

10 %

HD74BC645A

Rev.2.00, Jul.16.2004, page 6 of 7

Waveforms-2

V – 0.3 V

V + 0.3 V

tZL

1.5 V

tLZ

tZH

1.5 V

tHZ

tftr

90 %

1.5 V

10 %

90 %

1.5 V

10 %

VOH

VOL

0 V

3.5 V

3 V

0 V

Waveform – A

Waveform – B

Notes: 1. tr = 2.5 ns, tf = 2.5 ns

2. Input waveforms: PRR = 1 MHz, duty cycle 50%

3. Waveform-A shows input conditions such that the output is “L” level when enable by the

output control.

4. Waveform-B shows input conditions such that the output is “H” level when enable by the

output control.

HD74BC645A

Rev.2.00, Jul.16.2004, page 7 of 7

Package Dimensions

Package Code

JEDEC

JEITA

Mass

(reference value)

FP-20DAV

—

Conforms

0.31 g

*Ni/Pd/Au plating

*0.40 ± 0.06

0.12

0.15

*0.20 ± 0.05

0.80 Max

12.6

5.5

2.20 Max

13 Max

– 8

0.70 ± 0.20

+ 0.20

– 0.30

7.80

1.27

0.10 ± 0.10

1.15

As of January, 2003

Unit: mm

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