Filterless, High Efficiency,
Mono 2.5 W Class-D Audio Amplifier
SSM2377
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
Filterless, Class-D amplifier with spread-spectrum
Σ-Δ modulation
2.5 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion plus noise (THD + N)
92% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>100 dB signal-to-noise ratio (SNR)
High PSRR at 217 Hz: 80 dB
Ultralow EMI emissions
Single-supply operation from 2.5 V to 5.5 V
Gain select function: 6 dB or 12 dB
Fixed input impedance of 80 kΩ
100 nA shutdown current
Short-circuit and thermal protection with autorecovery
Available in a 9-ball, 1.2 mm × 1.2 mm WLCSP
Pop-and-click suppression
APPLICATIONS
Mobile phones
MP3 players
Portable electronics
GENERAL DESCRIPTION
The SSM2377 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 2.5 W of continuous output power
with <1% THD + N driving a 4 Ω load from a 5.0 V supply.
The SSM2377 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modu-
lation operates with high efficiency even at low output power.
The SSM2377 operates with 92% efficiency at 1.4 W into 8 Ω
from a 5.0 V supply and has an SNR of >100 dB.
Spread-spectrum pulse density modulation (PDM) is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures. The inherent randomized nature of
spread-spectrum PDM eliminates the clock intermodulation
(beating effect) of several amplifiers in close proximity.
The SSM2377 produces ultralow EMI emissions that signifi-
cantly reduce the radiated emissions at the Class-D outputs,
particularly above 100 MHz. The SSM2377 passes FCC Class B
radiated emission testing with 50 cm, unshielded speaker cable
without any external filtering. The ultralow EMI emissions of the
SSM2377 are also helpful for antenna and RF sensitivity problems.
The device is configured for either a 6 dB or a 12 dB gain setting
by connecting the GAIN pin to the VDD pin or the GND pin,
respectively. Input impedance is a fixed value of 80 kΩ, indepen-
dent of the gain select operation.
The SSM2377 has a micropower shutdown mode with a typical
shutdown current of 100 nA. Shutdown is enabled by applying
a logic low to the SD pin.
The device also includes pop-and-click suppression circuitry,
which minimizes voltage glitches at the output during turn-on
and turn-off, reducing audible noise on activation and deactivation.
Built-in input low-pass filtering is also included to suppress out-
of-band noise interference to the PDM modulator.
The SSM2377 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 9-ball, 0.4 mm
pitch, 1.2 mm × 1.2 mm wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
FET
DRIVER
MODULATOR
(Σ-Δ)
0.1µF
VDD
OUT+
OUT–
BIAS
IN+
80kΩ
80kΩ
POWER SUPPLY
2.5V TO 5.5V
IN–
INTERNAL
OSCILLATOR
POP/CLICK
AND EMI
SUPPRESSION GND
10µF
22nF
22nF
SHUTDOWN SD
GAIN SELECT
AUDIO IN+
AUDIO IN–
SSM2377
GAIN
GAIN = 6dB OR 12dB
09824-001
Figure 1.
SSM2377
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Typical Application Circuits .......................................................... 12
Theory of Operation ...................................................................... 13
Overview ..................................................................................... 13
Gain Selection ............................................................................. 13
Pop-and-Click Suppression ...................................................... 13
EMI Noise .................................................................................... 13
Output Modulation Description .............................................. 13
Layout .......................................................................................... 14
Input Capacitor Selection .......................................................... 14
Power Supply Decoupling ......................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
5/11—Revision 0: Initial Version
SSM2377
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 μH, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power POUT f = 1 kHz, 20 kHz BW
R
L = 8 Ω, THD = 1%, VDD = 5.0 V 1.41 W
R
L = 8 Ω, THD = 1%, VDD = 3.6 V 0.72 W
R
L = 8 Ω, THD = 1%, VDD = 2.5 V 0.33 W
R
L = 8 Ω, THD = 10%, VDD = 5.0 V 1.78 W
R
L = 8 Ω, THD = 10%, VDD = 3.6 V 0.90 W
R
L = 8 Ω, THD = 10%, VDD = 2.5 V 0.41 W
R
L = 4 Ω, THD = 1%, VDD = 5.0 V 2.49 W
R
L = 4 Ω, THD = 1%, VDD = 3.6 V 1.25 W
R
L = 4 Ω, THD = 1%, VDD = 2.5 V 0.54 W
R
L = 4 Ω, THD = 10%, VDD = 5.0 V 3.171 W
R
L = 4 Ω, THD = 10%, VDD = 3.6 V 1.56 W
R
L = 4 Ω, THD = 10%, VDD = 2.5 V 0.68 W
Efficiency η POUT = 1.4 W into 8 Ω, VDD = 5.0 V 92.4 %
Total Harmonic Distortion
Plus Noise
THD + N POUT = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.007 %
P
OUT = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.009 %
Input Common-Mode Voltage
Range
VCM 1.0 VDD − 1 V
Common-Mode Rejection
Ratio
CMRR 100 mV rms at 1 kHz 51 dB
Average Switching Frequency fSW 256 kHz
Clock Frequency fOSC 6.2 MHz
Differential Output Offset
Voltage
VOOS Gain = 6 dB 0.4 5.0 mV
POWER SUPPLY
Supply Voltage Range VDD Guaranteed from PSRR test 2.5 5.5 V
Power Supply Rejection Ratio Inputs are ac-grounded, CIN = 0.1 μF,
gain = 6 dB
PSRRGSM V
RIPPLE = 100 mV at 217 Hz 80 dB
PSRR VRIPPLE = 100 mV at 1 kHz 80 dB
Supply Current ISY V
IN = 0 V, no load, VDD = 5.0 V 2.5 mA
V
IN = 0 V, no load, VDD = 3.6 V 2.0 mA
V
IN = 0 V, no load, VDD = 2.5 V 1.9 mA
V
IN = 0 V, RL = 8 Ω + 33 μH, VDD = 5.0 V 2.5 mA
V
IN = 0 V, RL = 8 Ω + 33 μH, VDD = 3.6 V 2.0 mA
V
IN = 0 V, RL = 8 Ω + 33 μH, VDD = 2.5 V 1.8 mA
Shutdown Current ISD SD = GND 100 nA
GAIN CONTROL
Closed-Loop Gain Gain GAIN = GND 12 dB
GAIN = VDD 6 dB
Input Impedance ZIN SD = VDD, gain = 6 dB or 12 dB 80 kΩ
SHUTDOWN CONTROL
Input Voltage High VIH 1.35 V
Input Voltage Low VIL 0.35 V
Turn-On Time tWU SD rising edge from GND to VDD 12.5 ms
Turn-Off Time tSD SD falling edge from VDD to GND 5 μs
Output Impedance ZOUT SD = GND 100 kΩ
SSM2377
Rev. 0 | Page 4 of 16
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
NOISE PERFORMANCE
Output Voltage Noise en f = 20 Hz to 20 kHz, inputs are ac-grounded,
gain = 6 dB, A-weighted
V
DD = 5.0 V 30 μV
V
DD = 3.6 V 30 μV
Signal-to-Noise Ratio SNR POUT = 1.4 W, RL = 8 Ω, A-weighted 101 dB
1 Although the SSM2377 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
SSM2377
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage VDD
Common-Mode Input Voltage VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Susceptibility 4 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Junction-to-air thermal resistance (θJA) is specified for the worst-
case conditions, that is, a device soldered in a printed circuit
board (PCB) for surface-mount packages. θJA is determined
according to JEDEC JESD51-9 on a 4-layer PCB with natural
convection cooling.
Table 3. Thermal Resistance
Package Type PCB θJA Unit
9-Ball, 1.2 mm × 1.2 mm WLCSP 2S2P 88 °C/W
ESD CAUTION
SSM2377
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
09824-002
A
321
B
C
IN+
SD
GAIN
VDD
OUT–
IN–
GNDVDD
OUT+
BALL A1
CORNER
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
A1 IN+ Noninverting Input.
B1 VDD Power Supply.
C1 IN− Inverting Input.
A2 GAIN Gain Selection Pin.
B2 VDD Power Supply.
C2 SD Shutdown Input. Active low digital input.
A3 OUT− Inverting Output.
B3 GND Ground.
C3 OUT+ Noninverting Output.
SSM2377
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N (%)
OUTPUT POWER (W)
0.001 0.01 0.1 1
R
L
= 8Ω + 33µH
GAIN = 6dB
V
DD
= 2.5V
V
DD
= 5V
09824-003
V
DD
= 3.6V
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N (%)
OUTPUT POWER (W)
09824-004
0.001 0.01 0.1 1
R
L
= 8Ω + 33µH
GAIN = 12dB
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
Figure 3. THD + N vs. Output Power into 8 Ω, Gain = 6 dB Figure 6. THD + N vs. Output Power into 8 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N (%)
OUTPUT POWER (W)
0.001 0.01 0.1 1
R
L
= 4Ω + 15µH
GAIN = 6dB
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
09824-005
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N (%)
OUTPUT POWER (W)
0.001 0.01 0.1 1
R
L
= 4Ω + 15µH
GAIN = 12dB
V
DD
= 2.5V
V
DD
= 5V
09824-006
V
DD
= 3.6V
Figure 4. THD + N vs. Output Power into 4 Ω, Gain = 6 dB Figure 7. THD + N vs. Output Power into 4 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
09824-008
100 1k 10k
V
DD
= 5V
GAIN = 12dB
R
L
= 8Ω + 33µH
1W
0.5W
0.25W
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
09824-007
100 1k 10k
V
DD
= 5V
GAIN = 6dB
R
L
= 8Ω + 33µH
1W
0.5W
0.25W
Figure 5. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 6 dB Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 12 dB
SSM2377
Rev. 0 | Page 8 of 16
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 5V
GAIN = 6dB
R
L
= 4Ω + 15µH
2W
0.5W
1W
09824-009
Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 3.6V
GAIN = 6dB
R
L
=8Ω + 33µH
0.25W
0.125W
0.5W
09824-011
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 3.6V
GAIN = 6dB
R
L
= 4Ω + 15µH
0.25W
0.5W
1W
09824-013
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 5V
GAIN = 12dB
R
L
= 4Ω + 15µH
2W
0.5W
1W
09824-010
Figure 12. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 3.6V
GAIN = 12dB
R
L
=8Ω + 33µH
0.25W
0.5W
09824-012
0.125W
Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 3.6V
GAIN = 12dB
R
L
= 4Ω + 15µH
0.25W
0.5W
1W
09824-014
Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 12 dB
SSM2377
Rev. 0 | Page 9 of 16
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 2.5V
GAIN = 6dB
R
L
= 8Ω + 33µH
0.125W
0.25W
09824-015
0.0625W
Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
VDD = 2.5V
GAIN = 6dB
RL = 4Ω + 15µH
0.125W
0.25W
0.5W
09824-017
Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 6 dB
2.5 3.0 3.5 4.0 4.5 5.0 5.5
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
GAIN = 6dB
NO LOAD
R
L
= 4Ω + 15µH
09824-019
R
L
= 8Ω + 33µH
Figure 17. Quiescent Current vs. Supply Voltage, Gain = 6 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
VDD = 2.5V
GAIN = 12dB
RL = 8Ω + 33µH
0.125W
0.25W
09824-016
0.0625W
Figure 18. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.001
10 100k
THD + N (%)
FREQUENCY (Hz)
100 1k 10k
V
DD
= 2.5V
GAIN = 12dB
R
L
= 4Ω + 15µH
0.125W
0.25W
0.5W
09824-018
Figure 19. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 12 dB
2.5 3.0 3.5 4.0 4.5 5.0 5.5
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
GAIN = 12dB
NO LOAD
R
L
= 4Ω + 15µH
09824-020
R
L
= 8Ω + 33µH
Figure 20. Quiescent Current vs. Supply Voltage, Gain = 12 dB
SSM2377
Rev. 0 | Page 10 of 16
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
f = 1kHz
GAIN = 6dB
R
L
= 8Ω + 33µH
THD + N = 10%
THD + N = 1%
09824-021
Figure 21. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 6 dB
3.5
2.0
2.5
3.0
1.5
1.0
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
f = 1kHz
GAIN = 6dB
R
L
= 4Ω + 15µH
THD + N = 10%
THD + N = 1%
09824-023
Figure 22. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 6 dB
100
90
80
70
60
50
40
30
20
10
0
0 0.20.40.60.81.01.21.41.61.82.0
EFFICIENCY (%)
OUTPUT POWER (W)
V
DD
= 2.5V
V
DD
= 3.6V V
DD
= 5V
R
L
= 8Ω + 33µH
GAIN = 6dB
09824-025
Figure 23. Efficiency vs. Output Power into 8 Ω, Gain = 6 dB
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
f = 1kHz
GAIN = 12dB
R
L
= 8Ω + 33µH
THD + N = 10%
THD + N = 1%
09824-022
Figure 24. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 12 dB
3.5
2.0
2.5
3.0
1.5
1.0
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
f = 1kHz
GAIN = 12dB
R
L
= 4Ω + 15µH
THD + N = 10%
THD + N = 1%
09824-024
Figure 25. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 12 dB
100
90
80
70
60
50
40
30
20
10
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.2
EFFICIENCY (%)
OUTPUT POWER (W)
1.8
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
R
L
= 4Ω + 15µH
GAIN = 6dB
09824-026
Figure 26. Efficiency vs. Output Power into 4 Ω, Gain = 6 dB
SSM2377
Rev. 0 | Page 11 of 16
500
0
02
SUPPLY CURRENT (mA)
OUTPUT POWER (W)
50
100
150
200
250
300
400
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 .0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.21.8
600
500
0
SUPPLY CURRENT (mA)
OUTPUT POWER (W)
100
200
300
400 V
DD
= 2.5V
V
DD
= 3.6V V
DD
= 5V
R
L
= 4Ω + 15µH
GAIN = 6dB
09824-028
450
350
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
R
L
= 8Ω + 33µH
GAIN = 6dB
09824-027
Figure 27. Supply Current vs. Output Power into 8 Ω, Gain = 6 dB Figure 30. Supply Current vs. Output Power into 4 Ω, Gain = 6 dB
0
10 100k
PSRR (dB)
FREQUENCY (Hz)
100 1k 10k
–90
–80
–70
–60
–50
–40
–30
–20
–10
V
DD
= 5V
R
L
= 8Ω + 33µH
GAIN = 12dB
GAIN = 6dB
09824-030
0
–100
10 100k
CMRR (dB)
FREQUENCY (Hz)
100 1k 10k
–90
–80
–70
–60
–50
–40
–30
–20
–10 V
DD
= 5V
R
L
= 8Ω + 33µH
GAIN = 12dB
GAIN = 6dB
09824-029
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
7
6
5
4
3
2
1
0
–1
–8 –4 36322824201612840
VOLTAGE (V)
TIME (ms)
SD INPUT
OUTPUT
09824-031
7
6
5
4
3
2
1
0
–50 –30 –10 10 30 50 70
VOLTAGE (V)
TIME (µs)
SD INPUT
OUTPUT
09824-032
Figure 29. Turn-On Response Figure 32. Turn-Off Response
SSM2377
Rev. 0 | Page 12 of 16
TYPICAL APPLICATION CIRCUITS
FET
DRIVER
MODULATOR
(Σ-Δ)
0.1µF
VDD
OUT+
OUT–
BIAS
IN+
80kΩ
80kΩ
POWER SUPPLY
2.5V TO 5.5V
IN–
INTERNAL
OSCILLATOR
POP/CLICK
AND EMI
SUPPRESSION GND
10µF
22nF
22nF
SHUTDOWN SD
GAIN SELECT
AUDIO IN+
AUDIO IN–
SSM2377
GAIN
GAIN = 6dB OR 12dB
09824-033
Figure 33. Monaural Differential Input Configuration
FET
DRIVER
MODULATOR
(Σ-Δ)
0.1µF
VDD
OUT+
OUT–
BIAS
IN+
80kΩ
80kΩ
POWER SUPPLY
2.5V TO 5.5V
IN–
INTERNAL
OSCILLATOR
POP/CLICK
AND EMI
SUPPRESSION GND
10µF
22nF
22nF
SHUTDOWN SD
GAIN SELECT
AUDIO IN–
SSM2377
GAIN
GAIN = 6dB OR 12dB
09824-034
Figure 34. Monaural Single-Ended Input Configuration
SSM2377
Rev. 0 | Page 13 of 16
THEORY OF OPERATION
OVERVIEW
The SSM2377 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing system cost.
The SSM2377 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square wave output.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM2377 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting
in a number of important benefits.
• Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width
modulators often do.
• Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies,
that is, reducing EMI emissions that might otherwise be
radiated by speakers and long cable traces.
• Due to the inherent spread-spectrum nature of Σ-Δ modu-
lation, the need for oscillator synchronization is eliminated
for designs that incorporate multiple SSM2377 amplifiers.
The SSM2377 also integrates overcurrent and overtemperature
protection.
GAIN SELECTION
The preset gain of the SSM2377 can be set to 6 dB or 12 dB
using the GAIN pin, as shown in Table 5.
Table 5. GAIN Pin Function Description
Gain Setting (dB) GAIN Pin Configuration
6 Tie to VDD
12 Tie to GND
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients
as low as 10 mV can be heard as an audible pop in the speaker.
Clicks and pops can also be classified as undesirable audible
transients generated by the amplifier system and, therefore, as
not coming from the system input signal.
The SSM2377 has a pop-and-click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation from the SD control pin.
EMI NOISE
The SSM2377 uses a proprietary modulation and spread-spectrum
technology to minimize EMI emissions from the device. For
applications that have difficulty passing FCC Class B emission
tests or experience antenna and RF sensitivity problems, the
ultralow EMI architecture of the SSM2377 significantly reduces
the radiated emissions at the Class-D outputs, particularly above
100 MHz. Figure 35 shows the low radiated emissions from the
SSM2377 due to its ultralow EMI architecture.
60
50
40
30
20
10
0
ELECTRIC FIELD STRENGTH (dBµV/m)
30
130
230
330
430
530
FREQUENCY (MHz)
630
730
830
930
1000
+
+
++
09824-035
FCC CLASS B LIMIT
HORIZONTAL POLARIZATION
VERTICAL POLARIZATION
Figure 35. EMI Emissions from the SSM2377
The measurements for Figure 35 were taken in an FCC-certified
EMI laboratory with a 1 kHz input signal, producing 1.0 W of
output power into an 8 Ω load from a 5.0 V supply. The SSM2377
passed FCC Class B limits with 50 cm, unshielded twisted pair
speaker cable. Note that reducing the power supply voltage greatly
reduces radiated emissions.
OUTPUT MODULATION DESCRIPTION
The SSM2377 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to VDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, noise sources are always present.
Due to the constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differ-
ential pulse is generated.
Most of the time, however, the output differential voltage is 0 V,
due to the Analog Devices, Inc., three-level, Σ-Δ output modula-
tion. This feature ensures that the current flowing through the
inductive load is small.
SSM2377
Rev. 0 | Page 14 of 16
When the user wants to send an input signal, an output pulse
(OUT+ and OUT−) is generated to follow the input voltage. The
differential pulse density (VOUT) is increased by raising the input
signal level. Figure 36 depicts three-level, Σ-Δ output modulation
with and without input stimulus.
OUTPUT > 0V
+5V
0V
OUT+
+5V
0V
OUT–
+5V
0V
V
OUT
OUTPUT < 0V
+5V
0V
OUT+
+5V
0V
OUT–
0V
–5V
V
OUT
OUTPUT = 0V
OUT+
+5V
0V
+5V
0V
OUT–
+5V
–5V
0V
V
OUT
0
9824-037
Figure 36. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to decrease
voltage drops and minimize inductance. Ensure that track widths
are at least 200 mil for every inch of track length for lowest DCR,
and use 1 oz or 2 oz copper PCB traces to further reduce IR drops
and inductance. A poor layout increases voltage drops, conse-
quently affecting efficiency. Use large traces for the power supply
inputs and amplifier outputs to minimize losses due to parasitic
trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be directly beneath the
analog power plane, and, similarly, the digital ground plane should
be directly beneath the digital power plane. There should be no
overlap between the analog and digital ground planes or between
the analog and digital power planes.
INPUT CAPACITOR SELECTION
The SSM2377 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If high-
pass filtering is needed at the input, the input capacitor (CIN)
and the input impedance of the SSM2377 form a high-pass filter
with a corner frequency determined by the following equation:
fC = 1/(2π × 80 kΩ × CIN)
The input capacitor value and the dielectric material can
significantly affect the performance of the circuit. Not using
input capacitors can generate a large dc output offset voltage
and degrade the dc PSRR performance.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz. The power supply
input must be decoupled with a good quality, low ESL, low ESR
capacitor, with a minimum value of 4.7 μF. This capacitor bypasses
low frequency noises to the ground plane. For high frequency
transient noises, use a 0.1 μF capacitor as close as possible to the
VDD pins of the device. Placing the decoupling capacitors as close
as possible to the SSM2377 helps to maintain efficient performance.
SSM2377
Rev. 0 | Page 15 of 16
OUTLINE DIMENSIONS
09-23-2010-A
A
B
C
0.645
0.600
0.555
1.280
1.240 SQ
1.200
1
2
3
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
END VIEW
0.300
0.260
0.220
0.80
REF
0.80
REF
0.40
REF
0.415
0.400
0.385
SEATING
PLANE 0.230
0.200
0.170
COPLANARITY
0.05
BALL A1
IDENTIFIER
Figure 37. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1Temperature Range Package Description Package Option2Branding
SSM2377ACBZ-RL −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-4 Y48
SSM2377ACBZ-R7 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-4 Y48
EVAL-SSM2377Z Evaluation Board
1 Z = RoHS Compliant Part.
2 This package option is halide free.
SSM2377
Rev. 0 | Page 16 of 16
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09824-0-5/11(0)
