5962-8760801QZA - TEXAS INSTRUMENTS

32K x 8 Static RAM

CY7C199

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05160 Rev. *B Revised August 3, 2006

Features

•High speed

—12 ns

• Fast tDOE

• CMOS for optimum speed/po we r

• Low active pow er

— 495 mW (Max, “L” version)

• Low standby power

— 0.275 mW (Max, “L” version)

• 2V data retention (“L” version only)

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• A vailable in pb-free 28-pin TSOP I and 28-pin (300-Mil)

Molded DIP

Functional Description

The CY7C199 is a high-performance CMOS static RAM

organized as 32,768 words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE) and active

LOW Output Enable (OE) and tri-state drivers. This device has

an automatic power-down feature, reducing the power

consumption by 81% when deselected. The CY7C199 is in the

standard 300-mil-wide DIP, SOJ, and LCC packages.

An active LOW Write Enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/outpu t pin s

(I/O0 through I/O7) is written into the memory location

addressed by the address present on the address pins (A0

through A14). Reading the device is accomplished by selecting

the device and enabling the outputs, CE and OE active LOW ,

while WE remains inac tive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and Write Enable

(WE) is HIGH. A die coat is used to improve alpha immunity.

Logic Block Diagram Pin Configurations

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

14 15

Top View

DIP

GND

A10

A11

A12

A13

VCC

I/O7

I/O6

I/O5

I/O4

A14

I/O0

I/O1

I/O2

I/O3

ARRAY

I/O7

I/O6

I/O5

I/O4

A11

A13

A12

A14

A10

510

VCC

I/O 7

I/O 6

I/O 5

GND

I/O 2

I/O 1

I/O 4

I/O 0

A14

A10

A11 A13

A12

I/O 3

TSOP I

Top View

(not to scale)

32K x 8

Selection Guide

–12 –15 –20 Unit

Maximum Access Time 12 15 20 ns

Maximum Operating Current 160 155 150 mA

L90

Maximum CMOS Standby Current 10 10 10 mA

L0.05

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CY7C199

Document #: 38-05160 Rev. *B Page 2 of 11

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .............................. ...–65°C to +150°C

Ambient Temperature with

Power Applied...... .. ............... .. ... .............. ...–55°C to +125°C

Supply Voltage to Ground Potential

(Pin 28 to Pin 14)............ ... .............. ... ...........–0.5V to +7.0V

DC Voltage Applied to Outputs

in High-Z S tate[1]....................................–0.5V to VCC + 0.5V

DC Input Vo ltage[1] ...... ... .............. .........–0.5V to VCC + 0.5V

Output Current into Outputs (LOW).............................20 mA

St atic Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current............... ... ... .............. ... ... ........... > 200 mA

Operating Range

Range Ambient Temperature[2] VCC

Commercial 0°C to +70°C 5V ± 10%

Electrical Characteristics Over the Operating Range [3]

Parameter Description Test Conditions -12 -15 -20 UnitMin. Max. Min. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min., IOH=–4.0 mA 2.4 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL=8.0 mA 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.3V 2.2 VCC +

0.3V V

VIL Input LO W Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 V

IIX Input Leakage Current GND < VI < VCC –5 +5 –5 +5 –5 +5 µA

IOZ Output Leakage Current GND < VO < VCC, Output

Disabled –5 +5 –5 +5 –5 +5 µA

ICC VCC Operating Supply

Current VCC = Max.,

IOUT = 0 mA,

f = fMAX = 1/tRC

Com’l 160 155 150 mA

L90mA

ISB1 Automatic CE

Power-down Current—

TTL Inputs

Max. VCC, CE > VIH,

VIN > VIH or

VIN < VIL, f = fMAX

Com’l 30 30 30 mA

L5mA

ISB2 Automatic CE

Power-down Current—

CMOS Inputs

Max. VCC,

CE > VCC – 0.3V

VIN > VCC – 0.3V

or VIN < 0.3V, f = 0

Com’l 10 10 10 mA

L0.05mA

Notes:

1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.

2. TA is the “instant on” case temperature.

3. See the last page of this specification for Group A subgroup testing information.

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CY7C199

Document #: 38-05160 Rev. *B Page 3 of 11

Capacitance[4]

Parameter Description Tes t Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 5.0V 8pF

COUT Output Capacitance 8 pF

AC Test Loads and Waveforms[5]

Data Retention Characteristics Over the Operating Range (L-version only)

Parameter Description Conditions[6] Min. Max. Unit

VDR VCC for Data Retention 2.0 V

ICCDR Data Retention Current VCC = VDR = 2.0V,

CE > VCC – 0.3V,

VIN > VCC – 0.3V or VIN < 0.3V

10 µA

tCDR[4] Chip Deselect to Data Retention Time 0ns

tR [5] Operation Recovery Time 200 µs

3.0V

OUTPUT

R1 481Ω

255 Ω

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

≤tr≤tr

OUTPUT

R1 481Ω

255Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT 1.73V

Equivalent to: THÉ VENIN EQUIVALENT

ALL INPUT PULSES

167Ω

Data Retention Waveform

Notes:

4. Tested initially and after any design or process changes that may affect these parameters.

5. tR< 3 ns for the -12 an d the -15 speeds . tR< 5 ns for the -20 and slower sp eeds.

6. No input may exceed VCC + 0.5V.

3.0V3.0V

tCDR

VDR >2V

DATA RETENTION MODE

VCC

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Document #: 38-05160 Rev. *B Page 4 of 11

Switching Characteristics Over the Operating Range [3,7]

Parameter Description

-12 -15 -20

UnitMin. Max. Min. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 12 15 20 ns

tAA Address to Data Valid 12 15 20 ns

tOHA Data Hold from Address Change 3 3 3 ns

tACE CE LOW to Data Valid 12 15 20 ns

tDOE OE LOW to Data Valid 5 7 9 ns

tLZOE OE LOW to Low-Z[8] 0 0 0 ns

tHZOE OE HIGH to High-Z[8, 9] 5 7 9 ns

tLZCE CE LOW to Low-Z[8] 3 3 3 ns

tHZCE CE HIGH to High-Z[8, 9] 5 7 9 ns

tPU CE LOW to Power-up 0 0 0 ns

tPD CE HIGH to Power-down 12 15 20 ns

Write Cycle[10, 11]

tWC W r it e C ycle Time 12 15 20 ns

tSCE CE LOW to Write End 910 15 ns

tAW Address Set-up to Write End 910 15 ns

tHA Address Hold from Write End 0 0 0 ns

tSA Address Set-up to Write Start 0 0 0 ns

tPWE WE Pulse Width 8 9 15 ns

tSD Data Set-up to Write End 8 9 10 ns

tHD Data Hold from Write End 0 0 0 ns

tHZWE WE LOW to High-Z[9] 7 7 10 ns

tLZWE WE HIGH to Low-Z[8] 3 3 3 ns

Notes:

7. Test conditions assume signal transition time of 3 ns or less f or -12 and -15 sp eeds and 5 ns or less for - 20 and slo wer speeds, timing re ference l evels of 1.5V,

input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.

8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

9. tHZOE, tHZCE, and tHZWE ar e specified with CL = 5 pF as in part (b) of AC Test Loads. T ransition is me asured ±500 mV from steady-st ate voltag e.

10.The internal write time of t he memory i s defi ned by the over lap of CE L OW and W E LOW . Both signals must be LOW to initiate a write and either signal can terminate a

write by goin g HIGH. The dat a input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

11.The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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CY7C199

Document #: 38-05160 Rev. *B Page 5 of 11

Switching Waveforms

Read Cycle No. 1[12, 13]

Read Cycle No. 2 [13, 14]

Notes:

12.Device is continuously selected. OE, CE = VIL.

13.WE is HIGH for read cycle.

14.Address valid prior to or coincident with CE transition LOW .

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE

tHZCE

tPD

HIGH

VCC

SUPPLY

CURRENT

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CY7C199

Document #: 38-05160 Rev. *B Page 6 of 11

Write Cycle No. 1 (WE Controlled)[10, 15, 16]

Write Cycle No. 2 (CE Controlled)[10, 15, 16]

Notes:

15.Data I/O is high impedance if OE = VIH.

16.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN VALID

tWC

tAW

tSA tHA

tHD

tSD

tSCE

DATA I/O

ADDRESS

DATA IN VALID

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CY7C199

Document #: 38-05160 Rev. *B Page 7 of 11

Write Cycle No. 3 (WE Controlled OE LOW)[11, 16]

Switching Waveforms (continued)

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATAIN VALID

Typical DC and AC Characteristics

1.2

1.4

1.0

0.6

0.4

0.2

4.0 4.5 5.0 5.5 6.0

1.6

1.4

1.2

1.0

0.8

–55 25 125

1.2

1.0

0.8

NORMALIZED tAA

120

100

0.0 1.0 2.0 3.0 4.0

OUTPUT SOURCE CURRENT (mA)

SUPPLY VOLTAGE (V)

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIME

vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

0.0

0.8

1.4

1.1

1.0

0.9

4.0 4.5 5.0 5.5 6.0

NORMALIZED t

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME

vs. SUPPLY VOLTAGE

120

140

100

0.0 1.0 2.0 3.0 4.0

OUTPUT SINK CURRENT (mA)

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE

0.6

0.4

0.2

0.0

NORMALIZED ICC,I SB

NORMALIZED ICC,I

ISB

ICC

VCC =5.0V VCC =5.0V

TA=25°C

VCC =5.0V

TA=25°C

ISB

TA=25°C

0.6

0.8

1.3

1.2

VIN =5.0V

TA=25°C

1.4

VCC =5.0V

VIN =5.0V

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CY7C199

Document #: 38-05160 Rev. *B Page 8 of 11

Typical DC and AC Characteristics (continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0 1.0 2.0 3.0 4.0

NORMALIZED I PO

SUPPLY VOLTAGE (V)

TYPICALPOWER-ON CURRENT

vs.SUPPLY VOLTAGE 30.0

25.0

20.0

15.0

10.0

5.0

0 200 400 600 800

DELTA t (ns)

CAPACITANCE (pF)

TYPICAL ACCESS TIMECHANGE

vs. OUTPUT LOADING 1.25

1.00

0.75

10 20 30 40

NORMALIZED I CC

CYCLE FREQUENCY (MHz)

NORMALIZED ICC vs.CYCLETIME

0.0 5.0 0.0 1000 0.50

VCC =4.5V

TA=25°C

VCC =5.0V

TA=25°C

VIN =0.5V

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X Hig h Z Deselect/Power-down Standby (ISB)

L H L Data Out Read Active (ICC)

L L X Data In Write Active (ICC)

L H H High Z Deselect, Output disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

12 CY7C199-12ZXC 51-85071 2 8-pin TSOP I (Pb-free) Commercial

15 CY7C199-15ZXC 51-85071 2 8-pin TSOP I (Pb-free) Commercial

CY7C199L-15ZXC

20 CY7C199-20PXC 51-85014 28-pin (300-Mil) Molded DIP (Pb-free) Commercial

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CY7C199

Document #: 38-05160 Rev. *B Page 9 of 11

Package Diagrams

DIMENSIONS IN INCHES [MM] MIN.

MAX.

SEATING PLANE

0.260[6.60]

0.295[7.49]

0.090[2.28]

0.110[2.79]

0.055[1.39]

0.065[1.65]

0.015[0.38]

0.020[0.50]

0.015[0.38]

0.060[1.52]

0.120[3.05]

0.140[3.55]

0.009[0.23]

0.012[0.30]

0.310[7.87]

0.385[9.78]

0.290[7.36]

0.325[8.25]

0.030[0.76]

0.080[2.03]

0.115[2.92]

0.160[4.06]

0.140[3.55]

0.190[4.82]

1.345[34.16]

1.385[35.18]

3° MIN.

114

15 28

REFERENCE JEDEC MO-095

LEAD END OPTION

SEE LEAD END OPTION

(LEAD #1, 14, 15 & 28)

PACKAGE WEIGHT: 2.15 gms

28-pin (300-Mil) PDIP (51-85014)

51-85014-*D

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Document #: 38-05160 Rev. *B Page 10 of 11

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change without notice. C ypr ess S em icon ductor Corporation assumes no resp onsib ility for the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All products and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

28-pin TSOP Type 1 (8x13.4 mm) (51-85071)

51-85071-*G

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CY7C199

Document #: 38-05160 Rev. *B Page 11 of 11

Document History Page

Document Title: CY7C199 32K x 8 Static RAM

Document Number: 38-05160

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 109971 10/28/01 SZV Change from Spec number: 38-00239 to 38-05160

*A 121730 01/09/02 DFP Updated Product Offering table

*B 492500 See ECN NXR Removed 8 ns, 10 ns, 25 ns , 35 ns, 45 ns speed bin s

Removed 28-Lead (300-Mil) CerDIP, 28-Pin Rectangular Leadless Chip

Carrier, 28-Lead Molded SOIC, 28-Lead Molded SOJ packages from product

offering

Changed the description of IIX from Inp ut Load Cu rrent to Input Leakage

Current in DC Electrical Characteristics table

Removed IOS parameter from DC Electrical Characteristics Table

Updated Ordering Information Table

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