DG528/529
Vishay Siliconix
Document Number: 70068
P-32167—Rev. C, 15-Nov-93 www.vishay.com
1
Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers
FEATURES BENEFITS APPLICATIONS
DLow rDS(on): 270
D44-V Power Supply Rating
DOn-Board Address Latches
DBreak-Before-Make
DLow Leakage—ID(on): 30 pA
DImproved System Accuracy
DMicroporcessor Bus Compatible
DEasily Interfaced
DReduced Crosstalk
DData Acquisition Systems
DAutomatic Test Equipment
DAvionics and Military Systems
DMedical Instrumentation
DESCRIPTION
The DG528 is an 8-channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output
as determined by a 3-bit binary address (A0, A1, A2). DG529,
a 4-channel dual analog multiplexer, is designed to connect
one of four differential inputs to a common differential output
as determined by its 2-bit binary address (A0, A1) logic.
These analog multiplexers have on-chip address and control
latches to simplify design in microprocessor based
applications. Break-before-make switching action protects
against momentary shorting of the input signals. The
DG528/529 are built on the improved PLUS-40 CMOS
process. A buried layer prevents latchup.
The on chip TTL-compatible address latches simplify digital
interface design and reduce board space in data acquisition
systems, process controls, avionics, and ATE.
FUNCTIONAL BLOCK DIAGRAMS AND PIN CONFIGURATIONS
WR
D
RS
S8
A0A1
EN A2
V– GND
S1V+
S2S5
S3S6
S4S7
Dual-In-Line
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top View
910
Latches EN A2
V– GND
S1V+
S2S5
S3S6
PLCC
14
15
16
17
18
8
7
6
5
4
1231920
111091312
Top View
4
D
NC
8
7
A
WR
NC
RS
A
Latches
Decoders/Drivers
0
1
S
S
S
WR
Da
RS
Db
A0A1
EN GND
V– V+
S1a S1b
S2a S2b
S3a S3b
S4a S4b
Dual-In-Line
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top View
910
Latches
DG528 DG528 DG529
DG528/529
Vishay Siliconix
www.vishay.com
2Document Number: 70068
P-32167—Rev. C, 15-Nov-93
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE Ċ DG528
8-Channel Single-Ended Multiplexer
A2A1A0EN WR RS On Switch
Latching
X X X X 1 Maintains previous
switch condition
Reset
X X X X X 0 None (latches cleared)
Transparent Operation
X X X 0 0 1 None
000101 1
001101 2
010101 3
011101 4
100101 5
101101 6
110101 7
111101 8
TRUTH TABLE Ċ DG529
Differential 4-Channel Multiplexer
A0EN WR RS On Switch
Latching
X X 1 Maintains previous
switch condition
Reset
X X X 0 None (latches cleared)
Transparent Operation
X 0 0 1 None
0 1 0 1 1
1 1 0 1 2
0 1 0 1 3
1 1 0 1 4
Logic “0” = VAL v 0.8 V
Logic “1” = VAH w 2.4 V
X = Don’t Care
ORDERING INFORMATION Ċ DG528
Temp Range Package Part Number
_18-Pin Plastic DIP DG528CJ
0 to 70_C20-Pin PLCC DG528DN
–25 to 85_CDG528BK
DG528AK
–55 to 125_C18-Pin CerDIP DG528AK/883
5962-8768901VA
ORDERING INFORMATION Ċ DG529
Temp Range Package Part Number
0 to 70_C18-Pin Plastic DIP DG529CJ
–25 to 85_CDG529BK
–55 to 125_C18-Pin CerDIP DG529AK/883
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V–
V+ 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa, VS, VD(V–) –2 V to (V+) +2 V or. . . . . . . . . . . . . . . . . . . . . . . .
30 mA, whichever occurs first
Current (Any Terminal Except S or D) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Current, S or D 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA. . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature (AK, BK Suffix) –65 to 150_C. . . . . . . . . . . . . .
(CJ, DN Suffix) –65 to 125_C. . . . . . . . . . . . . .
Power Dissipation (Package)b
18-Pin Plastic DIPc470 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-Pin CerDIPd900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin PLCCe800 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/_C above 75_C.
d. Derate 1.2 mW/_C above 75_C.
e. Derate 10 mW/_C above 75_C.
DG528/529
Vishay Siliconix
Document Number: 70068
P-32167—Rev. C, 15-Nov-93 www.vishay.com
3
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_C
B, C, D
Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V, WR = 0
RS = 2.4 V, VIN = 2.4 V, 0.8 FfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 –15 15 V
Drain-Source
On-Resistance rDS(on) VD = , IS = –200 ARoom
Full 270 400
500 450
550
Greatest Change in rDS(on)
Between ChannelsfrDS(on) –10 V < VS < 10 V Room 6 %
Source Off
Leakage Current IS(off) VEN = 0 V, VS = "10 V
VD = #10 V Room
Full "0.005 –1
–50 1
50 –5
–50 5
50
Drain Off VEN = 0 V
"
DG528 Room
Full "0.015 –10
–200 10
200 –20
–200 20
200
Drain Off
Leakage Current ID(off) VD = "10 V
VS = #10 V DG529 Room
Full "0.008 –10
–100 10
100 –20
–100 20
100 nA
Drain On VS = VD = V DG528 Room
Full "0.03 –10
–200 10
200 –20
–200 20
200
Drain On
Leakage Current ID(on) VS = VD = V
VEN = 2.4 V DG529 Room
Full "0.015 –10
–100 10
100 –20
–100 20
100
Digital Control
Logic Input Current VA = 2.4 V Room
Hot –0.002 –10
–30 –10
–30
Input Voltage High IAH VA = 15 V Room
Hot 0.006 10
30 10
30 A
Logic Input Current
Input Voltage Low IAL VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V Room
Hot –0.002 –10
–30 –10
–30
Dynamic Characteristics
Transition Time tTRANS See Figure 5 Room 0.6 1
Break-Before-Make Interval tOPEN See Figure 4 Room 0.2
EN and WR
Turn-On Time tON(EN, WR) See Figures 6 and 7 Room 1 1.5 s
EN and WR
Turn-Off Time tOFF(EN, WR) See Figures 6 and 8 Room 0.4 1
Charge Injection QVS = 0 V, Ry = 0
CL = 10 FRoom 4 pC
Off Isolation OIRR VEN = 0 V, RL = 1 k
CL = 15 pF
VS = 7 VRMS, f = 500 kHz Room 68 dB
Logic Input Capacitance Cin f = 1 MHz Room 2.5
Source Off Capacitance CS(off) VEN = 0 V, VS = 0 V
f = 140 kHz Room 5 pF
VEN = 0 V DG528 Room 25 pF
Drain Off Capacitance CD(off) VD = 0 V
f = 140 kHz DG529 Room 12
Minimum Input Timing Requirements
Write Pulse Width tWFull 300 300
AX, EN Setup Time tSFull 180 180
AX, EN Hold Time tHFull 30 30 ns
Reset Pulse Width tRS VS = 5 V, See Figure 3 Full 500 500
DG528/529
Vishay Siliconix
www.vishay.com
4Document Number: 70068
P-32167—Rev. C, 15-Nov-93
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_C
B, C, D
Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V, WR = 0
RS = 2.4 V, VIN = 2.4 V, 0.8 FfTempbTypcMindMaxdMindMaxdUnit
Power Supplies
Positive Supply Current I+ Room 2.5 2.5
Negative Supply Current I–VEN = 0 V, VA = 0 Room –1.5 –1.5 mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
–20 –15 –10 –505101520
500
400
300
200
100
rDS(on) vs. VD and Power Supply
VD – Drain Voltage (V)
"7.5 V
rDS(on)
– Drain-Source On-Resistance (
"10 V
"15 V
"20 V
TA = 25_C
–15 –10 –5051015
0
–20
–40
–60
Leakage Currents vs. Analog Voltage
ID(off)
ID(on)
IS(off)
"15 V Supplies
TA = 25_C
(pA)I , I
SD
VANALOG – Analog Voltage (V)
2.5
2.0
1.5
1.0
0.5
0
Input Switching Threshold vs.
V+ and V– Supply Voltages
V+, V– Positive and Negative Supplies (V)
TA = 25_C
(V)
T
V
0"5"10 "15 "20
Supply Currents vs. Toggle Frequency
I+, I– (mA)
1 k 10 k 100 k 1 M
4
3
2
1
0
I+
I–
Toggle Frequency (Hz)
)
DG528/529
Vishay Siliconix
Document Number: 70068
P-32167—Rev. C, 15-Nov-93 www.vishay.com
5
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
FIGURE 1.
V+
V+
V+
Latches
EN
CLK
RESET
AX
WR
RS
VREF
DO
Dn
QO
Qn
Level
Shift
V+
V–
V–
V–
V–
GND
V–
V+
D
V–
V+
Decode
S1
V–
V+
V–
V+
V+
Sn
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V
logic interface with input protection circuitry followed by a
latch, level shifter, decoder and finally the switch constructed
with parallel n- and p-channel MOSFETs (see Figure 1).
The logic interface circuit compares the TTL input signal
against a TTL threshold reference voltage. The output of the
comparator feeds the data input of a D type latch. The level
sensitive D latch continuously places the DX input signal on the
QX output when the WR input is low, resulting in transparent
latch operation. As soon as WR returns high, the latches hold
the data last present on the DX input, subject to the minimum
input timing requirements.
Following the latches the QX signals are level shifted and
decoded to provide proper drive levels for the CMOS switches.
This level shifting insures full on/off switch operation for any
analog signal present between the V+ and V– supply rails.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard-wired to the logic supply or to V+ if
one of the channels will always be used (except during a reset)
or it can be tied to address decoding circuitry for memory
mapped operation. The RS pin is used as a master reset. All
latches are cleared regardless of the state of any other latch
or control line. The WR pin is used to transfer the state of the
address control lines to their latches, except during a reset or
when EN is low (see Truth Tables).
FIGURE 2. FIGURE 3.
3 V
0
3 V
0
50%
80% 80%
EN
3 V
0
0
50%
tWtStH
tRStOFF (RS)
WR RS
A0, A1, (A2)80%
VO
Switch
Output
DG528/529
Vishay Siliconix
www.vishay.com
6Document Number: 70068
P-32167—Rev. C, 15-Nov-93
TEST CIRCUITS
FIGURE 4. Break-Before-Make
DG528
DG529
EN
V+
GND V–
+5 V
35 pF
–15 V
+15 V
+2.4 V RS
A0, A1, (A2)D
b, D
All S and Da
WR
300
VO
50
Logic
Input
Switch
Output
VO
VS
tOPEN
tr <20 ns
tf <20 ns
3 V
0 V
50%
80%
0 V
DG528
DG529
FIGURE 5. Transition Time
S1b
S1a – S4a, Da
S2b and S3b
Db
RS
A0
A1
50
WR
300
VO
#10 V
"10 V
S4b
EN
V+
GND V–
35 pF
–15 V
+15 V
+2.4 V
RS S1
S2 – S7
A0
A1
A2
50
WR
300
VO
S8
"10 V
#10 V
EN
V+
GND V–D
35 pF
–15 V
+15 V
+2.4 V
3 V
0 V
Logic
Input
Switch
Output
VS8
VO
tTRANS
tr <20 ns
tf <20 ns
S8 ONS1 ON tTRANS
0 V
VS1
50%
10%
90%
DG528/529
Vishay Siliconix
Document Number: 70068
P-32167—Rev. C, 15-Nov-93 www.vishay.com
7
TEST CIRCUITS
FIGURE 6. Enable tON/tOFF Time
DG528
DG529
RS
EN
+2.4 V S1
S2 – S8
A0
A1
A2
50
WR
300
VO
V+
GND V–D
– 5 V
35 pF
–15 V
+15 V
S1b
S1a – S4a, Da
S2b – S4b
RS
Db
A0
A1
50
WR
300
VO
EN
+2.4 V V+
GND V–
– 5 V
35 pF
–15 V
+15 V
Logic
Input
Switch
Output
VO
tr <20 ns
tf <20 ns
3 V
0 V
0 V
tOFF(EN)
tON(EN)
50%
90%
VO
FIGURE 7. Write Turn-On Time tON(WR)
3 V
0 V
0 V 50%
DG528
DG529
WR
Switch
Output
VO
20%
tON(WR)
A0, A1, (A2)
Db, D
EN
WR
300 W
Remaining
Switches
S1 or S1b
VO
RS
V+
GND V–
+5 V
35 pF
–15 V
+15 V
+2.4 V
DG528/529
Vishay Siliconix
www.vishay.com
8Document Number: 70068
P-32167—Rev. C, 15-Nov-93
TEST CIRCUITS
FIGURE 8. Reset Turn-Off Time tOFF(RS)
3 V
0 V
0 V 50%
DG528
DG529
RS
Switch
Output
VO80%
tOFF(RS)
RS VO
EN
Remaining
Switches
WR
S1 or S1b
Db, D
A0, A1, (A2)
300 W
V+
GND V–
+5 V
35 pF
–15 V
+15 V
+2.4 V
Data Bus
RESET
Address
Decoder
Address
Bus
+5 V
EN
V+
V–
D
+15 V
– 15 V
DG528
Processor
System
Bus
"15 V
Analog
Inputs
Analog
Output
WR
RS
S1
S8
A0, A1, A2 ,
WRITE
FIGURE 9. Bus Interface
DG528/529
Vishay Siliconix
Document Number: 70068
P-32167—Rev. C, 15-Nov-93 www.vishay.com
9
APPLICATION HINTSa
V+ Positive Supply
Voltage
(V)
V– Negative Supply
Voltage
(V)
VIN Logic Input Voltage
VINH(min)/VINL(max)
(V)
VS or VD Analog Voltage
Range
(V)
20
15b
8c
–20
–15
–8 (min)
2.4/0.8
2.4/0.8
2.4/0.8
"20
"15
"8
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
b. Electrical Parameter Chart based on V+ = 15 V, VL = 5 V, VR = GND.
c. Operation below "8 V is not recommended.
The DG528/DG529 minimize the amount of interface
hardware between a microprocessor system bus and the
analog system being controlled or measured. The internal TTL
compatible latches give these multiplexers write-only memory,
that is, they can be programmed to stay in a particular switch
state (e.g., switch 1 on) until the microprocessor determines
it is necessary to turn dif ferent switches on or turn all switches
off (see Figure 9).
The input latches become transparent when WR is held low;
therefore, these multiplexers operate by direct command of
the coded switch state on A2, A1, A0. In this mode the DG528
is identical to the popular DG508A. The same is true of the
DG529 versus the popular DG509A.
During system power-up, RS would be low, maintaining all
eight switches in the off state. After RS returned high the
DG528 maintains all switches in the of f state. When the system
program performs a write operation to the address assigned
to the DG528, the address decoder provides a CS active low
signal which is gated with the WRITE (WR) control signal. At
this time the data on the DAT A BUS (that will determine which
switch to close) is stabilizing. When the WR signal returns to
the high state, (positive edge) the input latches of the DG528
save the data from the DATA BUS. The coded information in
the A0, A1, A2 and EN latches is decoded and the appropriate
switch is turned on.
The EN latch allows all switches to be turned off under program
control. This becomes useful when two or more DG528s are
cascaded to build 16-line and larger multiplexers.
