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AmPDL128G

Data Sheet

Publication Number 25685 Revision BAmendment +2 Issue Date July 29, 2002

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 25685 Rev: BAmendment/+2

Issue Date: July 29, 2002

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29PDL128G

128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous

Read/ Write Flash Memory with VersatileIOTM Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTA G ES

■128Mbit Page Mode device

— Word (16-bit) or double word (32-bit) mode selectable via

WORD# input

— Page size of 8 words/4 double words: Fast page read access

from random locations within the page

■Single power supply operation

— Full Voltage range: 2.7 to 3.6 volt read, erase, and program

operations for battery-powered applications

■Simultaneous Read/Write Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

■FlexBank Architecture

— 4 separate banks, with up to two simultaneous operations

per device

— Organized as two 16 Mbit banks (Bank 1 & 4) and two 48

Mbit banks (Bank 2 & 3)

■VersatileI/OTM (VIO) Control

— Output voltage generated and input voltages tolerated on the

device is determined by the voltage on the VIO pin

■SecSi (Secur ed Silicon) Sector region

— 128 words (64 double words) accessible through a

command sequence

■Both top and bottom boot blocks in one device

■Manufactured on 0.17 µm process technology

■20-year data retention at 125°C

■Minimum 1 million write cycle guarantee per sector

PERFORMA NCE CHA RAC TERISTIC S

■High Performance

—Page access times as fast as 25 ns

—Random access times as fast as 70 ns

■Power consumption (typical values at 10 MHz)

—38 mA active read current

—17 mA program/erase current

—1.5 µA typical standby mode current

SOFTWARE FEATURES

■Software command-set compatible with JEDEC 42 .4

standard

—Backward compatible with Am29F and Am29LV families

■CFI (Common Fla sh Interface) complaint

—Provides device-s pecific i nformation to the system, all owing

host software to easil y reconfigure for different Flash devic es

■Erase Suspend / Erase Resume

—Suspends an erase operation to allow read or program

operations in other sectors of same bank

■Unlock Bypass Program command

—Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■Ready/Busy# pin (RY/BY #)

—Provides a hardware method of detecting program or erase

cycle completion

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

■WP# (Write Protect) input

—At VIL, protects the two top and two bottom sectors,

regardless of sector protect/unprotect status

—At VIH, allows removal of sector protection

—An internal pull up to Vcc is provided

■Persistent Sector Protection

—A command sector protection method to lock combinations

of individual sectors and sector groups to prevent program or

erase operations within that sector

—Sectors can be locked and unlocked in-system at VCC level

■Password Sector Protection

—A sophisticated sector protection method to lock

combinations of individual sectors and sector groups to

prevent program or erase operations within that sector using

a user-defined 64-bit password

■ACC (Acceleration) input provides faster programming

times in a factory setting

■Package options

—80-ball Fortified BGA

2 Am29PDL128G July 29, 2002

PRELIMINARY

GENERAL DESCRIPTION

The Am29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode

and Simultaneous Read/Write Flash memory device orga-

nized as 8 Mwords or 4 M double words (One word is equal

to two bytes). The device is offered in an 80-ball Fortified

BGA package. The word-wide data (x16) appears on

DQ15-DQ0; the double word mode data (x32) appears on

DQ31-D Q0 . This dev ice can be pro gra mm ed in -sys tem or in

standard EP ROM programmers. A 12.0 V VPP is not re-

quired for write or erase operations.

The device offers fast page access times of 25 and 30 ns,

with corresponding random access times of 70 and 80 ns,

respectively, a llowing high speed micro processors to oper-

ate without wait states. To eliminate bus contention the de-

vice has separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

Simultaneous Read/Write Operation with

Zero Latency

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into 4

banks, which can be considered to be four separate memory

arrays as far as ce rtain operations are co ncerned. The de-

vice can improve overall system performance by allowing a

host system to program or erase in one bank, then immedi-

ately and simultaneously read from another bank with zero

latency (with 2 simu ltaneous ope rations oper ating at any

one time). This releases the system from waiting for the

completion of a program or erase operation, greatly improv-

ing system performance.

The device can be organized in both top and bottom sector

configurations (see Table 1).

Page Mode Features

The device is AC timing, input/output, and package compat-

ible with 8 Mbit x16 page mode mask ROM. The pa ge si ze

is 8 words or 4 double words.

After initial page access is accomplished, the page mode op-

eration provides fast read access speed of random locations

within that page.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V

to 3.6 V) for both read and write functions. Internally gener-

ated and regulated voltages are provided for the program

and erase operations.

The device is entirely command set compatible with the

JEDEC 42 .4 single-power -supply Flash s tandard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an int ern al sta te-m ac hin e tha t con trols the er ase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

Device programming occurs by executing the program com-

mand sequence. The Unlock Bypass mode facilitates faster

program ming times by req uirin g on ly two writ e cyc les to pro-

gram da ta inste ad of fo ur. Dev ice eras ure occ urs by e xecut-

ing the erase command sequence.

The hos t sy stem ca n de tec t wh eth er a pro gra m o r era se op-

eration is complete by reading the DQ7 (Data# Polling) and

DQ6 (toggle) status b i ts . After a program or erase cycle has

been completed, the device is ready to read array data or

accept ano the r comm an d.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

Hardwa re data protecti on measu res incl ude a l ow VCC de-

tector that automatically inhibits write opera tions during

power transitions. The hardware sector protection feature

disables bo th program and erase o perations in an y combi-

nati on of s ec t or s o f m em o ry. This c an be a ch i ev e d i n - sy ste m

or via programming equipment.

The Erase Sus pend/Erase Resum e feature enab les the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

The device offers two po wer-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standb y mode. Power con-

sumption is greatly reduced in both these modes.

AMD’s Flash techno logy combine d years of F lash memory

manu facturin g exper ience t o produ ce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electro n injec tion .

Bank/Sector Sizes

Bank Number of

Sectors

Sector Size

(Word/Dbl.

Word) Bank Size

184/2

16 Mbit

31 32/16

2 96 32/16 48 Mbit

3 96 32/16 48 Mbit

484/2

16 Mbit

31 32/16

July 29, 2002 Am29PDL128G 3
PRELIMINARY 
TA BLE OF CONTENTS
Product Selecto r Guide. . . . . . . . . . . . . . . . . . . . .  5
Bloc k  Diag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
Simultaneous Operation Block Diagram . . . . . . .  6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .  7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Orderin g Information. . . . . . . . . . . . . . . . . . . . .  . .  9
Device Bus Operations . . . . . . . . . . . . . . . . . . . .  10
Table 1. Am29PDL128G Device Bus Operations ...................... .....10
Word/Double Word Configuration......................... .................. 10
Requirements for Reading Array Data ................... .. ..............10
Random Read (Non-Page Read) ................. .......... ................10
Pa ge  M o de  R ea d  . .. ... ..................... .......................... ...............1 1
Table 2. Page Select, Double Word Mode ............................... .......11
Table 3. Page Select, Word Mode ..................................................11
Simultaneous Operation .........................................................11
Table 4. Bank Select .......................................................................11
Writing Commands/Command Sequences ................. ...........11
Acc e le ra t ed  P ro g r a m O p era t io n  .... ................. ............ ............12
Autoselect Functions ..............................................................12
Standby Mode..... ........... ........ ................................................ 12
Automatic Sleep Mode  ........................................ .......... .........12
RESET#: Hardware Reset Pin  ...............................................12
Output Disable Mode ..............................................................12
Table 5. Se cto r  Ad d re ss Ta b le .......................................... ..............13
Table 6.  SecSi Sector Add r e sse s................................................20
Autoselect Mode..................................................................... 20
Table 7. Autoselect Codes (High Voltage Method)  ........................20
Table 8. Sector Block Addresses for Protection/Unprotection ........2 1
Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . .  23
Persistent Sector Protection ...................................................24
Persistent Protection Bit (PPB) ...............................................24
Persistent Protection Bit Lock (PPB Lock)  .............................24
Dynamic Protection Bit (DYB)  ................................................24
Table 9. Se cto r  Prote ction Schem es ... ............................................25
Persistent Sector Protection Mode Locking Bit ........ ..............25
Pa ss w ord Pr o te ction  Mo de  ............ ............................... ..........25
Password and Password Mode Locking Bit ...........................25
64-b i t P a ss w o r d ..... ... ..................... ................. ................ ........26
Write Protect (WP#) ................................................................26
Persistent Protection Bit Lock .................................................26
High Voltage Sector Protection  ............. ............ .....................26
Figure 1. In-System Sector Protection/
Sector  Unpro tection Algo rithms....... ............................................... 27
Temporary Sector Unprotect ..................................................28
Figure 2. Temporary Sector Unprotect Operation........................... 28
SecSi™ (Secured Silicon) Sector 
Flash Memory Region ............................................................28
Se cS i  Sec t or P ro te c t io n  Bit   ...... ... ................ ................. ..........2 9
Utilizing Password and SecSi Sector Concurrently ................29
Hardware Data Protection ......................................................29
Low  VCC  Wri te  In h ib i t  ....... ............ ............ ................. ........... .29
Write Pulse “Glitch” Protection  ...............................................29
Logical Inhibit ..........................................................................29
Power-Up Write Inhibit ............................................................29
Common Flash Memor y  Interface (CFI). . . . . . .  30
Tabl e 1 0 . C FI Que r y Id en tifi cat i on  S tri n g............ ................ 30
Table 11. System Interface String................................................... 31
Tabl e 1 2 . D e vi c e  Ge o m e try De finiti o n... ....... ............ ........... 32
Table 13. Primary Vendor-Specific Extended Query...... .. ... 33
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 34
Reading Array Data ................................................................34
Reset Command ................ ........... ............................ ........ ......34
Autoselect Command Sequence ............ ........... .......... ...........34
Enter SecSi Sector/Exit SecSi Sector
Command Sequence ..............................................................34
Double Word/Word Program Command Sequence ................35
Unlock Bypass Command Sequence ....... .......... ....................35
Figur e 3. Progra m Oper a ti o n...... ...................................................  36
Chip  Era se  C omma nd  S e q uen c e  .. ................. ................. .......36
Sector Erase Command Sequence .................................... .. ..36
Erase Suspend/Erase Resume Commands ...........................37
Figure 4. Erase Operation.............................................................. 37
Password Program Command ................................................37
Pass w o rd V e ri fy Co m mand  ....... ........... ................. ............ .....38
Password Protection Mode Locking Bit Program Command ..38
Persistent Sector Protection Mode Locking Bit Program 
Command ............................................................................... 38
SecSi Sector Protection Bit Program Command ....................38
PPB Lock Bit Set Command ...................................................38
DYB Write Command ...................... ..................... .......... .. ......39
Pass w o rd Unlo c k C omma nd  ..... .. .. ...................... ...................3 9
PPB Program Command ........................................................39
All PPB Erase Command ........................................................39
DYB Write Command ...................... ..................... .......... .. ......39
PPB Lock Bit Set Command ...................................................40
PPB Lock Bit Status Command ..............................................40
Sector Protection Status Command .............. ........... .......... ....40
Command Definitions Tables.................................................. 41
Table 14. Memory Array Command Definitions (x32 Mode) ..........41
Table 15. Sector Protection Command Definitions (x32 Mode) ..... 42
Table 16. Memory Array Command Definitions (x16 Mode) ..........43
Table 17. Sector Protection Command Definitions (x16 Mode) ..... 44
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 45
DQ7: Da ta# P o l lin g  ............. ..................... ..................... ..........45
Figur e 5. Data# Polling Algorithm..................................................  45
RY/BY#: Ready/Busy#............................................................ 46
DQ6: Toggle Bit I ....................................................................46
Figure 6. Toggle Bit Algorithm........................................................  46
DQ2: Toggle Bit II ...................................................................47
Reading Toggle Bits DQ6/DQ2 ...............................................47
DQ5: Exceeded Timing Limits ................................................47
DQ3: S e cto r  E ra s e  Time r ............ ............ ............ ............ .......47
Table 18.  Write Ope r a tion Status  ...................................................48
Absolute Maximu m Ratings. . . . . . . . . . . . . . . . . 49
Figure 7. Maximum Negative Overshoot Waveform......................  49
Figure 8. Maximum Positive  Ov ershoot Wavefo r m........................ 49
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figur e 9.  Test Setup... ................................................................... 51
Figure 10. Input Waveforms and Measurement Levels ................. 51
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52
Read-Only Operations  ...........................................................52
Figure 11. Read Operation Timings...............................................  52
Figure 12. Page Read Operation Timin g s... ..................... .............. 53

4 Am29PDL128G July 29, 2002
PRELIMINARY 
Hardware Reset (RESET#) ....................................................54
Figure 13. Reset Timings................................................................ 54
Word/Double Word Configuration (WORD#) ..........................55
Figure 14. WORD# Tim ings for Read Operations. ........ .................. 55
Figure 15. WORD# Timings for Write Operations........................... 55
Erase and Program Operations ..............................................56
Figur e 16 . Progra m Oper a tion Timing s....................... .................... 57
Figure 17. Accelerated Program Timing Diagram........................... 57
Figur e 18 . Chip/S ec to r Era se  Oper a tion Timings........................... 58
Figure 19. Back-to-back Read/Write Cycle Timings....................... 59
Figure 20. Data# Polling Timings (During Embedded Algorithms).. 59
Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 60
Figur e 22 . DQ2 vs. DQ6................................. ................................. 60
Temporary Sector Unprotect ..................................................61
Figure 23. Temporary Sector Unprotect Timing Diagram. .............. 61
Figure 24. Sector/Sector Block Protect and 
Unprotect Timing Diagram.............................................................  62
Alternate CE# Controlled  Erase and Program Operations .....63
Figure 25. Alternate CE# Controlled  Write (Erase/Program) 
Operation Timi ngs................................................ .......................... 64
Erase And Prog ramming Performance. . . . . . . . 65
Latchup C haracteristics. . . . . . . . . . . . . . . . . . . . 65
TSOP Pin and BGA Package Capacitance . . . . . 65
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67
LAB080—80-Ball Fortified Ball Grid Array 
10 x 15 mm package ..............................................................67
Re v is ion Su mmary  . . . . . . . . . . . . . . . . . . . . . . . . 6 8

July 29, 2002 Am29PDL128G 5

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See AC Chara cter istic s secti on for full spe cifi cations.

BLOCK DIAGRAM

Notes:

1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address range is

A21-A-1.

2. RY/BY# is an open drain output.

Part Number Am29PDL128G

Speed Op tion Voltage Range: VCC = 3.0–3.6 V 70R

Voltage Range: VCC = 2.7–3.6 V 70 80 90

Max Access Time, ns (tACC)708090

Max CE# Acce ss, ns (tCE)708090

Max Page Access, ns (tPACC)253035

Max OE# Access, ns (tOE)253040

VCC

VSS

State

Control

Command

Generator

VCC Detector Timer

Erase Voltage

Generator

Input/Output

Buffers

Sector

Switches

Chip Enable

Output Enable

Logic

Y-Gating

Cell Matrix

Address Latch

Y-Decoder

X-Decoder

Data Latch

RESET#

RY/BY# (Note 2)

STB

A21–A2

A1–A0

(A-1)

A3, A4

CE#

OE#

WE#

DQ31–DQ0

VIO

6 Am29PDL128G July 29, 2002

PRELIMINARY

SIMULTANEOUS OPERATION BLOCK DIAGRAM

VCC

VSS

Bank 1 Address

Bank 2 Address

A21–A0

RESET#

WE#

CE#

DQ0–DQ15

DW/W#

WP#

ACC

STATE

CONTROL

COMMAND

RY/BY#

Bank 1

X-Decoder

OE# DW/W#

DQ31–DQ0

Status

Control

A21–A0

A21–A0A21–A0

DQ31–DQ0

Mux

Bank 2

X-Decoder

Y-gate

Bank 3

X-Decoder

Bank 4

X-Decoder

Y-gate

Bank 3 Address

Bank 4 Address

July 29, 2002 Am29PDL128G 7

PRELIMINARY

CONNECTION DIAGRAMS

Special Handling Instructions for BGA

Packages

Special handling is required for Flash Memory products

in molded packages (TSOP, BGA, PLCC, PDIP,

SSOP). The package and/or data integrity may be

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

B2 D2 E2 F2 G2 H2 J2

B3 D3 E3 F3 G3 H3 J3

B4 D4 E4 F4 G4 H4 J4

B5 D5 E5 F5 G5 H5 J5

B6 D6 E6 F6 G6 H6 J6

B7 D7 E7 F7 G7 H7 J7

DQ24 A19VIO

DQ26DQ13VSS

DQ15CE#

DQ8 A16DQ25DQ27DQ12DQ14DQ31/A-1A20

A14 A13DQ10RFUACCDQ29WE#WP#

A12 RFUVSS

RFURESET#DQ18A1A0

VSS A10DQ22DQ20DQ4VSS

DQ16A3

DQ23 A7

A17

A15

RFU

A11

A9DQ6DQ21DQ3VIO

DQ1VCC

B1 D1 E1 F1 G1 H1 J1

DQ7 A6VIO

DQ5DQ19DQ2DQ17DQ0

B8 D8

WORD#

A21

RFU

RY/BY#

C8 E8 F8 G8 H8 J8

DQ9 VCC

A18VSS

DQ11DQ28VIO

DQ30VSS

OE#

80-Ball Fortified BGA

Top View, Balls Facing Down

8 Am29PDL128G July 29, 2002

PRELIMINARY

PIN DESCRIPTION

A21–A0 = 22 Addresses

DQ30–DQ0 = 31 Data Inputs/ Outputs

DQ31/A-1 = DQ31 (Data Input/Output, double

word mode), A-1 (LSB Address In-

put, word mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

WP# = Hardware Write Protect Input

ACC = Acceleration Input

RESET# = Hardware Reset Pin, Active Low

WORD# = Word Enable Input

At VIL, selects 16-bit mode,

At VIH, selects 32-bit mode

RY/B Y# = Ready/Busy Output

VCC = 3.0 Volt-only Single Power Supply

(see Product Selector Guide for

speed options and voltage supply

tolerances)

VIO = Output Buf fer Power Supply

VSS = Device Ground

NC = Pin Not Connected Internally

RFU = Reserved for Future Use

LOGIC SYMBOL

22 32 or 16

DQ31–DQ0

(A-1)

A21–A0

CE#

OE#

WE#

RESET#

WORD#

RY/BY#

ACC

WP#

VIO

July 29, 2002 Am29PDL128G 9

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Valid Combinations

V alid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Am29PDL128G 70 PE I OPTIONAL PR OCESSING

Blank = Standard Pr ocessing

N = 16-byte ESN devices

(Contact an AM D representative for more information)

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

PE = 80-Ball Fortified Ball Grid Array (FBGA)

1 mm pitch, 15 x 10 mm package (LAB080)

SPEED OPTION

See Product Selector Guide and Valid Combi nations

DEVICE NUMBER/DESCRIPTION

Am29PDL128G

128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CM OS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for BGA Packages

Order Number Package Marking

Am29PDL128G70R PEI PD128G70R I

Am29PDL128G70 PD128G70V

Am29PDL128G80 PEI,

PEE PD128G80V I, E

Am29PDL128G90 PD128G90V

10 Am29PDL128G July 29, 2002

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus o perations, which are in itiated through

the internal command register. The command register

itself doe s not occupy a ny address able memo ry loca-

tion. The register is a latch used to store the com-

mands , along with the ad dress and data in formation

needed to execute the command. The contents of the

regis ter serve as inpu ts to the intern al state machin e.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts an d contro l levels they requir e, and the resultin g

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29PDL128G Device Bus Operations

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A21–A0 in double word mode (WORD# = VIH), A21–A-1 in word mode (WORD# = VIL).

2. The sector protect and sector unprot ect f unctions may al so be i mplemente d via programmi ng equipmen t. See the “ Sector

Protection” section .

Word/Double Word Configuration

The WORD # pin controls whether the device data I/O

pins operate in the word or double word configuration.

If the WORD# pin is set at VIH, the device is in double

word configuration, DQ31–DQ0 are active and con-

trolled by CE# and OE#.

If the WOR D# pin is set at VIL, the de vice is in word

configuration, and only data I/O pins DQ15–DQ0 are

active and controlled by CE# and OE#. The data I/O

pins DQ30–DQ16 are tri-stated, and the DQ31 pin is

used as an inp ut for the le ast signific ant address bit

(LSB) function, which is named A-1.

Requirements for Reading Array Data

To read array data from the outputs, the system must

driv e the CE # and OE# pi ns to VIL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at VIH. The WORD# pin determines

whether the devic e output s array data in words or dou-

ble words.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

conten t occurs durin g the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

Re fe r to th e A C Read-Only Operations table for timing

specifications and to Figure 11 for the timing diagram.

ICC1 in the DC Characteristics table represents the ac-

tive current specification for reading array data.

Random Read (Non-Page Read)

Address access time (tACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable ad-

dresses a nd stable CE# to valid data at the outpu t in-

puts. The output enable access time is the delay from

the fall ing edge of the OE# to vali d data at th e output

Operation CE# OE# WE# RESET# WP# Addresses

(Note 1)

DQ31–DQ16

DQ15–

DQ0

WORD#

= VIH

WORD#

= VIL

Read L L H H X AIN DOUT DQ30–DQ16 =

High-Z, DQ31 = A-1 DOUT

Write L H L H X AIN DIN DIN

Standby VCC ±

0.3 V XXVCC ±

0.3 V X X High-Z High-Z High-Z

Output Disable L H H H X X High-Z High-Z High-Z

Reset X X X L X X High-Z High-Z High-Z

Temporary Sector

Unprotect (High Voltage) XXX V

ID XA

IN DIN XD

July 29, 2002 Am29PDL128G 11

PRELIMINARY

inputs (assuming the addresses have been stable for

at least tACC–tOE time).

Page Mode Read

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation . This mode provides faster read ac cess spee d

for random locations within a page. The page size of

the device is 8 words, or 4 double words , with the ap-

propriate page being selec ted by the higher address

bits A21–A2 and the LSB bits A1–A0 (in the double

word mode) and A1 to A-1 (in the word mode) deter-

mining the specific word/double word within that page.

This is an asynchronous operation with the micropro-

cesso r supp lying th e specifi c word or doub le wor d lo-

cation.

The random or initial page access is equal to tACC or

tCE and subsequent page read ac cesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to tPACC. When C E# is

deasserted and reasserted for a subsequent access,

the access time is tACC or tCE. Here again, CE# selects

the device and OE# i s the output control and should

be used to gate data to the output inpu ts if the device

is selected. Fast page mode accesses are obt ained by

keepi ng A21–A2 constant and changing A1 to A0 to

select the specific double word, or changing A1 to A-1

to select the specific word, within that page.

Table 2. Page Select, Double Word Mode

Table 3. Page Select, Word Mode

Simultaneous Operation

The device is capable of reading data from one bank

of memory while a program or erase operation is in

progress in another bank of memory (simultaneous

operation), in addition to the conventional features

(read, program, erase-suspend read, and erase-sus-

pend program). The bank selected can be selected by

bank addresses (A21–A1 9) w i th zero late n c y.

The s imultane ous operatio n can ex ecute multi-fu nc-

tion mode in the same bank.

Table 4. Bank Select

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the WORD# pin determines

whether the device accepts program data in double

words or words. Refer to “Word/Double Word Configu-

ration” for more information.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once a bank enters the Un-

lock B ypass m ode, onl y two wr ite cycles are re quired

to program a double word or word, ins tead of f our. The

“Double Word/Word Program Command Sequence”

section has details on programming data to the device

using both standard and Unlock Bypass command se-

quences.

An erase operat ion can e rase one sector, multipl e sec-

tors, or the entire device. Table 5 indicates t he addres s

space that each sector occ upies. A “bank a ddress” is

the address bits required to uniquely select a bank.

Similarly, a “sector address” refer s to the address bits

required to uniquely s elect a sector. The “Command

Definitions” section has details on erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

ICC2 in the DC Characteristics table represents the ac-

tive current spec ification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Word A1 A0

Double Word 0 0 0

Double Word 1 0 1

Double Word 2 1 0

Double Word 3 1 1

Word A1 A0 A-1

Wor d 0 0 0 0

Wor d 1 0 0 1

Wor d 2 0 1 0

Wor d 3 0 1 1

Wor d 4 1 0 0

Wor d 5 1 0 1

Wor d 6 1 1 0

Wor d 7 1 1 1

Bank A21–A19

Bank 1 000

Bank 2 001, 010, 011

Bank 3 100, 101, 110

Bank 4 111

12 Am29PDL128G July 29, 2002

PRELIMINARY

Accelerated P rog ram Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput at the

factory.

If the sy stem as serts VHH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporar ily unprotects any protected se ctors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would us e a two-cycle pro gram comm and sequence

as required by the Unlock Bypass mode. Removing

VHH from the ACC pin returns the device to normal op-

eration. Note that VHH must not be asserted on ACC

for operations other than accelerated programming, or

device damage may result.

Autoselect Functions

If the system writes the autoselect command se-

quence, the devic e enters the autoselect mo de. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode . Refer to the A utoselect Mode and Autose-

lect Comm and Sequence sections for mo re informa-

tion.

Standby Mode

When the system is not re ading or writing to the de-

vice, it can place the devic e in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.3 V.

(Note that this is a more restricted voltage range tha n

VIH.) If CE# and RESET# are held at VIH, but not within

VCC ± 0.3 V, th e device will be in the standby mod e,

but the standby current will be grea ter. The device re-

quires standard access time (tCE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

ICC3 in the DC Characteristics table represents the

CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Note that durin g automatic s leep mode, OE# m ust be

at VIH before the devi ce redu ces curren t to the state d

sleep mode specification. ICC5 in the DC Characteris-

tics tab le represent s the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin pr ovides a hardware method of re-

setting the device to reading array data. When the RE-

SE T# pin is driv en low for at lea st a period of tRP, th e

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/w rite comm ands for the duration of the RESET #

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is

held at VIL but not within VSS±0.3 V, the standby cur-

rent will be greater.

The RESET# p in may be tied to the system reset cir-

cuitry. A system reset would thu s also reset the Flas h

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESE T# is asser ted duri ng a pr ogram or era se op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not ex-

ecuting (R Y/BY# pi n is “1”), the reset operation is com-

pleted within a time of tREADY (not during Embedded

Algorithms). The system c an read data tRH after the

RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET # pa-

rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from t he device is

disabled. The output pins (except for RY/BY#) are

placed in the high impedance state.

July 29, 2002 Am29PDL128G 13

PRELIMINARY

Table 5. Sector Address Table

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

Bank 1

SA0 00000000000 4/2 00000h–00FFFh 000000h–0007FFh

SA1 00000000001 4/2 01000h–01FFFh 000800h–000FFFh

SA2 00000000010 4/2 02000h–02FFFh 001000h–0017FFh

SA3 00000000011 4/2 03000h–03FFFh 001800h–001FFFh

SA4 00000000100 4/2 04000h–04FFFh 002000h–0027FFh

SA5 00000000101 4/2 05000h–05FFFh 002800h–002FFFh

SA6 00000000110 4/2 06000h–06FFFh 003000h–0037FFh

SA7 00000000111 4/2 07000h–07FFFh 003800h–003FFFh

SA8 00000001XXX 32/16 08000h–0FFFFh 004000h–007FFFh

SA9 00000010XXX 32/16 10000h–17FFFh 008000h–00BFFFh

SA10 00000011XXX 32/16 18000h–1FFFFh 00C000h–00FFFFh

SA11 00000100XXX 32/16 20000h–27FFFh 010000h–013FFFh

SA12 00000101XXX 32/16 28000h–2FFFFh 014000h–017FFFh

SA13 00000110XXX 32/16 30000h–37FFFh 018000h–01BFFFh

SA14 00000111XXX 32/16 38000h–3FFFFh 01C000h–01FFFFh

SA15 00001000XXX 32/16 40000h–47FFFh 020000h–023FFFh

SA16 00001001XXX 32/16 48000h–4FFFFh 024000h–027FFFh

SA17 00001010XXX 32/16 50000h–57FFFh 028000h–02BFFFh

SA18 00001011XXX 32/16 58000h–5FFFFh 02C000h–02FFFFh

SA19 00001100XXX 32/16 60000h–67FFFh 030000h–033FFFh

SA20 00001101XXX 32/16 68000h–6FFFFh 034000h–037FFFh

SA21 00001110XXX 32/16 70000h–77FFFh 038000h–03BFFFh

SA22 00001111XXX 32/16 78000h–7FFFFh 03C000h–03FFFFh

SA23 00010000XXX 32/16 80000h–87FFFh 040000h–043FFFh

SA24 00010001XXX 32/16 88000h–8FFFFh 044000h–047FFFh

SA25 00010010XXX 32/16 90000h–97FFFh 048000h–04BFFFh

SA26 00010011XXX 32/16 98000h–9FFFFh 04C000h–04FFFFh

SA27 00010100XXX 32/16 A0000h–A7FFFh 050000h–053FFFh

SA28 00010101XXX 32/16 A8000h–AFFFFh 054000h–057FFFh

SA29 00010110XXX 32/16 B0000h–B7FFFh 058000h–05BFFFh

SA30 00010111XXX 32/16 B8000h–BFFFFh 05C000h–05FFFFh

SA31 00011000XXX 32/16 C0000h–C7FFFh 060000h–063FFFh

SA32 00011001XXX 32/16 C8000h–CFFFFh 064000h–067FFFh

SA33 00011010XXX 32/16 D0000h–D7FFFh 068000h–06BFFFh

SA34 00011011XXX 32/16 D8000h–DFFFFh 06C000h–06FFFFh

SA35 00011100XXX 32/16 E0000h–E7FFFh 070000h–073FFFh

SA36 00011101XXX 32/16 E8000h–EFFFFh 074000h–077FFFh

SA37 00011110XXX 32/16 F0000h–F7FFFh 078000h–07BFFFh

SA38 00011111XXX 32/16 F8000h–FFFFFh 07C000–07FFFFh

14 Am29PDL128G July 29, 2002

PRELIMINARY

Bank 2

SA39 00100000XXX 32/16 100000h–107FFFh 080000h–083FFFh

SA40 00100001XXX 32/16 108000h–10FFFFh 084000h–087FFFh

SA41 00100010XXX 32/16 110000h–117FFFh 088000h–08BFFFh

SA42 00100011XXX 32/16 118000h–11FFFFh 08C000h–08FFFFh

SA43 00100100XXX 32/16 120000h–127FFFh 090000h–093FFFh

SA44 00100101XXX 32/16 128000h–12FFFFh 094000h–097FFFh

SA45 00100110XXX 32/16 130000h–137FFFh 098000h–09BFFFh

SA46 00100111XXX 32/16 138000h–13FFFFh 09C000h–09FFFFh

SA47 00101000XXX 32/16 140000h–147FFFh 0A0000h–0A3FFFh

SA48 00101001XXX 32/16 148000h–14FFFFh 0A4000h–0A7FFFh

SA49 00101010XXX 32/16 150000h–157FFFh 0A8000h–0ABFFFh

SA50 00101011XXX 32/16 158000h–15FFFFh 0AC000h–0AFFFFh

SA51 00101100XXX 32/16 160000h–167FFFh 0B0000h–0B3FFFh

SA52 00101101XXX 32/16 168000h–16FFFFh 0B4000h–0B7FFFh

SA53 00101110XXX 32/16 170000h–177FFFh 0B8000h–0BBFFFh

SA54 00101111XXX 32/16 178000h–17FFFFh 0BC000h–0BFFFFh

SA55 00110000XXX 32/16 180000h–187FFFh 0C0000h–0C3FFFh

SA56 00110001XXX 32/16 188000h–18FFFFh 0C4000h–0C7FFFh

SA57 00110010XXX 32/16 190000h–197FFFh 0C8000h–0CBFFFh

SA58 00110011XXX 32/16 198000h–19FFFFh 0CC000h–0CFFFFh

SA59 00110100XXX 32/16 1A0000h–1A7FFFh 0D0000h–0D3FFFh

SA60 00110101XXX 32/16 1A8000h–1AFFFFh 0D4000h–0D7FFFh

SA61 00110110XXX 32/16 1B0000h–1B7FFFh 0D8000h–0DBFFFh

SA62 00110111XXX 32/16 1B8000h–1BFFFFh 0DC000h–0DFFFFh

SA63 00111000XXX 32/16 1C0000h–1C7FFFh 0E0000h–0E3FFFh

SA64 00111001XXX 32/16 1C8000h–1CFFFFh 0E4000h–0E7FFFh

SA65 00111010XXX 32/16 1D0000h–1D7FFFh 0E8000h–0EBFFFh

SA66 00111011XXX 32/16 1D8000h–1DFFFFh 0EC000h–0EFFFFh

SA67 00111100XXX 32/16 1E0000h–1E7FFFh 0F0000h–0F3FFFh

SA68 00111101XXX 32/16 1E8000h–1EFFFFh 0F4000h–0F7FFFh

SA69 00111110XXX 32/16 1F0000h–1F7FFFh 0F8000h–0FBFFFh

SA70 00111111XXX 32/16 1F8000h–1FFFFFh 0FC000h–0FFFFFh

SA71 01000000XXX 32/16 200000h–207FFFh 100000h–103FFFh

SA72 01000001XXX 32/16 208000h–20FFFFh 104000h–107FFFh

SA73 01000010XXX 32/16 210000h–217FFFh 108000h–10BFFFh

SA74 01000011XXX 32/16 218000h–21FFFFh 10C000h–10FFFFh

SA75 01000100XXX 32/16 220000h–227FFFh 110000h–113FFFh

SA76 01000101XXX 32/16 228000h–22FFFFh 114000h–117FFFh

SA77 01000110XXX 32/16 230000h–237FFFh 118000h–11BFFFh

SA78 01000111XXX 32/16 238000h–23FFFFh 11C000h–11FFFFh

SA79 01001000XXX 32/16 240000h–247FFFh 120000h–123FFFh

SA80 01001001XXX 32/16 248000h–24FFFFh 124000h–127FFFh

Table 5. Sector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

July 29, 2002 Am29PDL128G 15

PRELIMINARY

Bank 2 (continued)

SA81 01001010XXX 32/16 250000h–257FFFh 128000h–12BFFFh

SA82 01001011XXX 32/16 258000h–25FFFFh 12C000h–12FFFFh

SA83 01001100XXX 32/16 260000h–267FFFh 130000h–133FFFh

SA84 01001101XXX 32/16 268000h–26FFFFh 134000h–137FFFh

SA85 01001110XXX 32/16 270000h–277FFFh 138000h–13BFFFh

SA86 01001111XXX 32/16 278000h–27FFFFh 13C000h–13FFFFh

SA87 01010000XXX 32/16 280000h–287FFFh 140000h–143FFFh

SA88 01010001XXX 32/16 288000h–28FFFFh 144000h–147FFFh

SA89 01010010XXX 32/16 290000h–297FFFh 148000h–14BFFFh

SA90 01010011XXX 32/16 298000h–29FFFFh 14C000h–14FFFFh

SA91 01010100XXX 32/16 2A0000h–2A7FFFh 150000h–153FFFh

SA92 01010101XXX 32/16 2A8000h–2AFFFFh 154000h–157FFFh

SA93 01010110XXX 32/16 2B0000h–2B7FFFh 158000h–15BFFFh

SA94 01010111XXX 32/16 2B8000h–2BFFFFh 15C000h–15FFFFh

SA95 01011000XXX 32/16 2C0000h–2C7FFFh 160000h–163FFFh

SA96 01011001XXX 32/16 2C8000h–2CFFFFh 164000h–167FFFh

SA97 01011010XXX 32/16 2D0000h–2D7FFFh 168000h–16BFFFh

SA98 01011011XXX 32/16 2D8000h–2DFFFFh 16C000h–16FFFFh

SA99 01011100XXX 32/16 2E0000h–2E7FFFh 170000h–173FFFh

SA100 01011101XXX 32/16 2E8000h–2EFFFFh 174000h–177FFFh

SA101 01011110XXX 32/16 2F0000h–2F7FFFh 178000h–17BFFFh

SA102 01011111XXX 32/16 2F8000h–2FFFFFh 17C000h–17FFFFh

SA103 01100000XXX 32/16 300000h–307FFFh 180000h–183FFFh

SA104 01100001XXX 32/16 308000h–30FFFFh 184000h–187FFFh

SA105 01100010XXX 32/16 310000h–317FFFh 188000h–18BFFFh

SA106 01100011XXX 32/16 318000h–31FFFFh 18C000h–18FFFFh

SA107 01100100XXX 32/16 320000h–327FFFh 190000h–193FFFh

SA108 01100101XXX 32/16 328000h–32FFFFh 194000h–197FFFh

SA109 01100110XXX 32/16 330000h–337FFFh 198000h–19BFFFh

SA110 01100111XXX 32/16 338000h–33FFFFh 19C000h–19FFFFh

SA111 01101000XXX 32/16 340000h–347FFFh 1A0000h–1A3FFFh

SA112 01101001XXX 32/16 348000h–34FFFFh 1A4000h–1A7FFFh

SA113 01101010XXX 32/16 350000h–357FFFh 1A8000h–1ABFFFh

SA114 01101011XXX 32/16 358000h–35FFFFh 1AC000h–1AFFFFh

SA115 01101100XXX 32/16 360000h–367FFFh 1B0000h–1B3FFFh

SA116 01101101XXX 32/16 368000h–36FFFFh 1B4000h–1B7FFFh

SA117 01101110XXX 32/16 370000h–377FFFh 1B8000h–1BBFFFh

SA118 01101111XXX 32/16 378000h–37FFFFh 1BC000h–1BFFFFh

SA119 01110000XXX 32/16 380000h–387FFFh 1C0000h–1C3FFFh

Table 5. Sector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

16 Am29PDL128G July 29, 2002

PRELIMINARY

Bank 2 (continued)

SA120 01110001XXX 32/16 388000h–38FFFFh 1C4000h–1C7FFFh

SA121 01110010XXX 32/16 390000h–397FFFh 1C8000h–1CBFFFh

SA122 01110011XXX 32/16 398000h–39FFFFh 1CC000h–1CFFFFh

SA123 01110100XXX 32/16 3A0000h–3A7FFFh 1D0000h–1D3FFFh

SA124 01110101XXX 32/16 3A8000h–3AFFFFh 1D4000h–1D7FFFh

SA125 01110110XXX 32/16 3B0000h–3B7FFFh 1D8000h–1DBFFFh

SA126 01110111XXX 32/16 3B8000h–3BFFFFh 1DC000h–1DFFFFh

SA127 01111000XXX 32/16 3C0000h–3C7FFFh 1E0000h–1E3FFFh

SA128 01111001XXX 32/16 3C8000h–3CFFFFh 1E4000h–1E7FFFh

SA129 01111010XXX 32/16 3D0000h–3D7FFFh 1E8000h–1EBFFFh

SA130 01111011XXX 32/16 3D8000h–3DFFFFh 1EC000h–1EFFFFh

SA131 01111100XXX 32/16 3E0000h–3E7FFFh 1F0000h–1F3FFFh

SA132 01111101XXX 32/16 3E8000h–3EFFFFh 1F4000h–1F7FFFh

SA133 01111110XXX 32/16 3F0000h–3F7FFFh 1F8000h–1FBFFFh

SA134 01111111XXX 32/16 3F8000h–3FFFFFh 1FC000h–1FFFFFh

Bank 3

SA135 10000000XXX 32/16 400000h–407FFFh 200000h–203FFFh

SA136 10000001XXX 32/16 408000h–40FFFFh 204000h–207FFFh

SA137 10000010XXX 32/16 410000h–417FFFh 208000h–20BFFFh

SA138 10000011XXX 32/16 418000h–41FFFFh 20C000h–20FFFFh

SA139 10000100XXX 32/16 420000h–427FFFh 210000h–213FFFh

SA140 10000101XXX 32/16 428000h–42FFFFh 214000h–217FFFh

SA141 10000110XXX 32/16 430000h–437FFFh 218000h–21BFFFh

SA142 10000111XXX 32/16 438000h–43FFFFh 21C000h–21FFFFh

SA143 10001000XXX 32/16 440000h–447FFFh 220000h–223FFFh

SA144 10001001XXX 32/16 448000h–44FFFFh 224000h–227FFFh

SA145 10001010XXX 32/16 450000h–457FFFh 228000h–22BFFFh

SA146 10001011XXX 32/16 458000h–45FFFFh 22C000h–22FFFFh

SA147 10001100XXX 32/16 460000h–467FFFh 230000h–233FFFh

SA148 10001101XXX 32/16 468000h–46FFFFh 234000h–237FFFh

SA149 10001110XXX 32/16 470000h–477FFFh 238000h–23BFFFh

SA150 10001111XXX 32/16 478000h–47FFFFh 23C000h–23FFFFh

SA151 10010000XXX 32/16 480000h–487FFFh 240000h–243FFFh

SA152 10010001XXX 32/16 488000h–48FFFFh 244000h–247FFFh

SA153 10010010XXX 32/16 490000h–497FFFh 248000h–24BFFFh

SA154 10010011XXX 32/16 498000h–49FFFFh 24C000h–24FFFFh

SA155 10010100XXX 32/16 4A0000h–4A7FFFh 250000h–253FFFh

SA156 10010101XXX 32/16 4A8000h–4AFFFFh 254000h–257FFFh

SA157 10010110XXX 32/16 4B0000h–4B7FFFh 258000h–25BFFFh

SA158 10010111XXX 32/16 A48000h–4BFFFFh 25C000h–25FFFFh

Table 5. Sector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

July 29, 2002 Am29PDL128G 17

PRELIMINARY

Bank 3 (continued)

SA159 10011000XXX 32/16 4C0000h–4C7FFFh 260000h–263FFFh

SA160 10011001XXX 32/16 4C8000h–4CFFFFh 264000h–267FFFh

SA161 10011010XXX 32/16 4D0000h–4D7FFFh 268000h–26BFFFh

SA162 10011011XXX 32/16 4D8000h–4DFFFFh 26C000h–26FFFFh

SA163 10011100XXX 32/16 4E0000h–4E7FFFh 270000h–273FFFh

SA164 10011101XXX 32/16 4E8000h–4EFFFFh 274000h–277FFFh

SA165 10011110XXX 32/16 4F0000h–4F7FFFh 278000h–27BFFFh

SA166 10011111XXX 32/16 4F8000h–4FFFFFh 27C000h–27FFFFh

SA167 10100000XXX 32/16 500000h–507FFFh 280000h–283FFFh

SA168 10100001XXX 32/16 508000h–50FFFFh 284000h–287FFFh

SA169 10100010XXX 32/16 510000h–517FFFh 288000h–28BFFFh

SA170 10100011XXX 32/16 518000h–51FFFFh 28C000h–28FFFFh

SA171 10100100XXX 32/16 520000h–527FFFh 290000h–293FFFh

SA172 10100101XXX 32/16 528000h–52FFFFh 294000h–297FFFh

SA173 10100110XXX 32/16 530000h–537FFFh 298000h–29BFFFh

SA174 10100111XXX 32/16 538000h–53FFFFh 29C000h–29FFFFh

SA175 10101000XXX 32/16 540000h–547FFFh 2A0000h–2A3FFFh

SA176 10101001XXX 32/16 548000h–54FFFFh 2A4000h–2A7FFFh

SA177 10101010XXX 32/16 550000h–557FFFh 2A8000h–2ABFFFh

SA178 10101011XXX 32/16 558000h–55FFFFh 2AC000h–2AFFFFh

SA179 10101100XXX 32/16 560000h–567FFFh 2B0000h–2B3FFFh

SA180 10101101XXX 32/16 568000h–56FFFFh 2B4000h–2B7FFFh

SA181 10101110XXX 32/16 570000h–577FFFh 2B8000h–2BBFFFh

SA182 10101111XXX 32/16 578000h–57FFFFh 2BC000h–2BFFFFh

SA183 10110000XXX 32/16 580000h–587FFFh 2C0000h–2C3FFFh

SA184 10110001XXX 32/16 588000h–58FFFFh 2C4000h–2C7FFFh

SA185 10110010XXX 32/16 590000h–597FFFh 2C8000h–2CBFFFh

SA186 10110011XXX 32/16 598000h–59FFFFh 2CC000h–2CFFFFh

SA187 10110100XXX 32/16 5A0000h–5A7FFFh 2D0000h–2D3FFFh

SA188 10110101XXX 32/16 5A8000h–5AFFFFh 2D4000h–2D7FFFh

SA189 10110110XXX 32/16 5B0000h–5B7FFFh 2D8000h–2DBFFFh

SA190 10110111XXX 32/16 5B8000h–5BFFFFh 2DC000h–2DFFFFh

SA191 10111000XXX 32/16 5C0000h–5C7FFFh 2E0000h–2E3FFFh

SA192 10111001XXX 32/16 5C8000h–5CFFFFh 2E4000h–2E7FFFh

SA193 10111010XXX 32/16 5D0000h–5D7FFFh 2E8000h–2EBFFFh

SA194 10111011XXX 32/16 5D8000h–5DFFFFh 2EC000h–2EFFFFh

SA195 10111100XXX 32/16 5E0000h–5E7FFFh 2F0000h–2F3FFFh

SA196 10111101XXX 32/16 5E8000h–5EFFFFh 2F4000h–2F7FFFh

SA197 10111110XXX 32/16 5F0000h–5F7FFFh 2F8000h–2FBFFFh

Table 5. Sector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

18 Am29PDL128G July 29, 2002

PRELIMINARY

Bank 3 (continued)

SA198 10111111XXX 32/16 5F8000h–5FFFFFh 2FC000h–2FFFFFh

SA199 11000000XXX 32/16 600000h–607FFFh 300000h–303FFFh

SA200 11000001XXX 32/16 608000h–60FFFFh 304000h–307FFFh

SA201 11000010XXX 32/16 610000h–617FFFh 308000h–30BFFFh

SA202 11000011XXX 32/16 618000h–61FFFFh 30C000h–30FFFFh

SA203 11000100XXX 32/16 620000h–627FFFh 310000h–313FFFh

SA204 11000101XXX 32/16 628000h–62FFFFh 314000h–317FFFh

SA205 11000110XXX 32/16 630000h–637FFFh 318000h–31BFFFh

SA206 11000111XXX 32/16 638000h–63FFFFh 31C000h–31FFFFh

SA207 11001000XXX 32/16 640000h–647FFFh 320000h–323FFFh

SA208 11001001XXX 32/16 648000h–64FFFFh 324000h–327FFFh

SA209 11001010XXX 32/16 650000h–657FFFh 328000h–32BFFFh

SA210 11001011XXX 32/16 658000h–65FFFFh 32C000h–32FFFFh

SA211 11001100XXX 32/16 660000h–667FFFh 330000h–333FFFh

SA212 11001101XXX 32/16 668000h–66FFFFh 334000h–337FFFh

SA213 11001110XXX 32/16 670000h–677FFFh 338000h–33BFFFh

SA214 11001111XXX 32/16 678000h–67FFFFh 33C000h–33FFFFh

SA215 11010000XXX 32/16 680000h–687FFFh 340000h–343FFFh

SA216 11010001XXX 32/16 688000h–68FFFFh 344000h–347FFFh

SA217 11010010XXX 32/16 690000h–697FFFh 348000h–34BFFFh

SA218 11010011XXX 32/16 698000h–69FFFFh 34C000h–34FFFFh

SA219 11010100XXX 32/16 6A0000h–6A7FFFh 350000h–353FFFh

SA220 11010101XXX 32/16 6A8000h–6AFFFFh 354000h–357FFFh

SA221 11010110XXX 32/16 6B0000h–6B7FFFh 358000h–35BFFFh

SA222 11010111XXX 32/16 6B8000h–6BFFFFh 35C000h–35FFFFh

SA223 11011000XXX 32/16 6C0000h–6C7FFFh 360000h–363FFFh

SA224 11011001XXX 32/16 6C8000h–6CFFFFh 364000h–367FFFh

SA225 11011010XXX 32/16 6D0000h–6D7FFFh 368000h–36BFFFh

SA226 11011011XXX 32/16 6D8000h–6DFFFFh 36C000h–36FFFFh

SA227 11011100XXX 32/16 6E0000h–6E7FFFh 370000h–373FFFh

SA228 11011101XXX 32/16 6E8000h–6EFFFFh 374000h–377FFFh

SA229 11011110XXX 32/16 6F0000h–6F7FFFh 378000h–37BFFFh

SA230 11011111XXX 32/16 6F8000h–6FFFFFh 37C000h–37FFFFh

Table 5. Sector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

July 29, 2002 Am29PDL128G 19

PRELIMINARY

Note: The address range is A21:A-1 in word mode (WORD#=VIL) or A21:A0 in doubl e word mode (WORD#=VIH). Address bits A21:A1 1 uniquely

select a sector; address bits A21:A19 uniquely select a bank.

Bank 4

SA231 11100000XXX 32/16 700000h–707FFFh 380000h–383FFFh

SA232 11100001XXX 32/16 708000h–70FFFFh 384000h–387FFFh

SA233 11100010XXX 32/16 710000h–717FFFh 388000h–38BFFFh

SA234 11100011XXX 32/16 718000h–71FFFFh 38C000h–38FFFFh

SA235 11100100XXX 32/16 720000h–727FFFh 390000h–393FFFh

SA236 11100101XXX 32/16 728000h–72FFFFh 394000h–397FFFh

SA237 11100110XXX 32/16 730000h–737FFFh 398000h–39BFFFh

SA238 11100111XXX 32/16 738000h–73FFFFh 39C000h–39FFFFh

SA239 11101000XXX 32/16 740000h–747FFFh 3A0000h–3A3FFFh

SA240 11101001XXX 32/16 748000h–74FFFFh 3A4000h–3A7FFFh

SA241 11101010XXX 32/16 750000h–757FFFh 3A8000h–3ABFFFh

SA242 11101011XXX 32/16 758000h–75FFFFh 3AC000h–3AFFFFh

SA243 11101100XXX 32/16 760000h–767FFFh 3B0000h–3B3FFFh

SA244 11101101XXX 32/16 768000h–76FFFFh 3B4000h–3B7FFFh

SA245 11101110XXX 32/16 770000h–777FFFh 3B8000h–3BBFFFh

SA246 11101111XXX 32/16 778000h–77FFFFh 3BC000h–3BFFFFh

SA247 11110000XXX 32/16 780000h–787FFFh 3C0000h–3C3FFFh

SA248 11110001XXX 32/16 788000h–78FFFFh 3C4000h–3C7FFFh

SA249 11110010XXX 32/16 790000h–797FFFh 3C8000h–3CBFFFh

SA250 11110011XXX 32/16 798000h–79FFFFh 3CC000h–3CFFFFh

SA251 11110100XXX 32/16 7A0000h–7A7FFFh 3D0000h–3D3FFFh

SA252 11110101XXX 32/16 7A8000h–7AFFFFh 3D4000h–3D7FFFh

SA253 11110110XXX 32/16 7B0000h–7B7FFFh 3D8000h–3DBFFFh

SA254 11110111XXX 32/16 7B8000h–7BFFFFh 3DC000h–3DFFFFh

SA255 11111000XXX 32/16 7C0000h–7C7FFFh 3E0000h–3E3FFFh

SA256 11111001XXX 32/16 7C8000h–7CFFFFh 3E4000h–3E7FFFh

SA257 11111010XXX 32/16 7D0000h–7D7FFFh 3E8000h–3EBFFFh

SA258 11111011XXX 32/16 7D8000h–7DFFFFh 3EC000h–3EFFFFh

SA259 11111100XXX 32/16 7E0000h–7E7FFFh 3F0000h–3F3FFFh

SA260 11111101XXX 32/16 7E8000h–7EFFFFh 3F4000h–3F7FFFh

SA261 11111110XXX 32/16 7F0000h–7F7FFFh 3F8000h–3FBFFFh

SA262 11111111000 4/2 7F8000h–7F8FFFh 3FC000h–3FC7FFh

SA263 11111111001 4/2 7F9000h–7F9FFFh 3FC800h–3FCFFFh

SA264 11111111010 4/2 7FA000h–7FAFFFh 3FD000h–3FD7FFh

SA265 11111111011 4/2 7FB000h–7FBFFFh 3FD800h–3FDFFFh

SA266 11111111100 4/2 7FC000h–7FCFFFh 3FE000h–3FE7FFh

SA267 11111111101 4/2 7FD000h–7FDFFFh 3FE800h–3FEFFFh

SA268 11111111110 4/2 7FE000h–7FEFFFh 3FF000h–3FF7FFh

SA269 11111111111 4/2 7FF000h–7FFFFFh 3FF800h–3FFFFFh

Table 5. Sector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

20 Am29PDL128G July 29, 2002

PRELIMINARY

Table 6. SecSi Sector Addresses

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, an d sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for program ming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

When using programming equipm ent, the autoselect

mode requires VID on address pin A9. Address pins

must be as shown in Table 7 . In addition, when verify-

ing sector p rotection, the sector address must appear

on the appropriate highest order address bits (see

Table 5). Table 7 shows the remaining address bits

that are don’t care. When all necessary bits have been

set as required, the programming equipment may then

read the corresponding identifier code on DQ7–DQ0.

However, the autoselect codes can also be accessed

in-system throug h the command register, for instances

when the device is erased or programmed in a system

without access to high voltage on the A9 pin. The

command sequence is illustrated in Tables 14 and 16.

Note that if a Bank Address (BA) on address bits A21,

A20, and A19 is assert ed during the t hird write cyc le of

the autoselect command, the host system can read

autoselect data that bank and then immediately read

array data from the other bank, without exiting the au-

toselect mode.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Tables 14 and 16. T his

method does not require VID. Refer to the Autoselect

Command Sequence section for more information.

Table 7. Autoselect Codes (High Voltage Method)

Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may al so be accessed in-system via comma nd se quence s.

Device Sector Size (x32)

Address Range (x16)

Address Range

Am29PDL128G 128 words/64 double

words 000000h–00003Fh 000000h–00007Fh

Description CE# OE# WE#

A21

A11 A10 A9 A8 A7 A6

A4 A3 A2 A1 A0

DQ31 to DQ8

(Word/Double

Word) DQ7

to DQ0

Manufacturer ID:

AMD LLHXX

VID X X L X L L L L 000000h 01h

Device ID

Read

Cycle 1

LLHXX

VID XL

LLLH 22h/

222222h 7Eh

Read

Cycle 2 LHHHL

22h/

222222h 0Dh

Read

Cycle 3 LHHHH

22h/

222222h 00h

Sector Protection

Verification LLHSAX

VID XLLHHLHL 00h/

000000h 01h (protected),

00h (unprotected)

SecSi Indicator Bit

(DQ7) LLHXX

VID XXLXLLHH 00h/

000000h

80h

(factory locked),

00h (not factory

locked)

July 29, 2002 Am29PDL128G 21

PRELIMINARY

Table 8. Sector Block Addresses for Protection/Unprotection

Sector

Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors

SGA0 00000000000 SA0

SGA1 00000000001 SA1

SGA2 00000000010 SA2

SGA3 00000000011 SA3

SGA4 00000000100 SA4

SGA5 00000000101 SA5

SGA6 00000000110 SA6

SGA7 00000000111 SA7

SGA8 000000

X X X SA8 to SA1010

SGA9 000001XXXXX SA11 to SA14

SGA10 000010XXXXX SA15 to SA18

SGA11 000011XXXXX SA19 to SA22

SGA12 000100XXXXX SA23 to SA26

SGA13 000101XXXXX SA27 to SA30

SGA14 000110XXXXX SA31 to SA34

SGA15 000111XXXXX SA35 to SA38

SGA16 001000XXXXX SA39 to SA42

SGA17 001001XXXXX SA43 to SA46

SGA18 001010XXXXX SA47 to SA50

SGA19 001011XXXXX SA51 to SA54

SGA20 001100XXXXX SA55 to SA58

SGA21 001101XXXXX SA59 to SA62

SGA22 001110XXXXX SA63 to SA66

SGA23 001111XXXXX SA67 to SA70

SGA24 010000XXXXX SA71 to SA74

SGA25 010001XXXXX SA75 to SA78

SGA26 010010XXXXX SA79 to SA82

SGA27 010011XXXXX SA83 to SA86

SGA28 010100XXXXX SA87 to SA90

SGA29 010101XXXXX SA91 to SA94

SGA30 010110XXXXX SA95 to SA98

SGA31 010111XXXXX SA99 to SA102

22 Am29PDL128G July 29, 2002

PRELIMINARY

SGA32 011000XXXXX SA103 to SA106

SGA33 011001XXXXX SA107 to SA110

SGA34 011010XXXXX SA111 to SA114

SGA35 011011XXXXX SA115 to SA118

SGA36 011100XXXXX SA119 to SA122

SGA37 011101XXXXX SA123 to SA126

SGA38 011110XXXXX SA127 to SA130

SGA39 011111XXXXX SA131 to SA134

SGA40 100000XXXXX SA135 to SA138

SGA41 100001XXXXX SA139 to SA142

SGA42 100010XXXXX SA143 to SA146

SGA43 100011XXXXX SA147 to SA150

SGA44 100100XXXXX SA151 to SA154

SGA45 100101XXXXX SA155 to SA158

SGA46 100110XXXXX SA159 to SA162

SGA47 100111XXXXX SA163 to SA166

SGA48 101000XXXXX SA167 to SA170

SGA49 101001XXXXX SA171 to SA174

SGA50 101010XXXXX SA175 to SA178

SGA51 101011XXXXX SA179 to SA182

SGA52 101100XXXXX SA183 to SA186

SGA53 101101XXXXX SA187 to SA190

SGA54 101110XXXXX SA191 to SA194

SGA55 101111XXXXX SA195 to SA198

SGA56 110000XXXXX SA199 to SA202

SGA57 110001XXXXX SA203 to SA206

SGA58 110010XXXXX SA207 to SA210

SGA59 110011XXXXX SA211 to SA214

SGA60 110100XXXXX SA215 to SA218

SGA61 110101XXXXX SA219 to SA222

SGA62 110110XXXXX SA223 to SA226

SGA63 110111XXXXX SA227 to SA230

SGA64 111000XXXXX SA231 to SA234

SGA65 111001XXXXX SA235 to SA238

Table 8. Sector Block Addresses for Protection/Unprotection (Continued)

Sector

Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors

July 29, 2002 Am29PDL128G 23

PRELIMINARY

SECTOR PROTECTION

The Am29PDL128G features several levels of sector

protection, which can disable both the program and

erase operations in certain sectors or sector groups:

Persistent Sector Protection

A command sector protection method that replaces

the old 12 V controlled protection method.

Password Sector Protection

A highly sophisticated protection method that requires

a passw ord befo re chang es to certain sectors o r sec-

tor groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase

operations in sectors 0, 1, 268, and 269.

All parts default to operate in the P ersistent Sector

Prote ction mode. The cus tomer must then cho ose if

the Persistent or Password Protection method is most

desirable. There are two one-time programmable

non-volatile bits that define which sector protection

method will be used. If the customer decides to con-

tinue using the Persistent Sector Protection method,

they must set the Persistent Sector Protection

Mode Locking Bit. This will pe rmanently s et the part

to operate only using Persistent Sector Protection. If

the customer decides to use the password method,

they must set the Password Mode Locking Bit. This

will permanently set the part to operate only using

password sector protection.

It is important to remember that setting either the Per-

sistent Sector Protection Mo de Locking Bit or the

Password Mode Locking Bit permanently selects

the protection mode. It is not possible to switch be-

tween the two methods once a locking bit has been

set. It is important that one mode is explicitly se-

lected when the device is first programmed, rather

than relying on the default mode alone. This is so

that it is not po ssible for a system pro gram or virus to

later set the Password Mode Locking Bit, which would

cause an u nexpected sh ift from the default Pe rsistent

Sector Protection Mode into the Password Protection

Mode.

The WP# Hardware Protection feature is always avail-

able, independent of the software managed protection

method chosen.

The device is shipped with all sectors unprotected.

AMD o ffers the option of programm ing and p rotecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

SGA66 111010XXXXX SA239 to SA242

SGA67 111011XXXXX SA243 to SA246

SGA68 111100XXXXX SA247 to SA250

SGA69 111101XXXXX SA251 to SA254

SGA70 111110XXXXX SA255 to SA258

SGA71 111111

X X X SA259 to SA26101

SGA72 11111111000 SA262

SGA73 11111111001 SA263

SGA74 11111111010 SA264

SGA75 11111111011 SA265

SGA76 11111111100 SA266

SGA77 11111111101 SA267

SGA78 11111111110 SA268

SGA79 11111111111 SA269

Table 8. Sector Block Addresses for Protection/Unprotection (Continued)

Sector

Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors

24 Am29PDL128G July 29, 2002

PRELIMINARY

It is possible to determine whether a sector is pro-

tected or unprotected. See Autoselect Mode for de-

tails.

Persistent Sector Protection

The Persistent Sector Protection method replaces the

old 12 V controlled protection method while at the

same time e nhanci ng flexibi lity by provid ing thre e dif-

ferent sector protec tion states:

■Persistently Locked—A sector is protected and

cannot be changed.

■Dynamically Locked—The sector is protect ed and

can be changed by a simple command

■Unlocked—The sector is unprotected and can be

changed by a simple command

In order to achieve these states, three types of “bits”

are going to be used:

Persistent Pro t ection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is as-

signed to a maximum four sec tors (see the sector ad-

dress tables for specific sector protection groupings).

All 8 Kbyte boot-block sectors have individual sector

Persistent Protection Bits (PPBs) for greater flexibility.

Each PPB is individually modifiable through the PPB

Write Command.

Note: If a PPB requires erasure, all of the sect or PPBs

must first be preprogrammed prior to PPB erasing. All

PPBs era se in para llel, un like program ming whe re in-

dividual PPBs are programmable. It is the responsibil-

ity of the user to perform the preprogramming

operatio n. Otherwise, a n already er ased secto r PPBs

has the potential of being over-erased. There is no

hardware mechanism to prevent sector PPBs

over-erasure.

Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to “1”, the PPBs cannot

be changed. When cleared (“0”), the PPBs are

chang eable. Th ere is only on e PPB Lo ck bit per d e-

vice. The PPB Lock is cleared after power-up or hard-

ware reset. There is no command sequence to unlock

the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector.

After power-up or hardware reset, the contents of all

DYBs is “0”. Each DYB is individually modifiable

through the DYB Write Command.

When the parts are first shipped, the PPBs are

cleared, the DYB s are cleared, and PPB L ock is de-

faulted to power up in the cleared state – meaning the

PPBs are changeable.

When the device is first powered on the DYBs power

up cleared (sectors not protected). The Protection

State for each sector is determ ined b y the logi cal OR

of the PPB and the DYB related to that sector. For the

sectors that have the PPBs cleared, the DYBs control

whether or not the sec tor is protec ted or unpro tected.

By issuing the DYB Write command sequences, the

DYBs will be set or cleared, thus placing each sector

in the protected or unprotected state. The se are the

so-called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to

switch back and forth between the protected and un-

protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does

not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared

as often as needed.

The PPBs allow for a more static, and difficult to

change, level of prot ection. The PPBs ret ain t heir st ate

across powe r cycles because they are Non-Volatile.

Individual PPBs are set with a command but must all

be cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

The PPB Loc k bit adds an add itional level of protec-

tion. Once all PPBs are programmed to the desired

settings, the PPB Lock may be set to “1”. Set ting the

PPB Lock disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock Bit

locks the PP Bs into their c urrent s tate. The only way to

clear the PPB Lock is to go through a power cycle.

System boot code can determine if any changes to the

PPB are needed e.g. to allow new system code to be

down loaded . If no c hange s are ne eded th en th e boot

code can set the PPB Lock to disable any further

changes to the PBBs during system operation.

The WP# protects the top two and bottom two sectors

when at VIL. These sectors generally hold system boot

code. The WP# pin can prevent any changes to the

boot code tha t could override the choices ma de while

setting up sector protection during system initializa-

tion.

It is possible to have sectors tha t have be en persis-

tently locked, and sectors that are left in the dynamic

state. The sectors in the dynamic state are all unpro-

tected. If there is a need to protect some of them, a

simple DYB Write co mmand sequ ence is all tha t is

necessary. The DYB write command for the dynamic

sectors switch the DYBs to signify protected and un-

protected, respectively. If there is a need to change

the status of the persistently locked sectors, a few

more steps are required. First, the PPB Lock bit must

be disabled by either putting the device through a

power-cycle, or hardware reset. The PPBs can then

be changed to reflect the desired settings. Setting the

July 29, 2002 Am29PDL128G 25

PRELIMINARY

PPB lock bit once again will lock the PPBs, and the

device operates normally again.

Note: to achiev e the best pr otec tio n, it’s recommended

to execute th e PPB lock bit set command ear ly in the

boot code, and pro tect the boot code by holdin g WP#

= VIL.

Table 9. Sector P rotection Schem es

Table 9 contains all possible combinations of the DYB-

DYB, PPB, and PPB lock relating to the status of the

sector.

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clear s the PPB

lock. If the PPB is cleare d, the sector can b e dynam i-

cally locked or unlocked. The DYB then controls

whether or not the sector is protected or unprotected.

If the user attemp ts to p rogram or erase a pro tected

sector, the device ignores the command and returns to

read mode. A program c ommand to a protected sector

enab les status polling for ap proxima tely 1 µs be fore

the device re turns to rea d mode without having mod i-

fied the contents of the protected sector. An erase

command to a protected s ector enables status pollin g

for approximately 50 µs after which the device returns

to read mode without having erased the protected sec-

tor.

The progra mming of the DYB , PPB, and PPB lock for

a given sector can be verified by writing a

DYB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode

Locking Bit

Like the password mode locking bit, a Persistent Sec-

tor Protectio n mode locking bit ex ists to guar antee that

the device rema in in software sector protec tion. Once

set, the Persistent Sector Protection locking bit pre-

vents programming of the password protection mode

locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Password Protection Mode

The Password Sector Protection Mode method allows

an even higher level of security than the Persistent

Sector Protection Mode. There are two main differ-

ences betw een the Persistent Sector Pro tection an d

the Password Sector Protection Mode:

■When the device is first powered on, or comes out

of a reset cycle, the PPB Lock bit set to the locked

state, rather than cleared to the unlocked state.

■The only means to clear the PPB Lock bit is by writ-

ing a unique 64-bit Password to the device.

The P asswor d Secto r Protectio n method is otherw ise

identical to the Persistent Sect or Protection method.

A 64-bit password is the only additional tool utilized in

this method.

The passw ord is stored in the first eight by tes of the

SecSi Sector. Once the Password Mode Locking Bit is

set, the passw ord is permanently set with no means to

read , program, or era se it. The password is used to

clear the PPB Lock bit. The Password Unlock com-

mand must be writte n to the flash, alo ng with a pass-

word. The flash device internally compares the given

passwo rd with the pre-prog rammed password . If they

match, the PPB Lock bit is cleared, and the PPBs can

be altered. If they do not match, the flash device does

nothing. There is a built-in 2 µs delay for each “pass-

word check.” This delay is intended to thwart any ef-

forts to run a program that tries all possible

combinations in order to crack the password.

Because the password occupies t he first eig ht by tes of

the SecSi Sector, the password must be programm ed

before either the password protection mode is se-

lected or the SecSi Sector protection bit is pro-

grammed (to use both the SecSi Sector and Pas sword

Prot ecti on at the s ame time ). S ee Utilizing Password

and SecSi Sector Concurrently for more information.

Password and Password Mode Locking

Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. AMD recomm ends that the password be some-

how correlated to the unique Electronic Serial Number

(ESN) of the particular flash device. Each ESN is dif-

ferent for every flash device; therefore each password

should be different for every flash device. While pro-

gramming in the password region, the customer may

perform Password Verify operations .

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

DYB PPB PPB

Lock Sector State

000

Unprotected—PPB and DYB are

changeable

001

Unprotected—PPB not

changable, DYB is changable

010

Protected—P PB and DYB are

changeable

100

110

011

Protected—PPB not changeable,

DYB is changeable

101

111

26 Am29PDL128G July 29, 2002

PRELIMINARY

1. It permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

2. It also disables all further commands to the pass-

word region. All program, and read operations are

ignored.

Both of these objectives are important, and if not care-

fully considered, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no means to verify what the

password is afterwards. If the password is lost after

setting the Password Mode Locking Bit, there will be

no way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is n ot erasable. On ce Password M ode Locki ng Bit

is programmed, the Persistent Sect or Protection Lock-

ing Bit is disabled from programming, guaranteeing

that no changes to the protect i on scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Verify Command”). The password function works in

conjunction with the Password Mode Locking Bit,

which when set, prevents the Password Verify com-

mand from read ing the c ontents of th e password on

the pins of the device.

Write Protect (WP#)

The Write Prot ect f eature provides a hardware method

of pro tecting sec tors 0, 1, 26 8, and 269 without us ing

VID. This funct ion is provided by the WP# pin and over-

rides the previously discussed Sector Protection/Un-

protection method.

If the system asserts VIL on the WP# pin, the dev ice

disab les progr am and erase func tions in s ectors 0 , 1,

268, and 269 ind ependent of whet her it was previous ly

protected or unprotected using High Voltage Sector

Protection.

If the system asserts VIH on the WP# pin, the device

reverts to whether sectors 0, 1, 268, and 269 were last

set to be protected or unprotected. That is, sector pro-

tection or unprotection for these sectors depends on

whether they were p reviously prot ected or unpro tected

using High Voltage Sector Protection.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password M ode Lock-

ing Bit a fter power-up reset. If the Passwo rd Mode

Lock Bi t is also set after a hardwa re reset (RESE T#

asserted) or a power-u p reset. The ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue th e Pas sword Unlock comman d. Suc-

cessful execution of the Passwor d Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1” when the

Password Mode Lock Bit is not set.

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit is set by issuing the PPB Lock Bit Set com-

mand. Once set the only means for clearing the PPB

Lock Bit is by issuing a hardware or power-up re set.

The Password Unlock command is ignored in Persis-

tent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be imple-

mented using programming e quipment. The proce-

dure requires high voltage (VID) to be placed on the

RESET # pin. Refer to Figure 1 for detai ls on this pr o-

cedure. Note that for sector unprotect, all unprotected

sectors must first be pro tected prio r to the first sector

write cycle.

July 29, 2002 Am29PDL128G 27

PRELIMINARY

Figure 1. In-System Sector Protection/

Sector Unprotection Algor ithm s

Note:These algorithms are valid only in Persistent Sector Protection mode. They are not valid in Password Protection Mode.

Sector Protect:

Write 60h to sector

address with

A6-A0 =

0111010

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6-A0 =

0111010

Read from

sector address

with A6-A0 =

0111010

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6-A0 =

1111010

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6-A0 =

1111010

Read from

sector address

with A6-A0 =

1111010

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

28 Am29PDL128G July 29, 2002

PRELIMINARY

Temporary Sector Unprotect

This feature allow s temporary unprotection of previ-

ously protected sectors t o change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to VID. During this mo de, formerly protec ted

sectors can be programmed or erased by selecting the

sector ad dresses. Once VID is removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 2 shows the algorithm, and

Figure 23 shows the timing diagrams, for this feature.

Figure 2. Temporary Sector Unprotect Operation

SecSi™ (Secured Silicon) Sector

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 128 words (64 double

words) in length, and uses a SecSi Sector In dicator Bit

(DQ7) to indic ate whether or not the SecSi Sector is

lock ed wh en sh ipped from th e fac tory. T his b it is per-

manently set at the factory and cannot be changed,

which pre vents cloning of a factory locked par t. This

ensures the security of the ESN once the product is

shipped to the field.

AMD offers the device with the SecSi Sector eithe r

factory locked or customer lockable. The fac-

tory-locke d version is alw ays protected w hen shippe d

from the factory, and has the SecS i Sector Indicato r

Bit permanently set to a “1.” The customer-lockable

version is shipped with the SecSi S ector unprotected,

allowing customers to utilize the that sector in any

manner they choose. The customer-lockable version

has the SecSi Sector Indicato r Bit permanently set t o a

“0.” Thus, the SecSi Sector Indicator Bit prevents cus-

tomer-lockable devices from being used to replace de-

vices that are factory loc ked.

The system accesses the SecSi Sector through a

command sequence (see Enter SecSi Sector/Exit

SecSi Sector Com mand Se quence). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses nor mally occupied by the boot sec tors. This

mode of op eration continues u ntil the system iss ues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device revert s t o send-

ing commands to the normal address space.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number

and a secure ESN. The SecSi Sector is located at ad-

dresses 000000h–00007Fh in word mode (or

000000h–0 0003Fh in double wor d mode). The device

is available preprogrammed with one of the following:

■A random, secure ESN only

■Customer code through the ExpressFlash service

■Both a random, secure ESN and customer code

through the ExpressFlash service.

Customers may opt t o have their code pro grammed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ES N. The device s are then shippe d from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service .

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an addition al Flash m emory sp ace.

The SecSi Se ctor ca n be read any number o f times,

but can b e programme d and locked o nly once. Note

that the accelerated programm ing (ACC) and unlock

bypass functions are not available when programming

the SecSi Sector.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Se ctor

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected (If WP# = VIL, sectors

0, 1, 268, and 269 will remain protected).

2. All previously protected sectors are protected once

again.

July 29, 2002 Am29PDL128G 29

PRELIMINARY

The SecSi Sec tor area can be prote cted using one of

the following procedures:

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 1, ex-

cept that R ESET# may be at either VIH or VID. This

allows in-system protect ion of the SecSi Sector Re-

gion without raising any device pi n to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

■Write the three-cycle Enter SecSi Sector Secure

Region command sequence, and then use the alter-

nate method of sector protection described in the

Sector Protection section.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

SecSi Sector Protection Bit

The SecSi Sector Pr otection Bit prevents program-

ming of the SecSi Sector memory area. Once set, the

SecSi S ector memor y area conte nts are non-modi fi-

able.

Utilizing Password and SecSi Sector Concurrently

The password must be stored in the first eight byt es of

the SecSi Sector. Once the device is permanently

locked into the Password Protection Mode, the erase,

program, and read op eration no longer work on those

eight bytes of password in the SecSi Sector. Once the

SecSi Sector protection bit is progr ammed, no loc ation

in the SecSi Sector may be programmed. To use both

Password Protection and the SecSi Sector concur-

rently, the user must always program the password

into the first eight bytes of the SecSi Sector before ei-

ther the Passwor d Protec tion Mo de is sel ected or th e

SecSi Sector protection bit is programmed.

Method 1

1. Enter the SecSi Sector by issuing the SecSi Sector

Entry comm a nd.

2. Program the 64-bit password by issuing the Pass-

word Program and Password Verify commands

3. Lock the password by issuing the Password Protec-

tion Mode Locking Bit Program command.

4. Program the SecSi Sector, excluding bytes 0–7.

5. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

6. Exit the SecSi Sector by issuing the SecSi Sector

Exit or Reset command

Note: Step 4 may be performed prior to step 2.

Method 2

1. Enter the SecSi Sector by issuing the SecSi Sector

Entry comm a nd.

2. Program the entire SecSi Sector, including the first

eight bytes contain the 64-bit password.

3. Lock the password by issuing the Password Protec-

tion Mode Locking Bit Program command.

4. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

5. Exit the SecSi Sector by issuing the SecSi Sector

Exit or Reset command

Note: Step 4 may be performed prior to step 3.

Hardware Data Protection

The command sequence requirement of unlock cycles

for program ming or erasing provides data prote ction

against inadvertent writes. In addition, the following

hardware data protection measures prevent ac cidental

erasure or programming, which mig ht otherwi se be

caused by spurious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhib it

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

wri tes are igno red until VCC is greater than VLKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when VCC is

greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical z ero while OE# is a

logical one.

Po we r - Up Wri t e In hibit

If WE# = CE# = VIL and OE# = V IH during power up,

the device does not accept commands on the rising

edge of W E#. The intern al state machine is automati-

cally reset to the read mode on power-up.

30 Am29PDL128G July 29, 2002

PRELIMINARY

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backw ard-compatible for the specified flash device

famil ies. Flash vendor s can sta ndardi ze their existin g

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 10–13. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CF I query m ode, an d the syst em can read

CFI data at the addresses given in Tables 10–13. The

system must write the reset command to return the de-

vice to reading array data.

For further information, pleas e refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/prod-

ucts/nvd/overview/cfi.html. Alternatively, contact an

AMD representative for copies of these documents.

Table 10. CFI Query Identification String

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h Primary OEM Command Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended Table

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 32h

34h 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

July 29, 2002 Am29PDL128G 31

PRELIMINARY

Table 11. System Interface String

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

1Bh 36h 0027h VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase )

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin presen t)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 0 00 0h Max . timeo ut for full chi p erase 2 N times typical (00h = not supported)

32 Am29PDL128G July 29, 2002

PRELIMINARY

Table 12. Device Geometry Definition

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

27h 4Eh 0018h Device Size = 2N byte

28h

29h 50h

52h 0005h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh 54h

56h 0000h

0000h Max. number of byte in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0003h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

00FDh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

July 29, 2002 Am29PDL128G 33

PRELIMINARY

Table 13. Primary Vendor-Specific Extended Query

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h Query-unique ASCII string “PRI”

43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon)

44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table)

45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2)

46h 8Ch 0002h Era se Sus pe nd

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 8Eh 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0007h Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800

mode

4Ah 94h 00E7h Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

4Bh 96h 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0002h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 9Ch 0005h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 9Eh 0001h Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = Uniform, 8 x 8 Kbit Top and Bottom, 02h =

Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom

50h A0h 0000h Program Suspend

0 = Not supported, 1 = Supported

57h AEh 0004h Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

58h B0h *0027h Bank 1 Region Information

X = Number of Sectors in Bank 1

59h B2h *0060h Bank 2 Region Information

X = Number of Sectors in Bank 2

5Ah B4h *0060h Bank 3 Region Information

X = Number of Sectors in Bank 3

5Bh B6h 0027h Bank 4 Region Information

X = Number of Sectors in Bank 4

34 Am29PDL128G July 29, 2002

PRELIMINARY

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Tables 14–17 define the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper se-

quence resets the device to reading array data.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The device is automatically set to reading array data

after device po wer-up. No c omma nds a re re quired to

retrieve data. Each bank is rea dy to read ar ray data

after completing an Embedded Prog ram or Embedded

Erase algorithm.

After the device accepts an E rase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase -suspended sec tor within the

same bank. The system can read array data using the

standard read timing, except that if it reads at an ad-

dress within erase-suspended sectors, the device out-

puts status data. After completing a programming

operation in the Erase Suspend mode, the system

may once again read array data with the same excep-

tion. See the Erase Suspend/Erase Resume Com-

mands section for more information.

The sy stem must issue the reset command to return a

bank to the read (or erase-suspend-re ad) mode if DQ5

goes high during an active program or erase opera-

tion, o r if the ba nk is in the autoselect m ode. S ee the

next section, Reset Command, for more information.

See also Requirem ents for Reading Array Da ta in the

Device Bus Operations section for more information.

The Read-Only Operat ions table provides t he read pa-

rameters, and Figure 11 shows the timing diagram.

Reset Command

Writing the re set command resets the banks to the

read or erase-suspen d-read mod e. Address bi ts are

don’t cares for this command.

The reset comm and may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the d evice ignores reset commands

until the operation is complete.

The reset command may be written between the

sequence cycles in a program com mand sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If th e

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, how-

ever, the device ignores reset commands until the

operation is complete.

The reset comm and may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operat ion,

writing the reset command returns the banks to the

read mode (or eras e-sus pend-re ad mod e if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

tose lect c ommand . The bank th en ent ers th e auto se-

lect mode. The system may read any number of

autoselect codes without reinitiating the command se-

quence.

Tables 14 and 16 s how the address and data require-

ments. To determine sector protection information, the

system must write to the appropriate bank address

(BA) and sector address (SA). Table 5 shows the ad-

dres s range and bank num ber asso ciated with each

sector.

The system must write the reset command to return to

the read m ode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing a random, eight word/four double word

elec tronic seri al number (ESN). T he system can ac-

cess the SecSi S ector region by issuin g the th ree-cy-

cle Enter SecSi Sector command sequence. The

device continues to access the SecSi Sector region

July 29, 2002 Am29PDL128G 35

PRELIMINARY

until the system issues the four-cycle Exit SecSi Sec-

tor command sequence. The Exit SecSi Sector com-

mand sequence returns the device to normal

operation. The SecSi Sector is not accessible when

the device is executing an Embedded Program or em-

bedde d Erase algorithm. Tables 15 and 17 show the

address and data requirements for both command se-

quences. See also “SecSi™ (Secured Silicon) Sector

Flash Memory Region” for further information.

Double Word/Word Program Command

Sequence

The system may program the device by double word

or word, depending on the state of the WORD# pin.

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

comma nd. The program address and data ar e written

next, which in tur n initia te the Emb edded Pro gram al-

gorith m. The system is not required to pro vide fu rther

controls or timings. The device automatically provides

internally g enerated program pulses and verifies the

programmed cell margin. Tables 14 and 16 show the

addre ss and data req uirem ents for th e pr ogram c om-

mand sequence.

When the Emb edded Progra m algo rithm is comple te,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refe r to the Write Ope ration

Status section for information on these status bits.

Any com mands wr itten to the dev ice during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitia ted once th at bank has return ed to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or c ause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a

“0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram data to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is f ollowed by a third write cycle c on-

taining the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contain s the unlock bypass program com-

mand, A0h; the second cycle contains the program

addres s and data . Additional data is pro grammed i n

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

comman d sequence, resulting in faster total p rogram-

ming tim e. Tables 14 and 16 show the requirements

for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass R eset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

The device offers accelerated program operations

through the ACC pin. When t he syste m assert s VHH on

the ACC pin, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the h igher voltage on the

ACC pin to accelerate the operation. Note that the

ACC pin must not be at VHH any op eratio n other tha n

accelerated programming, or device damage may re-

sult. In addition, th e ACC p in must n ot be l eft floating

or unconnected; inconsistent behavior of the device

may result.

Figure 3 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 16 for timing diagrams.

36 Am29PDL128G July 29, 2002

PRELIMINARY

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cy cle operat ion. The c hip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then fol lowed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically pr eprograms and v erifi es the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operat ions. Tables 14 and

16 show the address and data requirements for the

chip erase command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched . The system can determine the st a-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/B Y#. R efer to the Write Operation Status sec-

tion for information on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

media tely termina tes the erase o peration. If tha t oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase a nd Program Opera tions ta-

bles in the AC Characteristics sectio n for parameters,

and Figure 18 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, f ollowed by a set-up command. Two ad-

ditional unlock cycles are written, and are the n fol-

lowed by the address of the sector to be erased, and

the sector erase command. Tables 14 and 16 show

the address and data requirements for the sector

erase command sequence.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matical ly programs and veri fies the entire memory fo r

an all zero d ata pattern prior to elec trical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is writte n, a sect or erase

time-out of 80 µs occurs. During the time-out period,

additio nal sector addresses and sector erase com-

mands may be written . Loading t he sector er ase buf fer

may be done in any sequence, and t he number of sec-

tors m ay be from on e sector to all sectors. The time

between these addi tional cycles must be less than 80

µs, otherwise erasure may begin. Any sector erase

address and command following the exceeded

time-out may or may not be accepted. It is recom-

mended that processor interrupts be disabled during

this time to ensure all command s are accepted. Th e

interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the

time-out period resets that bank to the read mode.

The system must rewrite the command sequence and

any additional addresses and commands.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer .). The t ime-out be gins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

bank returns to rea ding array data and address es are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine th e status of the erase oper ation by readin g

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Tables 14 and 16 for program command

sequence.

July 29, 2002 Am29PDL128G 37

PRELIMINARY

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.

Re fer to th e Write Operation Status section for infor-

mation on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately termina tes th e erase operation. If

that occurs, the sector erase command sequence

shou ld be rein itiated onc e that ban k has retur ned to

reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the E rase and Program Op erations ta-

bles in the AC Cha racteristics s ection for parameters ,

and Figure 18 sect ion for timing diagrams.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operat ion and then read

data from, or program data to, any sector not selected

for erasure. The bank ad dress i s required when writing

this com mand. Th is comma nd is v alid only during th e

sector erase operation, including the 80 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device im medi-

ately terminates the time-out period and suspends the

erase operation. Addresses are “don’t-cares” whe n

writing the Erase suspend command.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is activ ely erasing or is erase-suspen ded.

Re fer to th e Write Operation Status section for infor-

mation on these status bits.

After a n erase-su spende d program ope ration is co m-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

progr am op eration using th e DQ7 or DQ 6 statu s bits,

just as in the standard Double Word/Word Program

operation. Refer to the Write Operation Status section

for more information.

In the erase-suspend-read mode, the system can also

issue the autosele ct comma nd seque nce. The de vice

allows reading autoselect codes even at addresses

within eras ing sectors, sinc e the codes are no t stored

in the memory array. When the device exits the au-

toselect mode, the device reverts to the Erase Sus-

pend mode, and is ready for another valid operation.

Refer to the Autoselect Mode and Autoselect Com -

mand Sequence se ct ions f or details.

To resume the sector erase operation, the system

must write the Erase Resume command (address bits

are don’t care). The ba nk address of the era se-sus-

pended bank is required when writing this command.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the chip has resumed erasing.

Figure 4. Erase Operation

Password Program Command

The Password Program Command permits program-

ming the password that is used as part of the hard-

ware protection scheme. The actual password is

64-bits long. Depending upon the state of the WORD#

pin, multiple Password Program Commands are re-

quired. F or a x16 bit data bus , 4 Password P rogram

commands are required to program the password. For

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

Notes:

1. See Tables 14 and 16 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

38 Am29PDL128G July 29, 2002

PRELIMINARY

a x32 b it data bus, 2 P assword Prog ram comman ds

are required. The user must enter the unlock cycle,

password program c ommand (38h) and the program

address/d ata for each portion of the password when

programming. There is no special address ing order re-

quired for programming the password. Also, when the

password is undergoing programming, Simultaneous

Operation is disabled. Read operations to any memory

location will return the programming status. Once pro-

gramming is complete, the user must issue a

Read/Reset command to return the device to normal

operation. Once the Password is written and verified,

the Password Mode Locking Bit must be set in order to

prevent verification. The Password Program Com-

mand is only capable of programming “0”s. Program-

min g a “1” aft er a c ell is programmed as a “0” results in

a time-out by the Embedded Program Algorithm™

with the cell remainin g as a “0”. The password is all F’s

when shipped fro m the factory. All 64-bit password

combinations are valid as a password.

Password Pr ogramming i s permitted if the Sec Si sec-

tor is enabled.

Password Verify Command

The Pas sword Ve rify Comman d is used to verify th e

Password . The Passw ord is verifiable only when th e

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user attempts to verify the Pas sword, the device will

always drive all F’s onto the DQ data bus.

The Password Verify command is permitted if the

SecSi sector is enabled. Also, the device will not oper-

ate in Simultaneo us Operation wh en the Password

Verify command is executed. Only the password is re-

turned regardless of th e bank address. The lower tw o

address bits (A0:A-1) are valid during the Password

Verify. Writing the Read/Reset com mand returns the

device back to normal operation.

Password Protection Mode Locking Bit

Program Command

The Password Protection Mode Locking Bit Program

Comm and prog rams the Pa ssword P rotection Mode

Locking Bit, which prevents further verifies or updates

to the Password. Once programmed, the Password

Protection Mode Locking Bit cannot be erased! If the

Passwor d Protection Mod e Locking Bit is verified as

program without margin, the Password Protection

Mode Locking Bit Program command can be executed

to impr ove the program margin. Onc e the Passwor d

Protec tion Mode Locking Bit is prog ramme d, the Per-

sistent Sector Protection Locking Bit program circuitry

is disabled, thereby forcing the device to remain in the

Password Protec tion mode. Exiting the Mod e Locking

Bit P rogram co mmand is acco mplish ed by w riting th e

Read/Reset command.

The Password Protection Mode Locking Bit Program

command is permitted if the SecSi sector is enabled.

Persistent Sector Protecti on Mode

Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit

Program Command programs the Persistent Sector

Protection Mode Locking Bit, which prevents the Pass-

word M ode Lockin g Bit from ever being progr ammed.

If the Persistent Sector Protection Mode Locking Bit is

verified as programmed without margin, the Persistent

Sector Protection Mode L ocking Bit Program Com-

mand should be reissued to improve program margin.

By disabling the prog ram circuitry of t he Password

Mode Locking Bit, the device is forc ed to remain in the

Persistent Sector Protection mode of operation, once

this bit is set. Exiting the Persistent Protection Mode

Locking Bit Program command is accomplished by

writing the Read/Reset command.

The Persistent Sector Protection Mode Locking Bit

Program command is permitted if the SecSi sector is

enabled.

SecSi Sector Protection Bit Program

Command

The Se cSi Sector Protection Bit P rogram Com mand

programs the SecSi Sector Protection Bit, which pre-

vents the SecSi se ctor mem ory from bei ng cleared. If

the SecSi Sector Protection Bit is verified as pro-

grammed without margin, the SecSi Sector Protection

Bit Program Command should be reissued to improve

program margin. Exiting the VCC-level SecSi Sector

Protection Bit Progra m Command is acc omplished by

writing the Read/Reset command.

The SecSi Sector Protection Bit Program command is

permitted if the SecSi sector is enabled.

PPB Lock Bit Set Command

The P PB Lock Bit Set command is us ed to set the

PPB Lock bit if it is cleared either at reset or if the

Password Unlock command was successfully exe-

cuted. There is no PPB Lock Bit Clear command.

Once the PPB Lock Bit is set, it cannot be cleared un-

less the dev ice is taken throug h a power-on clear or

the Password Unlock command is executed. Upon

setting the PP B Loc k Bit , th e PPBs are la tc hed i nto the

DYBs. If the Password Mode Locking Bit is set, the

PPB L ock Bit status is refl ected as set, even after a

power-on reset cycle. In the Persistent Sector Protec-

tion mode, exiting the PPB Lock Bit Set command is

accomplished by writing the Read/Reset command.

The PPB Lock Bit Set comma nd is permitted if the

SecSi sector is enabled.

July 29, 2002 Am29PDL128G 39

PRELIMINARY

DYB Write Command

The DYB Write command is used to set or clear a DYB

for a given sector. The high order address bits

(A21–A11) are issued at the same time as the code

01h or 00h on DQ7-DQ0. All other DQ data bus pins

are ignored during the data write cycle. The DYBs are

modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. The DYBs are cleared at

power-up or hardware reset.Exiting the DYB Write

command is accomplished by writing the Read/Reset

command.

The DYB Write command is permitted if the SecSi

sector is enabled.

Password Unlock Command

The Password U nlock command is used to clear the

PPB Lock Bit so that the PPBs can be unlocked for

modificati on, thereby allowing the PPBs to become ac-

cessible for modificati on. The exact password must be

entered in order for the unlocking function to occur.

This c ommand c annot be issued an y faster tha n 2 µs

at a time to prevent a hacker from running through the

all 64-bit combinations in an atte mpt to c orrectl y match

a password. If the command is issued before the 2 µs

execution win dow for each portion of the unlock, the

command will be ignored.

The Password Unlock function is accomplished by

writing Password Unlock command and data to the

device to perform the clearing of the PPB L ock Bit.

The password is 64 bits long, so the user must write

the Password Unlock comma nd 2 times for a x32 bit

data bus and 4 times for a x16 data bus.

Once the Password Unlock command is entered, the

RY/BY# pin goes LOW indicating that the device is

busy. Approximately 2 µs is required for each portion

of the un lock. Once the fir st portion of the pa sswor d

unlock completes (RY/BY# is not driven and DQ6

does not toggle when read), the Password Unlock

comman d is issued agai n, only this time w ith the next

part of the passwor d. If WORD# = 1, the second Pas s-

word Unlock command is the final command before

the PPB Lock Bit is cleared (assuming a valid pass-

word). If WO RD# = 0, this is the fourth Pa ssword Un-

lock command. In x16 mode, four Password Unlock

commands are required to successfully clear the PPB

Lock Bit. As with the first Password Unlock command,

the RY/BY# s ignal goes LOW and reading the devi ce

results in the DQ6 pin toggling on successive read op-

erations until complete. It is the responsibility of the

microprocessor to keep track of the number of Pass-

word Unlock commands (2 for x32 bus and 4 for x16

bus), the order, and when to read the PPB Lock bit to

confirm successful password unlock

The Password Unlock command is permitted if the

SecSi sector is enabled.

PPB Program Command

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually pro-

grammed (but is bulk erased with the other PPBs).

The specific sector address (A21–A11) are written at

the sa me time as the p rogram command 60h wi th A6

= 0. If the PPB Lock Bit is set and the corresponding

PPB is set for the sector, the PPB Program command

will not execute and the command will time-out without

programming the PPB.

After programm ing a PPB , two additional cycles are

needed to determine whether the PPB has been pro-

grammed with margin. If the PPB has been pro-

grammed without margin, the program command

should be reissued to improve the program margin.

The PPB P rogram comm and is permitted if the SecSi

sector is enabled. The PPB Program command does

not follow the Embedded Program algorithm.

All PPB Erase Command

The All PPB Erase command is used to erase all

PPBs in bulk. There is no means for individually eras-

ing a specific PPB. Unlike the PPB program, no spe-

cific sector address is required. However, when the

PPB erase comman d is written (60h) and A6 = 1, all

Sector PPBs are erased in parallel. I f t he PPB Lock Bit

is set the ALL PPB Erase comm and will not execute

and the command will time-out without erasing the

PPBs. A fter erasing the P PBs, two add itional cycles

are needed to determine wh ether the PP B has been

erased with margin. If the PPBs has been erased with-

out margin, the erase command should be reissued to

improve the program margin.

It is the responsibility of the user to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the use r attempts to erase a cleared PPB , over-era-

sure ma y occur making i t difficult to pr ogram the PPB

at a later time. Also note that the total number of PPB

program/erase c ycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

The All PPB Erase command is permitted if the SecSi

sector is enabled.

DYB Write Command

The DYB Write command is us ed for setting the DYB,

which is a volatile bit that is cleared at hardware reset.

There is one DYB per sector. If the PPB is set, the

sector is protected regardless of the value of the DYB.

If the PPB is cleared, setting the DYB to a 1 protects

the sector f rom prog rams or erases . Since t his is a vol-

atile bit, removing power or resetting the device will

clear the DYBs. The bank address is latched when the

command is written.

40 Am29PDL128G July 29, 2002

PRELIMINARY

The DYB Write command is permitted if the SecSi

sector is enabled.

PPB Lock Bit Set Command

The PPB Lock Bit set command is used for setting the

PPB lock bit. Dur ing Passwor d Protection mode, on ly

the Password Unlock command can reset the PPB

Lock Bit to 0. Otherwise, a power-up or hardware reset

resets the PPB Lock Bit to 0.

PPB Lock Bit Status Command

The program ming of the PPB Lock Bit ca n be verified

by writing a PPB Lock Bit status verify command to the

device.

Sector Protection Status Command

The programming of either t he PPB o r DYB for a given

sector or sector group can be v erified by writing a Sec-

tor Protection Stat us command to the device.

Note that there i s no single command to i ndependent ly

verify the program ming of a DYB or PPB for a given

sector group.

July 29, 2002 Am29PDL128G 41

PRELIMINARY

Command Definitions Tables

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or

erase operation. Determined by A21:A19, see Tables 4 and 5 for

more detail.

PA = Program Address (A21:A0). Addresses latch on falling edge of

WE# or CE# pulse, whichever happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches

on rising edge of WE# or CE# pulse, whichever happens first.

RA = Read Address (A21:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (A21:A12) for verifying (in autoselect mode) or

erasing.

WD = Write Data. See “Configuration Register” definition for specific

write data. Data latched on rising edge of WE#.

X = Do n’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares .

5. No unlock or command cycles required when bank is reading

array data.

6. Reset command is required to return to reading array (or to

erase-suspend-read mode if previously in Erase Suspend) when

bank is in autoselect mode, or if DQ5 goes high (while bank is

providing status information).

7. Cycle 4 of autoselect command sequence is a read cycle. See

Autoselect Command Sequence section for more information.

8. The data is 80h for factory locked and 00h for not factory locked.

9. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

10. Device ID must be read across cycles 4, 5, and 6.

11. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector

erase operation, and requires bank address.

12. Program/Erase Resume command valid only during Erase

Suspend mode, and requires bank address.

13. Command valid when device is ready to read array data or when

device is in autoselect mode.

14. ACC must be at VID during entire operation of command.

15. Command is ignored during any Embedded Program, Embedded

Erase, or Suspend operation.

16. Unlock Bypass Entry command is required prior to any Unlock

Bypass operation. Unlock Bypass Reset command is required to

return to reading array.

Table 14. Memory Array Command Definitions (x32 Mode)

Command (Notes)

Cycles

Bus Cycles (Notes 1–4)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (5) 1 RA RD

Reset (6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01

Device ID (10) 6 555 AA 2AA 55 555 90 (BA)X01 7E (BA)X0E 0D (BA)X0F 00

SecSi Sector

Factory Protect 4 555 AA 2AA 55 555 90 X03 (see

Note 8)

Sector Group

Protect Verify (9) 4 555 AA 2AA 55 555 90 SA02 XX00/

XX01

Program 4 555 AA 2AA 55 555 90 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Program/Erase Suspend (11) 1 BA B0

Program/Erase Resume (12) 1 BA 30

CFI Query (13) 1 55 98

Accelerated Program (15) 2 XX A0 PA PD

Configuration Register Verify 4 555 AA 2AA 55 (BA)5

55 C6 (BA)XX RD

Configuration Register Write (16) 4 555 AA 2AA 55 555 D0 XX WD

Unlock Bypass Entry (17) 3 555 AA 2AA 55 555 20

Unlock Bypass Program (17) 2 XX A0 PA PD

Unlock Bypass Erase (17) 2 XX 80 XX 10

Unlock Bypass CFI (13, 17) 1 XX 98

Unlock Bypass Reset (17) 2 XX 90 XX 00

42 Am29PDL128G July 29, 2002

PRELIMINARY

Legend:

DYB = Dynamic Protection Bit

SSA = SecSi Sector Address (A6:A0) is (0011010).

PD[1:0] = Program Data. Password written in 2 portions.

PPB = Persistent Protection Bit

PWA = Password Address. A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A5:A0) is (001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock bit status.

SA = Sector Address where security command applies. Address bits

A21:A11 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)

WP = PPB Address (A6:A0) is (0111010) (Note 17)

EP = PPB Erase Ad dress (A6:A0 ) is (1111010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares .

5. Reset command returns device to reading array.

6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate

bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle

6, entire command sequence must be issued and verified again.

7. Data is latched on rising edge of WE#.

8. Entire command sequence must be executed for each portion of

password.

9. Command sequence returns FFh if PPMLB is set.

10. Password is written over four consecutive cycles at addresses

0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command

sequence must be issued and verified again. Before issuing

erase command, all PPBs should be programmed to prevent

PPBs overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

16. For all other parts that use the Persistant Protection Bit (axcluding

PDL640G), the WP address is 000010.

Table 15. Sector Protection Command Definitions (x32 Mode)

Command (Notes)

Cycles

Bus Cycles (Notes 1-4)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXX F0

SecSi Sector Entry 3 555 AA 2AA 55 (BA)555 88

SecSi Sector Exit 4 555 AA 2AA 55 (BA)555 90 XX 00

SecSi Protection Bit Program (5, 6) 6 555 AA 2AA 55 (BA)555 60 SSA 68 SSA 48 XX RD(0)

Password Program (5, 7, 8) 4 555 AA 2AA 55 555 38 XX[0-1] PD[0-1]

Password Verify (8, 9) 4 555 AA 2AA 55 555 C8 PWA[0-1] PWD[0-1]

Password Unlock (7, 10, 11) 4 555 AA 2AA 55 555 28 PWA[0-1] PWD[ 0-1]

PPB Program (6, 12) 6 555 AA 2AA 55 555 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0)

All PPB Erase (13, 14) 6 555 AA 2AA 55 555 60 (SA)EP 60 (SA)EP 40 (SA)WP RD(0)

PPB Lock Bit Set 3 555 AA 2AA 55 555 78

PPB Lock Bit Status (15) 4 555 AA 2AA 55 555 58 SA RD(1)

DYB Write (7) 4 555 AA 2AA 55 555 48 SA X1

DYB Erase (7) 4 555 AA 2AA 55 555 48 SA X0

DYB or PPB Status 4 555 AA 2AA 55 555 58 SA RD(0)

PPMLB Program (6,12) 6 555 AA 2AA 55 555 60 PL 68 PL 48 XX RD(0)

PPMLB Status (5) 4 555 AA 2AA 55 555 60 PL RD(0)

SPMLB Program (6,12) 6 555 AA 2AA 55 555 60 SL 68 SL 48 XX RD(0)

SPMLB Status (5) 4 555 AA 2AA 55 555 60 SL RD(0)

July 29, 2002 Am29PDL128G 43

PRELIMINARY

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or

erase. Determined by A21:A19, see Tables 4 and 5 for more detail.

PA = Program Address (A21:A-1). Addresses latch on falling edge of

WE# or CE# pulse, whichever happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches

on rising edge of WE# or CE# pulse, whichever happens first.

RA = Read Address (A21:A-1).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (A21:A12) for verifying (in autoselect mode) or

erasing.

WD = Write Data. See “Configuration Register” definition for specific

write data. Data latched on rising edge of WE#.

X = Do n’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits are

555 or AAAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares .

5. No unlock or command cycles required when bank is reading

array data.

6. Reset command is required to return to reading array (or to

erase-suspend-read mode if previously in Erase Suspend) when

a bank is in autoselect mode, or if DQ5 goes high (while bank is

providing status information).

7. Cycle 4 of autoselect command sequence is a read cycle. See

Autoselect Command Sequence section for more information.

8. The data is 80h for factory locked and 00h for not factory locked.

9. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

10. Device ID must be read across cycles 4, 5, and 6.

11. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command valid only during a sector

erase operation, and requires bank address.

12. Program/Erase Resume command valid only during Erase

Suspend mode, and requires bank address.

13. Command is valid when device is ready to read array data or

when device is in autoselect mode.

14. ACC must be at VID during entire operation of this command.

15. Command ignored during any Embedded Program, Embedded

Erase, or Suspend operation.

16. Unlock Bypass Entry command required prior to any Unlock

Bypass operation. Unlock Bypass Reset command is required to

return to reading array.

Table 16. Memory Array Command Definitions (x16 Mode)

Command (Notes)

Cycles

Bus Cycles (Notes 1–4)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (5) 1 RA RD

Reset (6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01

Device ID (10) 6 555 AA 2AA 55 555 90 (BA)X01 7E (BA)X0E 0D (BA)X0F 00

SecS i S e ctor Fa ctory

Protect 4 555 AA 2AA 55 555 90 X03 (see

Note

Sector Group Protect

Verify (9) 4 555 AA 2AA 55 555 90 SA02 XX00/

XX01

Program 4 555 AA 2AA 55 555 90 PA PD

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

Program/Erase Suspend (11) 1 BA B0

Program/Erase Resume (12) 1 BA 30

CFI Query (13) 1 55 98

Accelerated Program (15) 2 XX A0 PA PD

Configuration Register Verify 4 AAA AA 555 55 (BA)AAA C6 (BA)XX RD

Configuration Register Write (16) 4 AAA AA 555 55 AAA D0 XX WD

Unlock Bypass Entry (17) 3 AAA AA 55 5 55 AAA 20

Unlock Bypass Program (17) 2 XX A0 PA PD

Unlock Bypass Erase (17) 2 XX 80 XX 10

Unlock Bypass CFI (13, 17) 1 XX 98

Unlock Bypass Reset (17) 2 XX 90 XX 00

44 Am29PDL128G July 29, 2002

PRELIMINARY

Legend:

DYB = Dynamic Protection Bit

SSA = SecSi Sector Address (A6:A0) is (0011010).

PD[3:0] = Program Data. Password written as four 16-bit sections.

PPB = Persistent Protection Bit

PWA = Password Address. A0:A-1 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A5:A0) is (001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock bit status.

SA = Sector Address where security command applies. Address bits

A21:A11 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)

WP = PPB Address (A6:A0) is (0111010) (Note 16)

EP = PPB Erase Ad dress (A6:A0 ) is (1111010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits are

555 or AAAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares .

5. Reset command returns device to reading array.

6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate

the bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in

cycle 6, the program command must be issued and verified again.

7. Data is latched on rising edge of WE#.

8. Entire command sequence must be executed for each portion of

password.

9. Command sequence returns FFh if PPMLB is set.

10. Password is written over four consecutive cycles, at addresses

0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed in order to prevent

PPB overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

16. For all other parts that use the Persistant Protection Bit (excluding

PDL640G), the WP address is 000010.

Table 17. Sector Protection Command Definitions (x16 Mode)

Command (Notes)

Cycles

Bus Cycles (Notes 1-4)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXX F0

SecSi Sector Entry 3 AAA AA 555 55 (BA)AAA 88

SecSi Sector Exit 4 AAA AA 555 55 (BA)AAA 90 XX 00

SecSi Protection Bit Program (5, 6) 6 AAA AA 555 55 (BA)AAA 60 SSA 68 SSA 48 XX RD(0)

Password Program (5, 7, 8) 4 AAA AA 555 55 AAA 38 XX[0-3] PD [0-3]

Password Verify (8, 9) 4 AAA AA 555 55 AAA C8 PWA[0-3] PWD[0-3]

Password Unlock (7, 10, 11) 4 AAA AA 555 55 AAA 28 PWA[0-3] PWD[0-3]

PPB Program (6, 12) 6 AAA AA 555 55 AAA 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0)

All PPB Erase (13, 14) 6 AAA AA 555 55 AAA 60 (SA)EP 60 (SA)EP 40 (SA)WP RD(0)

PPB Lock Bit Set 3 AAA AA 555 55 AAA 78

PPB Lock Bit Status (15) 4 AAA AA 555 55 AAA 58 SA RD(1)

DYB Write (7) 4 AAA AA 555 55 AAA 48 SA X1

DYB Erase (7) 4 AAA AA 555 55 AAA 48 SA X0

DYB or PPB Status 4 AAA AA 555 55 AAA 58 SA RD(0)

PPMLB Program (5, 6, 12) 6 AAA AA 555 55 AAA 60 PL 68 PL 48 XX RD(0)

PPMLB Status (5) 4 AAA AA 555 55 AAA 60 PL RD(0)

SPMLB Program (5, 6, 12) 6 AAA AA 555 55 AAA 60 SL 68 SL 48 XX RD(0)

SPMLB Status (5) 4 AAA AA 555 55 AAA 60 SL RD(0)

July 29, 2002 Am29PDL128G 45

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the st atus of

a program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 18 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method

for determining whether a program or erase operation is

comple te or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Pr ogram or Eras e operation is in progress or

has been compl eted.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequen ce.

During the Embedded Program algorithm, the de vice out-

puts on DQ7 t he comp lemen t of t he dat um pr ogr ammed to

DQ7. This DQ7 status also applies to programming during

Erase S uspend. When the Embedded Progr am algorithm i s

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. I f a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for a pp rox im ate ly 1 µ s, th en th at b a nk retu r ns to th e

read mode.

Durin g the Embedded Era se algorithm, Da ta# Pollin g

produces a “0” on DQ7. When the E mbedded Erase

algorithm is comp lete, or if the ba nk enters th e Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors s elected for eras ure to read valid s tatus infor-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unpr otected secto rs, and ign ores the s e-

lected sector s that are protected. Howev er, if the sys -

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

When the system dete cts DQ7 ha s changed from the

complement to true data, it can read valid data at

DQ31–DQ0 (or DQ15–DQ0 for word mode) on the fol-

lowing read cycles. Just p rior to the com pletion of an

Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ31–DQ16

(DQ15–DQ0 for word mode) while Output Enable

(OE#) is asserted low. That is, the device may change

from providing stat us inf ormation to v alid data on DQ7.

Depending on when the system samples the DQ7 out-

put, it may read t he stat us or v alid data. Even if t he de-

vice has completed the program or erase operation

and DQ7 has valid data, the data outputs on

DQ31–DQ0 may be still invalid. Valid data on

DQ31–DQ0 (or DQ15–DQ0 for word mode) will ap-

pear on successive read cycles.

Table 18 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 20

in the AC Characteristics section shows the Data#

Polling timing diagram.

Figure 5. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

46 Am29PDL128G July 29, 2002

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

which indica tes whether an Embedded Algor ithm is in

progress or complete. The RY/BY# status is v alid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/ BY# is an open-drain output, sev-

eral RY/BY# pins can be tied togeth er in parallel with a

pull-up resistor to VCC.

If the output is low ( Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

Table 18 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Prog ram or E rase alg orithm is in prog ress or c om-

plete, or whether the device has entered the E rase

Susp end mode . Toggle Bit I may be read at any a d-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operatio n), and during the sector

erase time-out.

During an Embedded Program or Erase algorithm op-

eration, success ive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ 6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selec ted sector s are prot ected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

The syst em can us e DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that i s, the Embedded Eras e algorithm is in prog ress),

DQ6 togg les. Whe n the dev ice enters the Er ase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use D Q2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

If a program address falls within a protected sector,

DQ6 toggles for appr oximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 18 shows the ou tputs for To ggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 21 in

the “AC Characteristics” section shows the toggle bit

timing diagrams . Figure 2 2 shows the differences b e-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

Fig ure 6. Toggle Bit Alg orithm

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Toggle Bit

= Toggle?

Read Byte Twice

(DQ0–DQ7)

Address = VA

Read Byte

(DQ0–DQ7)

Address =VA

Read Byte

(DQ0–DQ7)

Address =VA

Note: The system should recheck the toggle bit even if DQ5

= “1” becaus e the tog gle bit may stop tog glin g as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more informa tio n.

July 29, 2002 Am29PDL128G 47

PRELIMINARY

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that i s, the Embedded Eras e algorithm is in prog ress),

or wheth er that sector is erase -suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the s ector is activ ely erasing or i s erase-sus-

pended. D Q6, by comparis on, indicates whether th e

device is actively erasing, or is in Er ase Suspend, but

cannot di stinguish wh ich sect ors are select ed for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 18 to compare out-

puts for DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorith m. See also the DQ6: Toggle Bit I subsection.

Figure 21 shows the toggle b it timing diagram. F igure

22 shows the differences between DQ2 and DQ6 in

graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it m ust read DQ31–DQ 0 (or DQ 15–DQ 0 for wor d

mode) at least twice in a row to determine whether a

toggle bit is toggling. Typical ly, the system would note

and store the value of the toggle bit after the first read.

After the second read, the system would compare the

new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the pro-

gram or erase operation. The system can read array

data on DQ31–DQ0 (or DQ15–DQ0 for word mode)

on the following read cycle.

However, if af ter the initial two read cycles, the system

determi nes that th e toggle bi t is still togg ling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then de termine again whether the tog gle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. I f it is still tog gling, the de-

vice did not completed the operation successfully, and

the system must write the reset comm and to return to

reading array data.

The rem ainin g scena rio is that t he syste m initia lly de-

termines that the toggle bit is toggling and DQ5 has

not gone hi gh. The system may continue t o monitor

the toggle bit and DQ5 through successive read cy-

cles, determin ing the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or e rase time has

exceeded a s pecified int ernal pulse cou nt limit. Under t hese

conditions DQ5 produces a “1,” indicating tha t the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device ha lts the operation , and when the timing lim it

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies afte r each a dditional se ctor erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the tim e between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. I f DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device w ill acce pt additio nal sector erase c ommands.

To ens ure the com mand has been acce pted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If D Q3 is high on the second statu s check, the

last command might not have been accepted.

Ta ble 18 shows the status of DQ3 relative to the other

status bits.

48 Am29PDL128G July 29, 2002

PRELIMINARY

Table 18. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embe dd ed Pro gra m Algo rith m DQ7# Toggle 0 N/A No toggle 0

Embedd ed Era se Alg orith m 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

July 29, 2002 Am29PDL128G 49

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to + 125°C

Voltage with Respect to Ground

VCC ( N o te 1 ) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

ACC ( N o te 2 ) . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot VSS to –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is VCC +0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to VCC +2.0 V for periods up to 20 ns. See

Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and ACC is –0.5 V. During voltage transitions, A9, OE#,

ACC, and RESET# may overshoot VSS to –2.0 V for

periods of up to 20 ns. See Fig ure 7 . M axi mu m D C inp ut

voltage on pin A9, OE#, and R ESET# is +12.5 V which

may overshoot to +14.0 V for periods up to 20 ns.

Maximum D C in put volt age on A C C is +9 .5 V whi ch m ay

overshoot to +12.0 V for periods up to 20 ns.

3. No more tha n one outpu t may be shor ted to ground at a

time. Duration of the short c ircuit should n ot be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; function al operation of the device at

these or any other co nditions above those i ndica ted in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditio ns for exte nd ed per iod s may affe ct dev ice relia bili ty.

Figure 7. Maximum Negative

Overshoot Waveform

Figure 8. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125 °C

Supply Voltages

VCC for full regulated range . . . . . . . . . .3.0 V to 3.6 V

VCC for full voltage range . . . . . . . . . . . .2.7 V to 3.6 V

VIO (see Not e ) . . . . . . . . . . . . . . . . . . . .2.7 V to 3. 6 V

Note: For all AC and DC specifications, VIO = VCC; contact

AMD for other VIO options.

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

50 Am29PDL128G July 29, 2002

PRELIMINARY

DC CHARACTERISTICS

CMOS Compatible

Notes:

1. The ICC current listed is typically less than 4mA/MHz, with OE# at VIH.

2. Maximum ICC specifications are t ested wi th V CC = VCCmax.

3. ICC active while Embedded Er ase or Embedded Prog ram is in pr ogress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sl eep mode current is

200 nA.

5. Not 100% tested.

Parameter

Symbo l Paramet er Des cri ptio n Test Cond itio ns Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA

ILIT A9, OE#, RES ET #

Input Load Current VCC = VCC max; VID= 12.5 V 35 µA

ILO Output Lea ka ge Cur r en t VOUT = VSS to VCC, OE# = VIH

VCC = VCC max ±1.0 µA

ICC1

VCC Active Inter-page Read Current,

Word/Double Word Modes

(Not es 1, 2) CE# = VIL, OE# = VIH

1 MHz 4.5 9

mA5 MHz 20 40

10 MHz 38 45

VCC Active Intra-page Read Current,

Word/Double Word Modes (Note 2) CE# = VIL, OE# = VIH 1 MHz 9 18 mA

5 MHz 37 45

ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 17 35 mA

ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 1.5 5 µA

ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 1.5 5 µA

ICC5 Automatic Sle ep Mod e (Not es 2, 4) VIH = VCC ± 0.3 V;

VIL = VSS ± 0.3 V 1.5 5 µA

ICC6 VCC Active Read-While-Program

Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 30 45 mA

Dbl. Word 30 45

ICC7 VCC Active Read-While-Erase

Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 21 45 mA

Dbl. Word 21 45

ICC8 VCC Active Program-While-Erase-

Suspen de d Curre nt (No tes 2, 5) CE# = VIL, OE# = VIH 17 35 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

VHH Voltage for ACC Program

Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V

VID Voltage for Autoselect and

Temporary Se ctor Unpro tec t VCC = 3.0 V ± 10% 11.5 12.5 V

VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V

VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VIO V

VOH2 IOH = –100 µA, VCC = VCC min V

IO–0.4

VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

July 29, 2002 Am29PDL128G 51

PRELIMINARY

TEST CONDITIONS

Table 19. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

Figure 9. Test Setup

Test Condition 70R, 70, 80, 90 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap acit anc e) 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference leve ls 1.5 V

Output timing measurement

reference leve ls 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

Figure 10. Input W aveforms and Measurement Levels

52 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 19 f or te st spec ific ations

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to

the data bus driven to VCC/2 is taken as tDF.

Parameter

Description Test Setup

Speed Options

JEDEC Std. 70R, 70 80 90 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 70 80 90 ns

tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 70 8090ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 8090ns

tPACC Page Access Time Max 25 30 35 ns

tGLQV tOE Output Enable to Output Delay Max 25 30 35 ns

tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max 25 30 30 ns

tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 25 30 30 ns

tAXQX tOH Output Hold Time From Addresses, CE# or OE#,

Whichev er Occ urs First Min 5 5 5 ns

tOEH Output Enable Hold Time

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

Figure 11. Read Operation Timings

July 29, 2002 Am29PDL128G 53

PRELIMINARY

AC CHARACTERISTICS

Figure 12. Page Read Operation Timings

A21

CE#

OE#

A-1

Data Bus

Same Page

Aa Ab Ac Ad

Qa Qb Qc Qd

tACC tPACC tPACC tPACC

54 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Descri ptio n All Speed Optio ns UnitJEDEC Std

tReady RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 13. Reset Timings

July 29, 2002 Am29PDL128G 55

PRELIMINARY

AC CHARACTERISTICS

Word/Double Word Configuration (WORD#)

Parameter Speed Options

JEDEC Std Description 70R, 70 80 90 Unit

tELFL/tELFH CE# to WORD# Switching Low or High Max 5 ns

tFLQZ WORD# Switching Low to Output HIGH Z Max 30 30 30 ns

tFHQV WORD# Switching High to Output Active Min 70 80 90 ns

Data

Switching from

word mode to

double word mode

Switching from

double word mode

to word mode

tELFL

tELFH

tFLQZ

tFHQV

Address

Input

Address

Input

Output

OutputOutput

Output

Output Output

DQ30–DQ16

DQ31/A-1

DQ15–DQ0

WORD#

OE#

CE#

Figure 14. WORD# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 15. WORD# Timings for W rite Operations

CE#

WE#

WORD#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

56 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std. Description 70R, 70 80 90 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 ns

tAVWL tAS Address Setup Time Min 0 ns

tASO Address Setup Time to OE# low during toggle bit polling Min 12 15 15 ns

tWLAX tAH Address Hold Time Min 45 ns

tAHT Address Hold Time From CE# or OE# high

during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 35 35 45 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggle bit polling Min 20 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 ns

tWHDL tWPH Write Pulse Width High Min 30 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 12.6 µs

Double Word Typ 16

tWHWH1 tWHWH1 Accelerated Programming Operation,

Double Word or Word (Note 2) Typ 10.5 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Write Recovery Time from RY/BY# Min 0 n s

tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

July 29, 2002 Am29PDL128G 57

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

tBUSY

otes:

. PA = program address, PD = program data, DOUT is the true data at the program address.

. Illustration shows device in word mode.

Figure 16. Program Operation Timings

WP#/ACC tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Figure 17. Accelerated Program Timing Diagram

58 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Status DOUT

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

otes:

. SA = sector address (for Sector Erase), VA = V al id Addr ess for readi ng sta tus dat a (see “Write Operation Status”.

. These waveforms are for the word mode.

Figure 18. Chip/Sector Erase Operation Timings

July 29, 2002 Am29PDL128G 59

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Data Valid

In Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

Figure 19. Back-to-back Read/Write Cycle Timings

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ6–DQ0

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

60 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status Valid

Status

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

July 29, 2002 Am29PDL128G 61

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

tRRB RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect Min 4 µs

RESET#

tVIDR

VID

VIL or VIH

VID

VIL or VIH

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

tRRB

Figure 23. Temporary Sector Unprotect Ti ming Diagram

62 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

1 µs

ESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Group Protect/Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector/Sector Block Protect and

Unprotect Timing Diagram

July 29, 2002 Am29PDL128G 63

PRELIMINARY

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std. Descripti on 70R, 70 80 90 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 ns

tAVWL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 45 ns

tDVEH tDS Data Setup Time Min 35 35 45 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Rec ov ery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setu p Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Puls e Width Min 35 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation

(Note 2) Word Typ 12.6 µs

Double Word Ty p 16.6

tWHWH1 tWHWH1 Accelerated Programming Operation,

Double Word or Word (Note 2) Typ 10.5 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec

64 Am29PDL128G July 29, 2002

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sect or addr ess, PD = prog ram data .

3. DQ7# is the compl ement of the data wri tten to t he devic e. D OUT is the data wri tten to t he devic e.

4. Waveforms are for the word mode.

Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings

July 29, 2002 Am29PDL128G 65

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycle s.

3. The typical chip programming t ime i s consi derabl y less than t he maxi mum chip programmi ng time lis ted, s ince most bytes

program faster than th e maximum p rogram t imes l isted .

4. In the pre-programming step of the Embed ded Erase algor ithm, all bytes a re prog rammed to 00h befo re eras ure.

5. System-level overhead is the time requir ed to execute the two- or four -bus-cycle sequence for the program command. See Tables

14–17 for further informati on on c ommand defi niti ons.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

FORTIFIED BGA PACKAGE CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Era se Time 0.2 10 s ec Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 100 sec

Double Word Program Time 16.6 330 µs

Excludes system level

overhead (Note 5)

Word Program Time 12.6 210 µs

Accelerated Double Word Program Time 14.5 120 µs

Accelerated Word Program Time 10.5 240 µs

Chip Program T ime

(Note 3) Double Word Mode 69.6 208 sec

Word Mode 105.7 317

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(incl udi ng A9, OE#, and RESE T#) –1.0 V 13 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 TBD TBD pF

COUT Output Capacitance VOUT = 0 T B D TB D pF

CIN2 Control Pin Capacitance VIN = 0 TBD TBD pF

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C10Years

125°C20Years

66 Am29PDL128G July 29, 2002

PRELIMINARY

PHYSICAL DIMENSIONS

LAB080—80-Ball Fortified Ball Grid Array

15 x 10 mm package

0.50 BSC.

N/A

15.00 mm x 10.00 mm

PACKAGE

LAB 080

NOM.

---

1.40

---

MAX.

10.00 BSC.

15.00 BSC.

---

MIN.

0.60

0.40

9.00 BSC.

7.00 BSC.

0.60 0.70

1.00 BSC.

0.50 1.00 BSC.

JEDEC

PACKAGE

SYMBOL

φb

NOTE

PACKAGE OUTLINE TYPE

DEPOPULATED SOLDER BALLS

MATRIX SIZE E DIRECTION

MATRIX FOOTPRINT

BALL PITCH - D DIRECTION

BALL PITCH - E DIRECTION

BODY SIZE

STANDOFF

BODY SIZE

BODY THICKNESS

PROFILE HEIGHT

BALL DIAMETER

MATRIX SIZE D DIRECTION

BALL COUNT

MATRIX FOOTPRINT

SOLDER BALL PLACEMENT

SD/SE

SIDE VIEW SEATING PLANE C

C0.25

C0.15

1.00 ± 0.5

TOP VIEW 2X

0.20

CORNER

A1 CORNER ID.

(INK OR LASER)

φ 0.50

1.00 ± 0.5

0.20

2X C

BOTTOM VIEW

CORNER

ABCDEFGHJK

CAB

NXφb

φ0.25

φ0.10 M

NOTES UNLESS OTHERWISE SPECIFIED:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 .

2. ALL DIMENSIONS ARE IN MILLIMETERS .

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010

(EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH .

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"

DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE

IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER

BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C .

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER

OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D

OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

July 29, 2002 Am29PDL128G 67

PRELIMINARY

REVISION SUMMARY

Revision A (October 29, 2001)

Initial release.

Revision A+1 (November 13, 2001)

Simultaneous Operation Block Diagram

Added drawing.

Table 13, Primary Vendor-Specific Extended Query

Corrected data for 4Dh and 4Eh addresses (dou-

ble-word mode).

Physical Dimensions

Added LAB080 package drawing.

Revision A+2 (February 8, 2002)

Global

Added 90 ns speed option. At this spe ed, tDF is 30 ns

and tOH is 5 ns. For all speeds, changed typical word

programming time to 8.6 µs, and typical double word

programming time to 12.6 µs.

Simultaneous Operation Block Diagram

Deleted BYTE# input.

Revision B (April 26, 2002)

Global

Added 70R (regulated voltage range) to speed op-

tions.

Orderi ng In form ati on

Added “V” to package marking.

Device Bus Operations

Corrected sector size references in sector address ta-

ble.

Password Protection Mode section: Clarifi ed that first

8 bytes of Se cSi Se ctor sho uld be reserved for th e

password. Added description of using pa ssword and

SecSi Sector concurrently.

SecSi Sector Flash Memory Region

Adde d section on u sing password an d SecSi Secto r

concurrently.

Table 13, Primary Vendor-Specific Extended Query

Corrected data for addresses 4D and 4Eh.

Comm and Definitions

Deleted PPB Status Command section.

Password Program Command section: Modified first

paragraph.

Password Unlock Command section: Modified second

paragraph.

PPB Lock Bit Set Comm and section: Modified entire

section.

Substantial modifications were made to the comma nd

definitions tab les and notes, inclu ding the following:

delete d the PPB S tatus comm and seque nce; added

bank address requirements to SecSi Sector com-

mand; s eparated m emory arr ay and sec tor protectio n

command sequences for easier reference.

DC Characteris tics

In Note 1 of the CMOS Compatible table, changed typ-

ical ICC current from 2 to 4mA/MHz. Changed ICC1 typi-

cal and maximum read currents, added currents for 10

MHz operation. Added specifications for intra-page

read current. Changed ICC6 typical current to 30 mA.

Revision B+1 (June 7, 2002)

Global

Changed data s heet status from Advance Information

to Preliminary.

AC Characteristics: Read-only Operations table

Changed tOE for 90 ns speed from 40 to 35 ns.

Changed tOH for 70 ns speeds from 4 to 5 ns.

AC Characteristics: Erase and Program Operations

table, Alternate CE# Controlled Erase and Program

Operations table

Changed tASO for 70 ns speed from 15 to 12 ns.

Changed tDS for 80 ns speed from 45 to 35 ns.

Changed tOEPH from 20 to 10 ns. Changed all typical

values from t WHWH1.

Erase and Programming Performance

Added or modified typical and maximum values to all

parameters in table except for typical sector erase

time.

Revision B+2 (July 29, 2002)

Global

Changed Simultanous Operation Flash to Simult anous

Read/ Write Flash.

Changed all references to DPB to DYB.

BGA Package Capacitance

Repla ced TS OP Pin C apacitanc e with FBGA Capaci-

tance data.

Table 7. Autoselect Codes (High Vo ltage Metho d)

Changed the A5 to A4 and A3 Sector P rotection Verifi-

cation fields from L to H.

68 Am29PDL128G July 29, 2002

PRELIMINARY

Table 9. Sector Protection Schemes

Added field: Unprotecte d-PPB not changeable, DYB is

changable.

Figure 1. In-System Sector Protection/Sector

Unprotection Algorithms

Added Note

T able 14. Memor y Array Command Definitions (x32

Mode)

T able 16. Memor y Array Command Definitions (x16

Mode)

Added SecSi Sector Factory Protec t and Sector Group

Protect Verify fields to tables.

Added Notes 8 and 9

Changed the Autoselect Sector Group Protect Verify

command variable from SA(3A) to SA02.

Table 15. Sector Protectio n Comm a nd Definiti ons

(x32 mode)

Table 17. Sector Protectio n Coma m nd Definiti ons

(x16 mode)

Changed variables in Cycle field for Password Pro-

gram (from 5 to 4), PPMLB Status (from 6 to 4), and

SPMLB Status (from 6 to 4).

Added Note 17

FBGA Ball Capacitance

Changed table from BGA Capacitance to Fortified

BGA C apacitanc e and m odified val ues within table to

TBD.

DC Characteristics

Deleted the IACC specification row.

Special Package Handling Instructions

Changed the instructions to include molded packages

(TSOP, BGA, PLCC, PDIP, SSOP).

CFI

Modified wording of last paragraph to read ‘reading

array data”.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.