LTM9013
1
9013fa
For more information www.linear.com/LTM9013
Typical applicaTion
FeaTures DescripTion
300MHz
Wideband Receiver
The LTM
®
9013 is a 300MHz wideband, low IF receiver.
Utilizing an integrated system in a package (SiP) technol-
ogy, it is a μModule
®
(micromodule) receiver that includes
a dual high speed 14-bit A/D converter, lowpass filter,
differential gain stages and a quadrature demodulator.
The LTM9013 is perfect for wideband I/Q receiver applica-
tions, with AC performance that includes 59dB SNR and
1.3dB frequency flatness from DC to 300MHz. A highpass
filter or simple AC coupling are used external to the device
for design flexiblity. The integrated on-chip broadband
transformers provide a 50Ω single-ended interface at
the RF input.
A 5V supply powers the demodulator and a 3.3V supply
powers the IF amplifiers for minimal distortion. A 1.8V
supply allows low power ADC operation. A separate output
supply allows the DDR LVDS outputs to drive 1.8V logic.
An optional multiplexer allows both channels to share a
digital output bus. An optional clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
64k Point FFT
fIN = 1950MHz, –1dBFS
applicaTions
n Integrated I/Q Demodulator, IF Amplifier, and Dual
14-Bit, 310Msps High Speed ADC
n External Highpass Filter Allows Bandwidth
Adjustment
n 300MHz Lowpass Filter for Each Channel
n RF Input Frequency Range: 0.7GHz to 4GHz
n 50Ω Single-Ended RF Port
n 50Ω Differential LO Port
n Frequency Flatness: 1.3dB Typical
n 66dBc IM3 Level at –7dBFS
n 59dB SNR at –1dBFS
n Parallel DDR LVDS Outputs
n Clock Duty Cycle Stabilizer
n Low Power: 2.6W
n Shutdown and Nap Modes
n 15mm × 15mm BGA Package
n Telecommunications
n Wideband, Low IF Receivers
n Digital Predistortion Receivers
n Cellular Base Stations L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation.
VCC2
3.3V
VCC1
5V
GAIN_Q
0.01µF
0.01µF
15nH
0.01µF
0.01µF
15nH
GND
LO IN
15nH
15nH
6.8pF
100Ω
100Ω
100Ω
5V
GAIN_I
VDD
1.8V
LTM9013
ADC
ADC
GND
9013 TA01
CLKOUT
SDOSDISCK CS
ADC CLK
OVDD
1.8V
OF
100Ω
5V 6.8pF
0°
90°
PAR/SER
LNA
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–60
–40
–20
0
128
9013 TA01b
–80
–100
–70
–50
–30
–10
–90
–110
–120 32 64 96
16 144
48 80 112 160
LTM9013
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For more information www.linear.com/LTM9013
pin conFiguraTionabsoluTe MaxiMuM raTings
Supply Voltage
VCC1 ...................................................... –0.3V to 5.5V
VCC2 ...................................................... –0.3V to 3.8V
VDD, OVDD ............................................. –0.3V to 2.0V
Analog Input Voltage
EN, EIP2, REF, IP2I, IP2Q ...........–0.3V to VCC1 + 0.3V
PAR/SER, SENSE ..................... –0.3V to (VDD + 0.2V)
Digital Input Voltage (Note 3)
CLK+, CLK– ............................. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4)
CS, SDI, SCK ......................................... –0.3V to 3.9V
RF Input DC Voltage ............................................... ±0.1V
LO+, LO– Input DC Voltage .............–0.3V to VCC1 + 0.3V
Analog Input Current
+IN_I, –IN_I, +IN_Q, –IN_Q ............................ ±20mA
GAIN_I, GAIN_Q, EN_I, EN_Q, SHDN_I,
SHDN_Q........................................................... ±10mA
LO+, LO– Input Power ........................................ +10dBm
RF Input Power ..................................................+20dBm
Analog Input Power, Continuous
+IN_I, –IN_I, +IN_Q, –IN_Q ........................... +15dBm
Analog Input Power, 100μs Pulse
+IN_I, –IN_I, +IN_Q, –IN_Q ...........................+20dBm
Analog Output Voltage
+OUT_I, –OUT_I,
+OUT_Q, –OUT_Q .........................2.5V to VCC1 + 0.3V
Digital Output Voltage
SDO ..................................................... –0.3V to 3.9V
Except SDO ............................–0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTM9013C ............................................... 0°C to 70°C
LTM9013I.............................................–40°C to 85°C
Storage Temperature Range .................. –55°C to 125°C
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the RF and LO inputs of the
LTM9013.
(Notes 1, 2)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
234567
TOP VIEW
BGA PACKAGE
196-LEAD (15mm × 15mm × 2.82mm)
8 9 10 11 12 13 14
TJMAX = 125°C, θJA = 20°C/W, θJCbottom = 6°C/W, θJCtop =19°C/W, θJB =9°C/W
θ VALUES DEFINED PER JESD 51-12
WEIGHT = 1.35g
LTM9013
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For more information www.linear.com/LTM9013
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PRF = –5dBm, PLO = 0dBm (Notes 5, 7) unless otherwise noted.
orDer inForMaTion
LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTM9013CY-AA#PBF LTM9013CY-AA#PBF LTM9013Y-AA 196-Lead (15mm × 15mm × 2.8mm) BGA 0°C to 70°C
LTM9013IY-AA#PBF LTM9013IY-AA#PBF LTM9013Y-AA 196-Lead (15mm × 15mm × 2.8mm) BGA –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
RF Input Frequency Range No External Matching (Mid Band)
with External Matching (Low Band, High Band) 1.5 to 2.7
0.7 to 4.0 GHz
GHz
LO Input Frequency Range No External Matching (Mid Band)
With External Matching (Low Band, High Band) 1.5 to 2.7
0.7 to 4.0 GHz
GHz
IF Frequency Range 0.5 to 300 MHz
RF Input Return Loss ZO = 50Ω, 1.5GHz to 2.7GHz, Internally Matched >10 dB
LO Input Return Loss ZO = 50Ω, 1.5GHz to 2.7GHz, Internally Matched >10 dB
RF Input Power for –1dBFS RF = 2140MHz, LO = 1990MHz (Figure 14) –5 dBm
LO Input Power –6 to +6 dBm
I/Q Gain Mismatch RF = 2140MHz, LO = 1990MHz (Figure 14) 0.15 dB
I/Q Phase Mismatch RF = 2140MHz, LO = 1990MHz (Figure 14) 1 Deg
LO to RF Leakage LO = 1990MHz –55 dBm
RF to LO Isolation RF = 2140MHz 58 dBm
Gain Flatness (Notes 5, 6) fIF = 500kHz to 300MHz (Figure 14) 0.5 dB
Lowpass Filter Cutoff Frequency 0.5dB Point 300 MHz
Resolution (No Missing Codes) l14 Bits
Integral Linearity Error (Note 8) Differential Analog Input ±4.5 LSB
Differential Linearity Error Differential Analog Input –1 ±0.35 1 LSB
Offset Error (Note 9) –186 ±62 186 LSB
LTM9013
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DynaMic accuracy
analog inpuTs anD ouTpuTs
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. PRF = –5dBm, PLO = 0dBm (Notes 5, 7) unless otherwise noted.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IIP3 Input 3rd Order Intercept, 1 Tone RF = 2140MHz, LO = 1990MHz 30 dBm
IIP2 Input 2nd Order Intercept, 1 Tone RF = 2140MHz, LO = 1990MHz 56 dBm
SNR Signal-to-Noise Ratio at –1dBFS RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
l
59 59
62 dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
l
60 65
70 dB
dB
Spurious Free Dynamic Range
4th or Higher RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
75
80 dB
dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
l
58 58
61 dBFS
dBFS
IMD3 Intermodulation Distortion at –7dBFS per
Tone RF = 2140MHz and 2141MHz, LO = 1990MHz
(Figure 14) 66 dB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Demodulator Adjust Inputs (IP2I, IP2Q)
Input Voltage 0 1.3 V
Input Impedance 2||1 kΩ||pF
Settling Time For Step Input; Output with 90% of Final Value 2 μs
Demodulator Adjust Input (REF)
Input Voltage 0.4 0.5 0.7 V
Input Impedance 8||1 MΩ||pF
Amplifier Analog Inputs (+IN_I, –IN_I, +IN_Q, –IN_Q)
Differential Input Resistance VIN(DIFF) = 100mV 49 57 65 Ω
Input Common Mode Voltage 640 mV
Minimum Input Frequency (3dB Corner) 500 kHz
Amplifier Gain Control Analog Inputs (GAIN_I, GAIN_Q)
RIN Input Resistance GAIN_I, GAIN_Q = 1.0V, RIN = 1V/∆IIL
l
7.8
7.2 9.2 10.6
12.8 kΩ
kΩ
IIL Input Low Current GAIN_I, GAIN_Q = 0V
l
–9
–10 –5 –1
–1 µA
µA
Gain Control Range VGAIN = 0.2V to 1.2V l27.5 29 30.5 dB
Temperature Coefficient of Gain at Fixed
Gain Control Voltage –0.007 dB/°C
Gain Control Slope Gain Control Voltage = 0.2V to 1V, Slope of the
Least-Square Fit Line
l30.6 32.6 34.7 dB/V
Average Conformance Error to Gain
Slope Line Gain Control Voltage = 0.2V to 1V
, Standard
Error to the Least-Square Fit Line 0.12 dB
Maximum Conformance Error to Gain
Slope Line Gain Control Voltage = 0.2V to 1V
, Maximum
Error to the Least-Square Fit Line 0.2 dB
LTM9013
5
9013fa
For more information www.linear.com/LTM9013
analog inpuTs anD ouTpuTs
DigiTal inpuTs anD ouTpuTs
analog inpuTs anD ouTpuTs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ADC Analog Inputs (SENSE)
Input Leakage Current 1.1V < SENSE < 1.2V –1 1 μA
Demodulator Analog Outputs (+OUT_I, –OUT_I, +OUT_Q, –OUT_Q)
Common Mode Voltage VCC1 – 1.5V V
Differential Output Impedance 50||6 Ω||pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Demodulator Logic Inputs (EN, EIP2)
VIH High Level Input Voltage VCC = 5V l2 V
VIL Low Level Input Voltage VCC = 5V l0.3 V
Input Pull-Up Resistance VCC = 5V, VEN = 4.4V to 2.6V 100 kΩ
EIP2 Input Current EIP2 = 5V 40 μA
Turn-On Time 0.2 µs
Turn-Off Time 0.8 µs
I and Q Channel Logic Inputs (EN_I, EN_Q, SHDN_I, SHDN_Q)
VIH High Level Input Voltage VCC = 3.3V l2.2 V
VIL Low Level Input Voltage VCC = 3.3V l0.8 V
Input Pull-Up Resistance VCC = 3.3V, VEN_I,EN_Q = 0V to 0.5V 100 kΩ
Input High Current EN_I, EN_Q = 2.2V, SHDN_I, SHDN_Q = 2.2V –30 –15 –1 µA
Input Low Current EN_I, EN_Q = 0.8V, SHDN_I, SHDN_Q = 0.8V –60 –30 –1 µA
ADC Encode Clock Inputs (CLK+, CLK–)
Differential Input Voltage VDD = 1.8V l0.2 V
Common Mode Input Voltage Internally Set
Externally Set
l
1.1 1.2
1.5 V
V
Input Resistance 10 kΩ
Input Capacitance (Note 10) 2 pF
ADC Logic Inputs (SDI, SCK, CS)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
Input Current VIN = 0V to 3.6V l–10 10 μA
Input Capacitance (Note 10) 3 pF
ADC Logic Inputs (PAR/SER)
Input Leakage Current 0 < PAR/SER < VDD –1 1 μA
ADC Logic Output (SDO)
Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
Output Capacitance (Note 10) 4 pF
LTM9013
6
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For more information www.linear.com/LTM9013
DigiTal inpuTs anD ouTpuTs
power requireMenTs
TiMing characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Data Outputs (OVDD = 1.8V)
Differential Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125 350
175 454
250 mV
mV
Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125 1.250
1.250 1.375
1.375 V
V
On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC1 Demodulator and Amplifier Supply Voltage l4.75 5.25 V
VCC2 Amplifier Analog Supply Voltage l2.7 3.3 3.6 V
VDD ADC Analog Supply Voltage l1.74 1.8 1.9 V
OVDD ADC Digital Output Supply Voltage l1.74 1.8 1.9 V
ICC1 Demodulator and Amplifier Supply Current l285 330 mA
ICC1(SHDN) Demodulator and Amplifier Shutdown
Current EN = 0V, EN_I, EN_Q = 3.3V, SHDN_I,
SHDN_Q = 0V
l16 20 mA
ICC2 Amplifier Supply Current l132 160 mA
IDD ADC Supply Current l335 385 mA
IOVDD Digital Supply Current 3.5mA Mode 80 90 mA
ADC Sleep Power ADC Programmed for Sleep Mode, No CLK 5 mW
Total Power Dissipation 2.6 W
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSSampling Frequency l1 310 MHz
tLCLK Low Time Duty Cycle Stabilizer Off (Note 10)
Duty Cycle Stabilizer On (Note 10)
l
l
1.5
1.2 1.6
1.6 50
50 ns
ns
tHCLK High Time Duty Cycle Stabilizer Off (Note 10)
Duty Cycle Stabilizer On (Note 10)
l
l
1.5
1.2 1.6
1.6 50
50 ns
ns
tJITTER Sample-and-Hold Acquisition Delay Time
Jitter 0.15 psRMS
tAP Sample-and-Hold Acquisition Delay Time 1 ns
DATA Outputs (Note 10)
tDCLK to DATA Delay CL = 5pF l1.7 2 2.3 ns
tCCLK to CLKOUT Delay CL = 5pF l1.3 1.6 2 ns
tSKEW DATA to CLKOUT Skew tD – tC l0.3 0.4 0.55 ns
LTM9013
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9013fa
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TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SPI Port Timing (Note 10)
tSCK SCK Period Write Mode
Readback Mode CSDO = 20pF, RPULLUP = 2kΩ
l
l
40
250 ns
ns
tSCS to SCK Set-up Time 5 ns
tHSCK to CS Hold Time 5 ns
tDS SDI Set-Up Time 5 ns
tDH SDI Hold Time 5 ns
tDO SCK Falling to SDO Valid Readback Mode CSDO = 20pF, RPULLUP = 2kΩ 125 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD,
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: Using test circuit 1 (see Figure 14 Design Example in Applications
Information section).
Note 6: Signal applied to the ±INn pins and measures only the amplifier
and ADC.
Note 7: VCC1 = 5V, VCC2 = 3.3V, VDD = 1.8V, EN = 5V, EN_I, EN_Q = 0V,
GAIN_I, GAIN_Q = 1.2V, SHDN_I, SHDN_Q = 3.3V, SENSE = 1.15V,
fS = 310MHz, unless otherwise noted.
Note 8: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 9: DC offset is the ADC output code with no RF or LO input signal
applied the module.
Note 10: Guaranteed by design, not subject to test
LTM9013
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Typical perForMance characTerisTics
HD2 at 150MHz IF vs LO Power HD2 at 150MHz IF vs RF Drive
HD3 at 150MHz IF vs RF Drive IM3 at 150MHz vs RF Drive LO to RF Isolation
Baseband Frequency Response
64K Point FFT, fIN = 1925MHz,
1975MHz, –7dBFS per Tone
SNR at 150MHz IF vs RF Drive
BASEBAND FREQUENCY (MHz)
–6
AMPLITUDE (dB)
–4
–2
0
–5
–3
–1
100 200 300 400
9013 G01
500500 150 250 350 450
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–60
–40
–20
0
128
9013 G03
–80
–100
–70
–50
–30
–10
–90
–110
–120 32 64 96
16 144
48 80 112 160
RF DRIVE (dBm)
–5
58.0
SNR (dB)
58.5
59.0
59.5
60.0
60.5
61.0
0 5 10 15
9013 G04
LO POWER (dBm)
–22
–80
HD2 (dBc)
–75
–65
–60
–55
2 6 10
–45
9013 G05
–70
–18 –14 –10 –6 –2
–50
HD2, I CHANNEL
HD2, Q CHANNEL
RF DRIVE (dBm)
–5
–70
HD2 (dBc)
–65
–60
–55
–50
–45
–40
0 5 10 15
9013 G06
HD2, I CHANNEL
HD2, Q CHANNEL
RF DRIVE (dBm)
–5
–55
–50
–40
10
9013 G07
–60
–65
0 5 15
–70
–75
–45
HD3 (dBc)
RF DRIVE PER TONE (dBm)
–12
IM3 (dBc)
–60
–55
–50
4 86
9013 G08
–65
–70
–80 –8 –4 0
–10 10
–6 –2 2
–75
–40
–45
LO FREQUENCY (GHz)
1.5
ISOLATION (dB)
–40
–30
–20
2.3 2.4
9013 G09
–50
–60
–80 1.7 1.9 2.1
1.6 2.5
1.8 2.0 2.2
–70
0
–10
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–60
–40
–20
0
128
9013 G02
–80
–100
–70
–50
–30
–10
–90
–110
–120 32 64 96
16 144
48 80 112 160
64k Point FFT, fIN = 1950MHz,
–1dBFS
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pin FuncTions
Supply Pins
VCC1 (Pin B7): Analog 5V Supply for Demodulator and
Amplifiers. The specified operating range is 4.75V to 5.25V.
The voltage on this pin provides power for the demodulator
and amplifier stages only and is internally bypassed to GND.
VCC2 (Pins A2, A3, A12, A13, D1, D12): Analog 3.3V Sup-
ply for Amplifiers. The specified operating range is 2.7V to
3.6V. VCC2 is internally bypassed to GND.
VDD (Pins J6, J9): Analog 1.8V Supply for ADC. The
specified operating range is 1.74V to 1.9V. VDD is internally
bypassed to GND.
OVDD (Pins N5, N10): Positive 1.8V Supply for the Digital
Output Drivers. The specified operating range is 1.74V to
1.9V. OVDD is internally bypassed to GND.
GND: Analog Ground. See Pin Configuration table for pin
locations.
Analog Inputs
RF (Pin A10): RF Input Pin. This is a single-ended 50Ω
terminated input. No external matching network is required
for the 1.5GHz to 2.7GHz band. An external series inductor
(and/or shunt capacitor) may be required for impedance
transformation to 50Ω in the band from 700MHz to 1.5GHz,
or for the band from 2.7GHz to 4GHz (see Figure 2). If the
RF source is not DC blocked, a series blocking capacitor
should be used. Otherwise, damage to the IC may result.
LO+, LO– (Pins A6, A5): Local Oscillator Input Pins. This is a
differential 50Ω terminated input. An external series induc-
tor (and/or shunt capacitor) may be required for impedance
transformation to 50Ω in the band from 700MHz to 1.5GHz,
or for the band from 2.7GHz to 4GHz (see Figure 4). If the
LO source is not DC blocked, a series blocking capacitor
must be used. Otherwise, damage to the IC may result.
+IN_I, –IN_I (Pins E10, E11): Channel I Signal Input. This
is a differential input that drives the amplifier. It has an
internally generated DC bias. Series blocking capacitors
are required between these pins and +OUT_I, –OUT_I.
+IN_Q, –IN_Q (Pins E4, E5): Channel Q Signal Input. This
is a differential input that drives the Amplifier. It has an
internally generated DC bias. Series blocking capacitors
are required between these pins and +OUT_Q, –OUT_Q.
GAIN_I (Pin C12): I Channel Gain Control Input. This is
an input that controls the gain of the amplifier. This pin is
internally pulled low with 10kΩ to GND. The gain control
slope is approximately 32dB/V with a gain control range
of 0.1V to 1.1V.
GAIN_Q (Pin C1): Q Channel Gain Control Input. This is
an input that controls the gain of the amplifier. This pin is
internally pulled low with 10kΩ to GND. The gain control
slope is approximately 32dB/V with a gain control range
of 0.1V to 1.1V.
CLK+, CLK– (Pins J5, K5): ADC Clock Input. Conversion
starts on the rising edge of CLK+.
IP2_I (Pin C10): IP2 Adjustment Pin for I Channel.
IP2_Q (Pin D10): IP2 Adjustment Pin for Q Channel.
REF (Pin D8): Voltage Reference Input for Analog Control
Voltage Pins.
SENSE (Pin J8): ADC Reference Programming Pin. Con-
necting SENSE to VDD selects the internal reference and
a 1.32V input range.
Analog Outputs
+OUT_I, –OUT_I (Pins F10, F11): Channel I Signal Output.
This is a differential output from the demodulator. The DC
bias point is VCC1 – 1.5V for each pin. These pins must
have an external 100Ω or inductor pull-up to VCC1. Series
blocking capacitors are required between these pins and
+IN_I, –IN_I.
+OUT_Q, –OUT_Q (Pins F4, F5): Channel Q Signal Output.
This is a differential output from the demodulator. The DC
bias point is VCC1 – 1.5V for each pin. These pins must
have an external 100Ω or inductor pull-up to VCC1. Series
blocking capacitors are required between these pins and
+IN_Q, –IN_Q.
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pin FuncTions
Control Pins
EN (Pin B8): Demodulator Enable Pin. If EN = high (the
input voltage is higher than 2.0V), the demodulator is en-
abled. If EN = low (the input voltage is less than 1.0V), it
is disabled. If the enable function is not needed, then this
pin should be tied to VCC1.
EIP2 (Pin D6): Demodulator IP2 Adjust Enable Pin. Pin is
internally pulled low with 200kΩ to GND. If EIP2 = high
(the input voltage is higher than 2.0V), the IP2 adjust
circuit is enabled. If EIP2 = low (the input voltage is less
than 1.0V), it is disabled.
NC1, NC2, NC3 (Pins C6, C9, D9): Do Not Connect.
EN_I (Pin C14): First Amplifier I Channel Enable Pin. Pin
is internally pulled high with 100kΩ to VCC2. Assert pin to
a low voltage to enable the amplifier. Connect pin to GND
if enable function is not used.
EN_Q (Pin C3): First Amplifier Q Channel Enable Pin. Pin
is internally pulled high with 100kΩ to VCC2. Assert pin to
a low voltage to enable the amplifier. Connect pin to GND
if enable function is not used.
SHDN_I (Pin D14): Amplifier I Channel Shutdown Pin.
Pin is internally pulled high with 100kΩ to VCC2. Assert
pin to a low voltage to shut down the amplifier. Proper
sequencing of the EN_I and SHDN_I pins is required to
avoid non-monotonic output signal behavior. Connect pin
to VCC2 if shutdown function is not used.
SHDN_Q (Pin D3): Amplifier Q Channel Shutdown Pin.
Pin is internally pulled high with 100kΩ to VCC2. Assert
pin to a low voltage to shut down the amplifier. Proper
sequencing of the EN_Q and SHDN_Q pins is required to
avoid non-monotonic output signal behavior. Connect pin
to VCC2 if shutdown function is not used.
SDI (Pin K11): Serial Interface Data Input. In serial pro-
gramming mode, (PAR/SER = GND), SDI is the serial
interface data input. Data on SDI is clocked into the mode
control registers on the rising edge of SCK. In the parallel
programming mode (PAR/SER = VDD), SDI selects 3.5mA
or a 7.5mA LVDS output current (see Table 4). SDI can be
driven with 1.8V to 3.3V logic.
SCK (Pin J11): Serial Interface Clock Input. In serial
programming mode (PAR/SER = GND), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK can be used to place the part in the
low power sleep mode (see Table 4). SCK can be driven
with 1.8V to 3.3V logic.
CS (Pin K10): Serial Interface Chip Select Input. In serial
programming mode (PAR/SER = GND), CS is the serial
interface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD), CS
controls the clock duty stabilizer (see Table 4). CS can be
driven with 1.8V to 3.3V logic.
PAR/SER (Pin J10): Programming Mode Selection Pin.
Connect to GND to enable the serial programming mode
where CS, SCK, SDI, SDO become a serial interface that
controls the ADC operating modes. Connect to VDD to enable
the parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the ADC operating modes. PAR/SER should be connected
directly to GND or VDD and not be driven by a logic signal.
Digital Outputs
SDO (Pin L11): Serial Interface Data Output. In serial pro-
gramming mode (PAR/SER = GND), SDO is the optional
serial inter-face data output. Data on SDO is read back from
the mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2kΩ pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
LVDS Digital Outputs
The following pins are differential LVDS outputs. The output
current level is programmable. There is an optional internal
100Ω termination resistor between the pins of each LVDS
output pair.
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pin FuncTions
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14
AGND VCC2 VCC2 GND LO–LO+GND GND GND RF GND VCC2 VCC2 GND
BGND GND GND GND GND GND VCC1 EN GND GND GND GND GND GND
CGAIN_Q GND EN_Q GND GND NC1 GND GND NC2 IP2_I GND GAIN_I GND EN_I
DVCC2 GND SHDN_Q GND GND EIP2 GND REF NC3 IP2_Q GND VCC2 GND SHDN_I
EGND GND GND +IN_Q –IN_Q GND GND GND GND +IN_I –IN_I GND GND GND
FGND GND GND +OUT_Q –OUT_Q GND GND GND GND +OUT_I –OUT_I GND GND GND
GGND GND GND GND GND GND GND GND GND GND GND GND GND GND
HGND GND GND GND GND GND GND GND GND GND GND GND GND GND
JGND GND GND GND CLK+VDD GND SENSE VDD PAR/SER SCK GND GND GND
KOF–OF+GND GND CLK–GND GND GND GND CS SDI GND GND GND
LDB01–DB01+ GND GND GND GND GND GND GND GND SDO GND DA1213–DA1213+
MDB23–DB23+DB45–DB45+GND GND GND GND GND GND DA89–DA89+DA1011–DA1011+
NDB67–DB67+DB89–DB89+OVDD GND GND GND GND OVDD DA45–DA45+DA67–DA67+
PGND DB1213+DB1213–DB1011+DB1011–GND CLKOUT–CLKOUT+GND DA23+DA23–DA01+DA01–GND
Top View of BGA Package (Looking Through Component)
CLKOUT+, CLKOUT– (Pins P8, P7): ADC Data Output Clock.
DB0_1–/DB0_1+ to DB12_13–/DB12_13+ (See Pin Con-
figuration table for pin locations): Q Channel ADC Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DB0,
DB2, DB4, DB6, DB8, DB10, DB12) appear when CLKOUT+
is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11,
DB13) appear when CLKOUT+ is high.
DA0_1–/DA0_1+ to DA12_13–/DA12_13+ (See Pin Con-
figuration table for pin locations): Q Channel ADC Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DA0,
DA2, DA4, DA6, DA8, DA10, DA12) appear when CLKOUT+
is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11,
DA13) appear when CLKOUT+ is high.
OF+, OF– (Pins K2, K1): Overflow/Underflow Outputs. OF+
is high when an overflow/underflow has occurred.
LTM9013
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Figure 1. Functional Block Diagram
blocK DiagraM
VCC2
IN_I+
IN_I–
DA12_13
OVDD
VDD
•
•
•
•
•
•
DA0_1
CLKOUT+
CLKOUT–
DB12_13
DB0_1
9013 F01
OF–
OF+
SENSE
VCC1
OUT_I+
OUT_I–
CLOCK DUTY
CYCLE CONTROL
RANGE
SELECT
ADC
CONTROL
SD0
SDI
SCK
GAIN_I
GAIN_Q
GND
CLK–
CLK+
SHDN_I
EN_I
SHDN_Q
EN_Q
CS
PAR/SER
IP2
CONTROL
0°
RF
90°
IP2_Q
IP2_I
EIP2
REF
OUT_Q+
OUT_Q–
LO–
LO+
EN
IN_Q+
IN_Q–
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TiMing DiagraMs
Double-Data Rate Output Timing, All Data Are Differential LVDS
tH
tC
tD
tL
OF_AN-5 OF_BN-5 OF_AN-4 OF_BN-4 OF_AN-3 OF_BN-3
t
SKEW
DA0N-5 DA1N-5 DA0N-4 DA1N-4 DA0N-3 DA1N-3
DA12N-5 DA13N-5 DA12N-4 DA13N-4 DA12N-3 DA13N-3
DB0N-5 DB1N-5 DB0N-4 DB1N-4 DB0N-3 DB1N-3
DB12N-5 DB13N-5 DB12N-4 DB13N-4 DB12N-3 DB13N-3
tAP
N + 1
N + 2
N + 3
N
CLK–
CLK+
DB0_1+
DB0_1–
DA0_1+
DA0_1–
DB12_13
+
DB12_13
–
DA12_13
+
DA12_13
–
CLKOUT+
CLKOUT–
OF+
OF–
9013 TD01
LTM9013
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TiMing DiagraMs
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO
HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
9013 TD02
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
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operaTion
Description
The LTM9013 is a low IF receiver targeting wideband I/Q
receiver and digital predistortion applications, such as wire-
less infrastructure with RF input frequencies up to 4GHz.
It is an integrated μModule receiver utilizing system in a
package (SiP) technology to combine a dual, high speed
14-bit A/D converter, 300MHz lowpass filters, one low
noise, differential amplifier per channel with adjustable
gain and an I/Q demodulator with IP2 adjustment.
The following sections describe in further detail the opera-
tion of each section.
Demodulator Operation
The RF signal is applied to the inputs of the RF trans-
conductance amplifiers and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated from an external LO source by preci-
sion 90° phase shifters.
Broadband transformers are integrated at the RF input to
enable a single-ended RF interface. In the mid frequency
band (1.5GHz to 2.7GHz), both RF and LO ports are inter-
nally matched to 50Ω. No external matching components
are needed. For the low (700MHz to 1.5GHz), and high
(2.7GHz to 4GHz) frequency bands a simple network with
series inductors and/or shunt capacitors can be used as
the impedance matching network.
Amplifier Operation
Each channel of the LTM9013 consists of a single stage of
AC-coupled, low noise and low distortion fully differential op
amp/ADC driver. Each stage is followed by a 4-pole lowpass
filter using a high speed, high performance operational
amplifier and precision passive components. The stage
is designed to provide maximum gain and phase flatness.
The LTM9013 variable gain amplifier employs an interpo-
lated, tapped attenuator circuit architecture to generate
the variable-gain characteristic. The tapped attenuator
is fed to a buffer and output amplifier to complete the
differential signal path. This circuit architecture provides
good RF input power handling capability along with a
constant output noise and output IP3 characteristic that
are desirable for most IF signal chain applications. The
internal control circuitry takes the gain control signal from
the GAIN terminals and converts this to an appropriate set
of control signals to the attenuator ladder. The attenuator
control circuit ensures that the linear-in-dB gain response
is continuous and monotonic over the gain range for both
slow and fast moving input control signals while exhibit-
ing very little input impedance variation over gain. These
design considerations result in a gain-vs-VG characteristic
with a ±0.1dB ripple and a 0.5µs gain response time that
is slower than a similar digital step attenuator design.
An often overlooked characteristic of an analog-controlled
VGA is upconverted amplitude modulation (AM) noise
from the gain control terminals. The VGA behaves as a
2-quadrant multiplier, so some minimal care is required
to avoid excessive AM sideband noise generation. The
following table demonstrates the effect of the baseline
20nV/√Hz equivalent input control noise from the LTM9013
circuit along with the effect of a higher combined input
noise due to a noisy external control circuit.
CONTROL INPUT TOTAL NOISE
VOLTAGE (nV/√Hz)
PEAK AM NOISE AT 10kHz OFFSET
NEAR MAXIMUM GAIN (dBc/Hz)
20 –142
40 –136
70 –131
100 –128
200 –122
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operaTion
The baseline equivalent 20nV/√Hz input noise is seen to
produce worst-case AM sidebands of –142dBc/Hz which is
near the –147dBm/Hz output noise floor at maximum gain
for a nominal 0dBm output signal. An input control noise
voltage less than 80nV/√Hz is generally recommended to
avoid measurable AM sideband noise. While op amp control
circuit output noise voltage is usually below 80nV/√Hz,
some low power DAC outputs exceed 150nV/√Hz. DACs
with output noise in the range of 100nV/√Hz to 150nV/√Hz
can usually be accommodated with a suitable 2:1 or 3:1
resistor divider network on the DAC output to suppress the
noise amplitude by the same ratio. Noisy DACs in excess
of 150nV/√Hz should be avoided if minimal AM noise is
important in the application.
ADC Input Network
The passive network between the amplifier output and
the ADC input stages provides a 0.1dB ripple, 4th order
Chebyshev lowpass filter response.
Converter Operation
The LTM9013 includes a 2-channel, 14-bit 310Msps A/D
converter powered by a single 1.8V supply. A sampled
input will result in a digitized value six cycles later. The
analog inputs are driven differentially by the VGA. The
encode inputs should be driven differentially for optimal
performance. The digital outputs are double data rate LVDS.
Additional features can be chosen by programming the
mode control registers through a serial SPI port.
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RF Input
Figure 2 shows the mixer’s RF input which consists of an
integrated transformer and high linearity transconduc-
tance amplifiers. The primary side of the transformer is
connected to the RF input pin. The secondary side of the
transformer is connected to the differential inputs of the
transconductance amplifiers. Under no circumstances
should an external DC voltage be applied to the RF input
pin. DC current flowing into the primary side of the trans-
former may cause damage to the integrated transformer.
A series blocking capacitor should be used to AC-couple
the RF input port to the RF signal source.
Figure 3. RF Input Return Loss with External Matching
Figure 2. RF Input Interface
9013 F02
EXTERNAL
MATCHING
NETWORK FOR
LOW BAND AND
MID BAND
RF
INPUT RF
C20 C21
C19 L5
TO I-MIXER
LTM9013
TO Q-MIXER
The RF input port is internally matched over a wide fre-
quency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. When the
part is operated at lower frequencies, however, the input
return loss can be improved with the matching network
shown in Figure2. Shunt capacitors C20, C21 and series
inductor L5 can be selected for optimum input impedance
matching at the desired frequency as illustrated in Figure3.
C19 serves as a series DC blocking capacitor.
The RF input impedance and S11 parameters (without
external matching components) are listed in Table 1.
FREQUENCY (MHz)
100
–30
RETURN LOSS (dB)
–25
–20
–15
–10
0
1000 10000
9013 F03
–5
NO MATCHING
ELEMENTS
1.95GHz MATCH
(3.3nH + 1.5pF)
Table 1. RF Input Impedance
FREQUENCY MAGNITUDE PHASE R X
500MHz 0.96 41.2 92.3Ω –95.4Ω
600MHz 0.93 50.6 85.3Ω –62.0Ω
700MHz 0.90 61.3 76.0Ω –36.0Ω
800MHz 0.81 71.3 66.9Ω –17.6Ω
900MHz 0.70 90.7 49.4Ω 0.4Ω
1000MHz 0.74 109.6 34.8Ω 8.5Ω
1100MHz 0.78 122.1 25.9Ω 11.2Ω
1200MHz 0.82 130.2 20.4Ω 12.1Ω
1300MHz 0.81 136.9 16.8Ω 11.6Ω
1400MHz 0.83 143.6 13.2Ω 10.9Ω
1500MHz 0.83 149.0 11.0Ω 9.7Ω
1600MHz 0.83 157.2 7.9Ω 7.7Ω
1700MHz 0.84 165.3 5.8Ω 5.2Ω
1800MHz 0.83 175.9 4.7Ω 1.5Ω
1900MHz 0.84 –173.1 4.8Ω –2.5Ω
2000MHz 0.81 –161.6 7.3Ω –6.2Ω
2100MHz 0.81 –150.2 10.9Ω –9.2Ω
2200MHz 0.78 –141.5 15.2Ω –10.5Ω
2300MHz 0.75 –132.7 20.2Ω –10.9Ω
2400MHz 0.73 –129.9 22.2Ω –10.6Ω
2500MHz 0.68 –126.8 24.9Ω –9.7Ω
2600MHz 0.66 –128.6 24.3Ω –9.4Ω
2700MHz 0.63 –129.1 24.8Ω –8.8Ω
2800MHz 0.62 –126.9 26.0Ω –8.6Ω
2900MHz 0.61 –124.9 27.2Ω –8.5Ω
3000MHz 0.59 –117.7 31.5Ω –7.6Ω
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LO Input Port
The mixer’s LO input interface is shown in Figure 4. The
input consists of a precision quadrature phase shifter
which generates 0° and 90° phase-shifted LO signals for
the LO buffer amplifiers driving the I/Q mixers. Under no
circumstances should an external DC voltage be applied
to the input pin. DC current flowing into the primary side
of the transformer may damage the transformer.
Figure 5. LO Input Return Loss with External Matching
Figure 4. LO Input Interface
LO
INPUT
9013 F04
LO+
LO–
LTM9013
C22
C24
T1
LO QUADRATURE
GENERATOR AND
BUFFER AMPLIFIERS
The LO input port is internally matched over a wide fre-
quency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. The LO input
impedance and S11 parameters (without external matching
components) are listed in Table 2. Outside this frequency
range, the impedance match can be improved using series
capacitor C22 and shunt capacitor C24.
FREQUENCY (MHz)
100
–30
RETURN LOSS (dB)
–25
–20
–15
–10
0
1000 10000
9013 F05
–5
NO MATCHING
ELEMENTS
1.8GHz MATCH
(0.5pF + 6.8nH)
Table 2. LO Input Impedance
FREQUENCY MAGNITUDE PHASE R X
500MHz 0.71 –70.3 67.7Ω 15.5Ω
600MHz 0.66 –83.9 55.0Ω 3.6Ω
700MHz 0.66 –97.1 44.5Ω –3.3Ω
800MHz 0.62 –119.8 29.8Ω –8.3Ω
900MHz 0.55 –144.9 20.2Ω –6.5Ω
1000MHz 0.51 –177.8 16.1Ω –0.4Ω
1100MHz 0.48 146.5 22.2Ω 5.3Ω
1200MHz 0.52 115.0 34.3Ω 6.1Ω
1300MHz 0.57 87.9 51.6Ω –0.9Ω
1400MHz 0.62 70.5 66.9Ω –12.4Ω
1500MHz 0.66 55.0 84.7Ω –30.5Ω
1600MHz 0.67 44.0 101.4Ω –46.6Ω
1700MHz 0.69 34.1 123.7Ω –67.4Ω
1800MHz 0.67 24.3 154.8Ω –75.6Ω
1900MHz 0.66 15.5 193.5Ω –70.8Ω
2000MHz 0.61 2.5 206.9Ω –10.8Ω
2100MHz 0.55 –10.2 163.1Ω 24.2Ω
2200MHz 0.46 –34.3 101.7Ω 21.3Ω
2300MHz 0.34 –63.8 65.5Ω 5.5Ω
2400MHz 0.30 –113.3 40.0Ω –2.5Ω
2500MHz 0.33 –164.3 25.8Ω –1.6Ω
2600MHz 0.42 164.8 21.4Ω 2.2Ω
2700MHz 0.51 140.5 23.1Ω 6.3Ω
2800MHz 0.53 120.3 31.4Ω 6.7Ω
2900MHz 0.52 101.7 42.2Ω 3.6Ω
3000MHz 0.33 98.1 45.9Ω 1.3Ω
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IM2 Adjustment Circuitry
The LTM9013 also contains circuitry for the independent
adjustment of IM2 levels on the I and Q channels. When
the EIP2 pin is a logic high, this circuitry is enabled and
the IP2I and IP2Q analog control voltage inputs are able
to adjust the IM2 level. The IM2 level can be effectively
minimized over a large range of the baseband bandwidth.
The circuitry has an effective baseband frequency upper
limit of about 200MHz. Any IM2 component that falls in
this frequency range can be minimized.
Variable Gain Amplifier
The LTM9013 includes a high linearity, fully-differential
analog-controlled variable-gain amplifier (VGA) opti-
mized for application frequencies in the range of 1MHz to
500MHz. The VGA architecture provides a constant OIP3
and constant output noise level (NF + Gain) over the 31dB
gain-control range and thus exhibits a uniform spurious-
free dynamic range (SFDR) over gain. This constant SFDR
characteristic is ideal for use in receiver IF chains.
Gain Characteristics
The LTM9013 provides a continuously adjustable gain of
31dB that is linear-in-dB with respect to the control volt-
ages applied to GAIN_I and GAIN_Q. In this way, a positive
gain-control slope is easily achieved:
Apply gain control voltage to the GAIN_I/GAIN_Q pins.
Gain increases with increasing GAIN_I/GAIN_Q voltage.
When connected in this typical single-ended configuration,
the active control input range extends from 0.1V to 1.1V.
This control input range can be extended using a resistor
divider with a suitably low output resistance. For example,
two series resistors of 1k each would extend the control
input range from 0.2V to 2.2V while providing an effective
500Ω Thevinin equivalent source resistance, a relatively
small loading effect compared to the 10k input resistance
of the GAIN_I/GAIN_Q terminals.
IF Input Port Characteristics
The amplifier inputs provide a nominal 50Ω differential
input impedance over the operating frequency range.
The input impedance characteristic derives from the dif-
ferential attenuator ladder. The internal circuit controls the
IF connections to this attenuator ladder and generates the
appropriate common mode DC voltage.
Enable/Shutdown
Both the EN and SHDN pins are self-biased to VCC2 through
their respective 100k pull-up resistors, so the default
open-pin state is powered on with the output amplifier
signal path disabled. Pulling the EN pin low completes the
signal path from the attenuator ladder through the output
amplifier. The EN pin essentially provides a fast muting
function while the SHDN pin provides slower power on/
off function.
For applications requiring the SHDN function, it is recom-
mended that the output amplifier signal path be disabled
with a high EN voltage before transitioning the SHDN
signal. When enabling the amplifier, allow at least 5ms
dwell time between the rising SHDN transition and the
falling EN transition to avoid non-monotonic output signal
behavior though the VGA. The opposite delay sequence
is recommended for the falling SHDN transition, but this
is less critical as the output signal amplitude will drop
abruptly regardless of the EN pin.
Figure 6
SHDN
EN
tDWELL tDWELL
9013 F06
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ESD
The amplifier inputs are protected with reverse-biased
ESD diodes on all pins. If any pin is forced one diode drop
above the positive supply or one diode drop below the
negative supply, then large currents may flow through the
diodes. No damage to the devices will occur if the current
is kept below 10mA.
Reference
The LTM9013 has an internal 1.25V voltage reference for
the ADC. For a 1.32V input range with internal reference,
connect SENSE to VDD. For a 1.32V input range with an
external reference, apply a 1.25V reference voltage to
SENSE (Figure 7). Apply a 1.15V reference voltage to
SENSE to achieve specified performance.
Figure 7. Reference Circuit
Figure 8. Equivalent Encode Input Circuit
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
the encode inputs directly. Otherwise a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD + 0.1V or go below –0.1V.
SCALER/
BUFFER
VREF
0.1µF
SENSE
1.25V
LTM9013
9013 F07
5Ω
ADC
REFERENCE
SENSE
DETECTOR
VDD
LTM9013
9013 F08
1.2V
10k
CLK+
CLK–
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Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 5) or
by CS in parallel programming mode.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this cases care should be taken to make the clock a 50%
(± 5%) duty cycle.
DIGITAL OUTPUTS
The digital outputs are double data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are seven LVDS output pairs for chan-
nel A (DA0_1+/DA0_1– through DA12_13–/DA12_13+)
and seven pairs for channel B (DB0_1+/DB0_1– through
DB12_13–/DB12_13+). Overflow (OF+/OF–) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that overflow for both channels is mul-
tiplexed onto the OF+/OF– output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 5). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Figure 9. Sinusoidal Encode Circuit
LTM9013 VDD
9013 F09
1.2V
10k
50Ω
100Ω
50Ω
0.1µF
0.1µF
T1: MACOM
ETC1-1-13
Figure 10. PECL or LVDS Encode Drive
VDD
LTM9013
PECL OR
LVDS INPUT
9013 F10
1.2V
10k
100Ω
0.1µF
0.1µF
CLK+
CLK–
LTM9013
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CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
0
0
0
1
1
1
1
CLKPHASE1
MODE CONTROL BITS
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
9013 F11
CLK+
applicaTions inForMaTion
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
The OF output is double data rate; when CLKOUT+ is low,
channel A’s overflow is available; when CLKOUT+ is high,
channel B’s overflow is available.
Phase Shifting the Output Clock
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
trol register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 11).
Figure 11. Phase Shifting CLKOUT
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DATA FORMAT
Table 3 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 3. Output Codes vs Input Level
+IN – –IN OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
+Overflow
+Full Scale
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
Mid-Scale
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–Full Scale
–Overflow
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT out-
puts are not affected. The output randomizer is enabled
by serially programming mode control register A4.
Figure 12. Functional Equivalent of Digital Output Randomizer
Figure 13. Decoding a Randomized Digital Output Signal
CLKOUT CLKOUT
OF
D13/D0
D12/D0
•
•
•
D1/D0
D0
9013 F12
OF
D13
D12
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
•
•
•
D1
D0
9013 F13
D0
D1/D0
D12/D0
D13/D0
OF
CLKOUT
LTM9013
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Alternate Bit Polarity
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13 to D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
Sleep Mode
The A/D may be placed in sleep mode to conserve power.
In sleep mode the entire A/D converter is powered down,
resulting in <5mW power consumption. If the encode
input signal is not disabled the power consumption will be
higher (up to 5mW at 250Msps). Sleep mode is enabled
by mode control register A1 (serial programming mode),
or by SCK (parallel programming mode).
In the serial programming mode it is also possible to dis-
able channel B while leaving channel A in normal operation.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitor on VREF . With
the 2.2µF value used internally, the A/D will stabilize after
0.1ms + 2500 • tp where tp is the period of the sampling
clock.
Nap Mode
In nap mode the A/D core is powered down while the inter-
nal reference circuits stay active, allowing faster wakeup.
Recovering from nap mode requires at least 100 clock
cycles. Nap mode is enabled by power-down register A1
in the serial programming mode.
Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise Power-Down Wake-up
conditions apply.
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DEVICE PROGRAMMING MODES
The operating modes of the A/D can be programmed by
either a parallel interface or a simple serial interface. The
serial interface has more flexibility and can program all
available modes. The parallel interface is more limited and
can only program some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 4 shows the modes set by CS, SCK
and SDI.
Table 4. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 5 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is neces-
sary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is write-only.
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Table 5. Serial Programming Mode Register Map (PAR/SER = GND). X Indicates Unused Bit
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Bit 7 RESET Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0 Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X SLEEP NAP PDB 0
Bits 7-4 Unused, this bit read back as 0
Bit 3 SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2 NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
Bit 1 PDB
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0 Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, This Bit Read Back as 0
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
applicaTions inForMaTion
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REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF
Bits 7-5 Unused, This Bit Read Back as 0
Bits 4-2 ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1 TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0 OUTOFF Digital Output Mode Control Bits
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
OUTTEST2 OUTTEST1 OUTTEST0 ABP 0 DTESTON RAND TWOSCOMP
Bits 7-5 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010
Note 1: Other bit combinations are not used.
Note 2: Patterns from channel A and channel B may not be synchronous.
Bit 4 ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3 Must Be Set to 0
Bit 2 DTESTON Enable the digital output test patterns (set by Bits 7-5)
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1 RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0 TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
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Design Examples
The LTM9013 allows the user to tailor the highpass corner
frequency to suit the application. The 0.5dB lowpass corner
is set by the internal network at 300MHz. By cascading
the external highpass and internal lowpass networks a
bandpass characteristic is realized. An example of a very
low frequency highpass corner is shown in Figure 14.
The typical performance for the overall module is shown
below:
IF passband (1.5dB): 1MHz to 300MHz
RF input for –1dBFS: –5dBm at maximum gain
SNR at –1dBFS: 59.1dB
HD2 at –1dBFS: 74dBc
IMD3 at –7dBFS per tone: –72dBc
The frequency response is shown in Figure 15:
Figure 14. Highpass Filter Set for 1MHz
Figure 15. Baseband Frequency Response
BASEBAND FREQUENCY (MHz)
–6
AMPLITUDE (dB)
–4
–2
0
–5
–3
–1
100 200 300 400
9013 F15
500500 150 250 350 450
VCC2
3.3V
VCC1
5V
GAIN_Q
0.01µF
0.01µF
15nH
0.01µF
0.01µF
15nH
GND
LO IN
15nH
15nH
6.8pF
100Ω
100Ω
100Ω
5V
GAIN_I
VDD
1.8V
LTM9013
ADC
ADC
GND
9013 F14
CLKOUT
SDOSDISCK CS
ADC CLK
OVDD
1.8V
OF
100Ω
5V 6.8pF
0°
90°
PAR/SER
LNA
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Figure 16. Highpass Filter Set for 55MHz
Figure 17. Baseband Frequency Response
For those applications that require a higher frequency
corner at the highpass point, the network can be tailored,
for example, as shown in Figure 16.
The typical performance for the overall module is shown
below:
IF passband (1.0dB): 55MHz to 315MHz
RF input for –1dBFS: –5dBm at maximum gain
SNR at –1dBFS: 59.1dB
HD2 at –1dBFS: 74dBc
IMD3 at –7dBFS per tone: –72dBc
The frequency response is shown in Figure 17:
BASEBAND FREQUENCY (MHz)
–3.0
AMPLITUDE (dB)
–2.0
–1.0
0
–2.5
–1.5
–0.5
100 200 300 400
9013 F17
500500 150 250 350 450
VCC2
3.3V
VCC1
5V
GAIN_Q
0.01µF
0.01µF
0.01µF
0.01µF
GND
LO IN
56pF
56pF
180nH
56pF
56pF
180nH 150nH
150nH
100Ω
100Ω
100Ω
5V
GAIN_I
VDD
1.8V
LTM9013
ADC
ADC
GND
9013 F16
CLKOUT
SDOSDISCK CS
ADC CLK
OVDD
1.8V
OF
100Ω
5V
0°
90°
PAR/SER
LNA
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Supply Sequencing
The VCC1 pins supply voltage to the demodulator. The
VCC2 pins supply voltage to the amplifiers. The amplifier
output stages are also fed by the VCC1 pins, so careful
power supply sequencing is important. Power must be
applied to the VCC2 pins before power is applied to the
VCC1 pins to avoid damage to the amplifiers. Note also that
the amplifiers must be enabled before voltage is applied
to the VCC1 pins for the same reason.
Grounding and Bypassing
The LTM9013 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9013 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. A continuous row of ground pads facilitate a
layout that ensures that digital and analog signal lines are
separated as much as possible.
The LTM9013 is internally bypassed with the ADC (VDD),
mixer, amplifier (VCC) digital (OVDD) supplies returning to
a common ground (GND). Additional bypass capacitance
is optional and may be required if power supply noise is
significant.
Heat Transfer
Most of the heat generated by the LTM9013 is transferred
through the bottom-side ground pins. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
Recommended Layout
The high integration of the LTM9013 makes the PCB
board layout simple. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for ground. This helps to
dissipate heat in the package through the board and
also helps to shield sensitive on-board analog signals.
• Use multiple ground vias. Using as many vias as pos-
sible helps to improve the thermal performance of the
board and creates necessary barriers separating analog
and digital traces on the board at high frequencies.
• Separate analog and digital traces as much as possible,
using vias to create high frequency barriers. This will
reduce digital feedback that can reduce the signal-to-
noise ratio (SNR) and dynamic range of the LTM9013.
Figures 18 through 25 give a good example of the recom-
mended layout.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
use a type 3 or 4 printing no-clean solder paste. The solder
stencil design should follow the guidelines outlined in PCB
Assembly and Manufacturing Guidelines
BGA Packages: Assembly Considerations for Linear Tech-
nology µModule BGA Packages.
applicaTions inForMaTion
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Typical applicaTions
Figure 18. Schematic for Recommended Layout
2 1
SLEEP
IP2 ADJUST ENABLE
SERIAL
CLOCK DUTY STABILIZE ON
GAIN ADJUST (Q CH)
AMP RUN
DEMOD REF
CLOCK DUTY STABILIZE OFF
IP2 ADJUST (Q CH)
CLK_IN
IP2 ADJUST DISABLE
I/Q ENABLE
LO_IN
IP2 ADJUST (I CH)
RUN
Matched for 1.95GHz
GAIN ADJUST (I CH)
Matched for 1.8GHz
AMP_MUTE (HI)
RF_IN
PARALLEL
AMP SHUTDOWN
1.75 mA
I/Q DISABLE
3.5 mA
VCC1_load
DA23+
DB1213-
VDD
DB89-
DB45-
DB01-
DA01-
DB1011-
DB1213+
DA01+
~CS
DB89+
DB1011+
DA45-
CLKOUT-
DA1011-
DB23-
DB67-
SDO
DB45+
VCC2
DA45+
DB01+
DA1011+
VCC1
CLKOUT+
DA23-
DA1213-
SDI
DA89+
DA67-
DA67+
OF+
SCK
DB23+
~AMP_SHDN
DB67+
DA89-
DA1213+
OF-
VDD VDD
VCC2
VCC2
VDD
VCC1
VCC1
VCC2
VCC1_load
VCC1
VDD
VCC2
VCC2
VCC1_load
VDD
VDD
VCC1
VDD
VCC1
C5
0.01uF
C6
0.01uF
JP2
1
2
3
R20
0
C17
2.2uF
R30
1.74K
R6
3.83K
R35
0
J1
R26
49.9
C7
0.01uF
C27
DNI
R14
100
C15
0.1uF
C26
0.01uF
R34
1K
C12
0.1uF
R33
178
R21
1K
R9
10K
J3
E5
JP3
1
2
3
C4
6.8pF
R5
100
JP1
1
2
3
R39
0
R18
0.1
R2
1K
JP5
1
2
3
E4
R23
1.74K
C20
1.5pF
C11
0.01uF
R12
3.83K
R36
DNI
J2
C8
DNI
R19
0.1
JP4
1
2
3
E6
JP7
1
2
3
R22
100
C10
6.8pF
C18
2.2uF
R28
178
R1
1K
C3
DNI
R17
0.1
U2
LTM9013
E2
C2
C1
A2
E6
C4
B4
B3
J3
K1
L1
M1
N1
K3
A3
B6
L6
M6
N7
C8
A8
M8
P1
K2
L2
M2
N2
P2
A12
H5
C3
D3
L5
D7
A7
G6
G8
K7
J7
M3
N3
P3
E8
H8
K8
C7
E4
E10
F6
J1
H1
G1
F1
M4
N4
P4
A5
E1
B1
A1
E5
E11
M9
P9
J5
K5
L9
N8
N10
P5
A6
F8
C6
D6
N9
B10
H11
E12 J6
B12
G12
F12
L12
K12
H13
B7
J13
K13
P14
K14
J14
H14
G14
E14
F14
B14
P7
B2
D2
D8
F2
G2
H2
J2
J8
E3
F3
G3
H3
P8
L3
A4
C9
D9
D4
G4
H4
J4
K4
L4
B5
C5
D5
G5
A10
M5
C10
D10
F10
F4
H6
K6
J10
K10
N6
P6
N5
P10
E7
F7
G7
H7
F11
F5
L7
M7
J11
K11
L11
M11
N11
P11
D1
L8
C12
A13
A9
B9
E9
F9
G9
H9
K9
M12
N12
P12
G10
H10
L10
M10
A11
B11
C11
D11
G11
L13
M13
N13
P13
H12
J12
C14
D14
B13
C13
D13
E13
F13
G13
L14
M14
N14
A14
B8
J9
D12
GND
GND
GAIN_Q
VCC2
GND
GND
GND
GND
GND
OF-
DB01-
DB23-
DB67-
GND
VCC2
GND
GND
GND
GND
GND
GND
GND
GND
OF+
DB01+
DB23+
DB67+
DB1213+
VCC2
GND
EN#_Q
SHDN#_Q
GND
GND
GND
GND
GND
GND
GND
DB45-
DB89-
DB1213-
GND
GND
GND
GND
+IN_Q
+IN_I
GND
GND
GND
GND
GND
DB45+
DB89+
DB1011+
LO-
GND
GND
GND
-IN_Q
-IN_I
GND
GND
CLK+
CLK-
GND
GND
OVDD
DB1011-
LO+
GND
NC
EIP2
GND
GND
GND
GND VDD
GND
GND
GND
GND
GND
GND
VCC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLKOUT-
GND
GND
REF
GND
GND
GND
GND
SENSE
GND
GND
GND
GND
CLKOUT+
GND
GND
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RF
GND
IP2_I
IP2_Q
+OUT_I
+OUT_Q
GND
GND
PAR_SER#
CS#
GND
GND
OVDD
DA23+
GND
GND
GND
GND
-OUT_I
-OUT_Q
GND
GND
SCK
SDI
SDO
DA89-
DA45-
DA23-
VCC2
GND
GAIN_I
VCC2
GND
GND
GND
GND
GND
GND
GND
DA89+
DA45+
DA01+
GND
GND
GND
GND
GND
GND
GND
GND
GND
DA1213-
DA1011-
DA67-
DA01-
GND
GND
EN#_I
SHDN#_I
GND
GND
GND
GND
GND
GND
DA1213+
DA1011+
DA67+
GND
EN
VDD
VCC2
T2
MABA007159
5
3
1
4
C22
6.8nH
R11
0
E3
R24
1K
C9
DNI
L5
3.3nH
R7
1.00K
R10
1K
R3
1K
C23
0.01uF
C14
0.1uF
R8
100
R15
1.00K
L1
15nH
C2
DNI
C24
0.5pF
R31
1.00K
C19
100pF
L4
15nH
L3
15nH
R37
49.9
U1
Si1563DH
6
2
1
3 4
5
R16
0.1
C1
0.01uF
R13
1K
R29
1.58K
C16
0.01uF
R32
1K
E1
R38
DNI
E2
C13
0.1uF
C25
0.01uF
T1
BD0826J50200A00
1
2
3
4
5
6
R4
1K
JP6
1
2
3
C21
DNI
L2
15nH
R27
1K
R25
1.00K
LTM9013
32
9013fa
For more information www.linear.com/LTM9013
Typical applicaTions
Figure 19. Additional Schematic Elements for Recommended Layout
+5V
GND
EEPROM WRITE
EN
+5V IN
DIS
+3.3V
+1.8V
+5V_IN
DB67+
SDI
VCC1
DA45-
DA89-
DA01+
DB1011-
SCK
SDA
DB45-
SDO
DA45+
DA1011+
DA67+
DB1011+
CLKOUT-
SDA
OF-
DB01-
VDD
DA23-
DB1213-
DA23+
DB89+
DB23+
CLKOUT+
DA01-
DA1213+
VCC2
DA1213-
DB67-
SCL
~CS
DB89-
DA67-
DB45+
DB1213+
DB01+
DB23-
DA89+
OF+
SCL
DA1011-
~AMP_SHDN
VDD
VCC2
VCC1
U4 LT3080EDD
7
5
3
8 2
1
9
4
VIN
VCTRL
VOUT
VIN VOUT
VOUT
PAD
SET
C36
0.1uF
R44
10K
C38
0.1uF
+
C29
47uF
U8
FMC_MOUNTING_HOLE
GND
C31
4.7uF
R42
3K
+
C32
47uF
JP8
1
2
3
R47
1K
U9
FMC_MOUNTING_HOLE
GND
U10
FMC_MOUNTING_HOLE
GND
R45
10K
J4H
SEAM-10X40PIN
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
U7
Si1563DH
6
2
1
3 4
5
C33
0.1uF
J4D
SEAM-10X40PIN
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
U5
24LC32A-I /ST
1
2
3
4
5
6
7
8
A0
A1
A2
VSS
SDA
SCL
WP
VCC
U6
FMC_MOUNTING_HOLE
GND
R40
3K
J4G
SEAM-10X40PIN
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
R46
10K
C37
0.1uF
J4C
SEAM-10X40PIN
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
C30
4.7uF
R43
182K
E7
R50
10K
R49
10K
+
C35
47uF
U3 LT3080EDD
7
5
3
8 2
1
9
4
VIN
VCTRL
VOUT
VIN VOUT
VOUT
PAD
SET
R41
330K
R48
10K
C34
0.1uF
E8
LTM9013
36
9013fa
For more information www.linear.com/LTM9013
pacKage DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
BGA Package
196-Lead (15mm × 15mm × 2.82mm)
(Reference LTC DWG# 05-08-1907 Rev A)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
DETAIL A
Øb (196 PLACES)
DETAIL B
SUBSTRATE
A
A1
b1
ccc Z
DETAIL B
PACKAGE SIDE VIEW
MOLD
CAP
Z
MX YZddd
MZeee
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
2.62
0.40
2.22
0.55
0.55
0.22
1.95
NOM
2.82
0.50
2.32
0.60
0.60
15.0
15.0
1.0
13.0
13.0
0.32
2.00
MAX
3.02
0.60
2.42
0.65
0.65
0.42
2.05
0.15
0.10
0.15
0.15
0.08
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 196
A2
D
E
SUGGESTED PCB LAYOUT
TOP VIEW
0.00
4.50
2.50
6.50
5.50
3.50
6.50
4.50
5.50
1.50
0.50
2.50
0.50
3.50
1.50
5.50
2.50
1.50
3.50
4.50
2.50
1.50
0.50
0.50
6.50
5.50
6.50
4.50
3.50
0.00
6.20
6.80
// bbb Z
Z
H2
H1
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
0.60 ±0.025 Ø 196x
P
N
M
L
K
J
H
G
F
E
D
C
B
A
12345614 13 12 11 10 9 8 7
DETAIL A
3
SEE NOTES PIN 1
e
e
F
G
b
6.80
6.20
BGA 196 1112 REV A
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
LTMXXXXXX
µModule
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
7
SEE NOTES
LTM9013
37
9013fa
For more information www.linear.com/LTM9013
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 4/14 Changed product description to wideband receiver
Changed latency to six cycles
Updated demo board schematic to reflect pin out convention shown on page 11
1
16
31, 32
LTM9013
38
9013fa
For more information www.linear.com/LTM9013
LINEAR TECHNOLOGY CORPORATION 2013
LT 0414 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM9013
relaTeD parTs
Typical applicaTion
RMS
DETECTION
1MHz BPF
DSP
DAC
ADC
IP2I
LTM9013
fLO = 1990MHz
f1 = 20MHz
f2 = 21MHz
9013 TA02
LNA
LOOPBACK
LTC5588-1
1-D
MINIMIZATION
ALGORITHM
DAC
PA
+
Block Diagram for IM2 Adjustment. Only the I-Channel Is Shown
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package
LTC2157-14/LTC2156-14/
LTC2155-14 14-Bit, 250Msps/210Msps/170Msps,
1.8V Dual ADC, DDR LVDS Outputs 605mW/565mW/511mW, 70dB SNR, 90dB SFDR, 9mm × 9mm
64-Lead QFN Package
LTC2152-14/LTC2151-14/
LTC2150-14 14-Bit, 250Msps/210Msps/170Msps,
1.8V Single ADC, DDR LVDS Outputs 338mW/316mW/290mW, 70dB SNR, 90dB SFDR, 6mm × 6mm
40-Lead QFN Package
LTC2158-14 14-Bit, 310Msps 1.8V Dual ADC, DDR LVDS Outputs,
Low Power 724mW, 68.8dB SNR, 88dB SFDR, 9mm × 9mm 64-Lead
QFN Package
RF Mixers/Demodulators
LT5517 40MHz to 900MHz Direct Conversion Quadrature
Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
LT5575 800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
,
Integrated RF and LO Transformer
Amplifiers/Filters
LTC6409 10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA
Supply Current, 3mm × 2mm QFN Package
LTC6412 800MHz, 31dB Range, Analog-Controlled Variable
Gain Amplifier Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz,
10dB Noise Figure, 4mm × 4mm QFN-24 Package
LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC
Drivers for 300MHz IF Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply
Current per Amplifier, 3mm × 4mm QFN-20 Package
Receiver Subsystems
LTM9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain
Differential Amplifiers
LTM9003 12-Bit Digital Pre-Distortion Receiver Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to
3.8GHz Input Frequency Range
