88PG8237A1-NFE1C000 - MARVELL TECHNOLOGY GROUP

Marvell. Moving Forward Faster

Doc. No. MV-S103563-00, Rev. C

April 23, 2008

Document Classification: Proprietary Information

Cover

88PG8237, 88PG8227, 88PG8226,

88PG8216, 88PG8204

Field Programmable DSP Switcher™

Family

1MHz, Dual Step-down Regulator with

AnyVoltage™ Technology

Datasheet

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to h ardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Document Status

Doc Status: 2.00 Technical Publication: 0.xx

For more information, visit our website at: www.marvell.com

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88PG82XX

Datasheet

Page 2 Document Classification: Proprietary Information April 23, 2008, 2.00

88PG82XX

Field Programmable DSP Switcher™ Family

Datasheet

April 23, 2008, 2.00 Document Classification: Proprietary Information Pa ge 3

PRODUCT OVERVIEW

The 88PG82XX family integr ates the dual synchronous

Step-Down (Buck) switching regulators housed in a 3 X

4mm QFN-20 package. Internally self-compensated, the

step-down regulator requires no external compensation

and works with low-ESR output capacitors to simplify the

design, minimize the board space, and reduce the

amount of external components. The switching

frequency for the step-down regulator is 1MHz, allowing

the use of low profile surface mount in ductors and low

value capacitors. Each step-down regulator includes

programmable output voltage to allow the user to easily

set the output voltage with external resistors, logic

control, or serial data interface. The output voltage range

is 0.72V to 3.63V.

The 88PG82XX family operates from an input voltage

range of 2.75V to 5.5V, making the device well suited for

portable applications.

Other key features of the 88PG82XX family include soft

start, an internal current limit, an under-voltage lockout,

thermal shutdown, over voltage protection, and

power-on-reset signals.

Features

Tiny 3 X 4 mm QFN-20 package

Dual switching regulators

1MHz switching frequency

Low quiescent current of 2.1 mA (typ.)

Stable with low-ESR ceramic output capacitors

No external compensation required

Up to 95% efficiency

Input voltage range: 2.75V to 5.5V

Programmable output voltage range: 0.72V to 3.63V

Serial / Logic Programmability

Any V oltage TM Technology provides 64 output voltage

selections to provide up most flexibility

Built-in undervoltage lockout

Over voltage protection

Thermal shutdown protection

Output short circuit protection

Output voltage margining capability

Lead-free packages

Applications

Portable and handheld computing

Point-of-load power supplies

DSP power supplies

Disk drive power supplies

Figure 1: Typical Application Circuit: Output 1.8V/1.5A and 1.2V/1.5A

51k

160k

100k

10 ohm

POR 2

22uF/6.3V

0.1uF

POR 1

88PG8226

22uF/6.3V

Vin

2.75V - 5.5V

2.5V/1.5A

PGND1 8

SW2 20

SFB2 2

SW2 18

SVIN

SW1 9

PVIN1

PGND2 19

SW1 7

SFB1 5

VSET2

PSET2

POR1

POR2

PVIN2

VSET1

PSET1

SDI

SGND

100k

3.3uH

Vout1

22uF/6.3V

1.5V/1.5A

Vout2

3.3uH C4

22uF/6.3V

100k

SDI

88PG82XX

Datasheet

Page 4 Document Classification: Proprietary Information April 23, 2008, 2.00

Caution: This is a very high frequency device, proper PCB layout is required. Refer to page 47 for further details.

Table 1: DC Loading Current Ratings

Buck 2

Buck 1 0.75A 1.0A 1.5A 2.0A

0.75A 88PG8204188PG8205 88PG8206 88PG8207

1.0A 88PG8214 88PG8215 88PG8216188PG8217

1.5A 88PG8224 88PG8225 88PG8226188PG82271

2.0A 88PG8234 88PG8235 88PG8236 88PG82371

1. The part numbers in Bold are released to production. The other parts are available upon request. Contact Marvell®

marketing for availability.

The devices shown in Table 1 have the same input and output voltage range for step-down registers.

Table of Contents

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Table of Contents

Product Overview.......................................................................................................................................3

Table of Contents .......................................................................................................................................5

List of Tables ..............................................................................................................................................7

List of Figures.............................................................................................................................................9

1 Signal Description.......................................................................................................................11

1.1 Pin Configuration.............................................................................................................................................11

1.2 Pin Description................................................................................................................................................12

1.2.1 Pin Types..........................................................................................................................................12

2 Electrical Specifications .............................................................................................................15

2.1 Absolute Maximum Ratings ............................................................................................................................15

2.2 Recommended Operating Conditions.............................................................................................................15

2.3 Electrical Characteristics.................................................................................................................................16

2.4 Switching Step-down Regulator........ ... ...................... ....................... ...................... ... .....................................17

3 Functional Description................................................................................................................19

3.1 Regulation and Start-up.......................... ...................... ....................... ...................... .....................................19

3.1.1 Soft Start and Sequencing................................................................................................................20

3.2 Output Voltage Settings.................... ..............................................................................................................22

3.2.1 Logic Programmability......................................................................................................................22

3.2.2 Serial Programmability.................................... .......................................... ........................................23

3.2.3 Output Voltage – AnyVoltage™ Technology ....................................................................................25

3.3 Undervoltage Lockout (UVLO)............................................... .......................................... ...............................28

3.4 Over Voltage Protection (OVP).......................................................................................................................28

3.5 Power-On Reset (POR) ..................................................................................................................................28

3.6 Thermal Shutdown..........................................................................................................................................29

3.7 Adaptive Transient Response................................................................ .........................................................29

4 Functional Characteristics .........................................................................................................31

4.1 Start-Up Waveforms............... ... ........................................................................................ ..............................31

4.2 Short-Circuit Waveforms.................................................................................................................................32

4.3 Switching Waveforms..................... ....................... .......................................... ................................................33

4.4 Load Transient Waveforms.............................................................................................................................34

4.4.1 Step-Down Regulator .......................................................................................................................34

4.4.2 Cross-Talk Waveforms ....... ... ... ........................................................................................................36

4.5 Output Voltage Transient Waveforms.............................................................................................................37

4.5.1 Step-Down Regulator .......................................................................................................................37

88PG82XX

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4.6 Line Transient Waveforms ..............................................................................................................................38

5 Typical Characteristics ...............................................................................................................39

5.1 Efficiency Graphs............................................................................................................................................39

5.1.1 Efficiency Graphs in Log Scale...... ... ... ...................... ... ....................... ...................... .......... .............39

5.2 Load Regulation..............................................................................................................................................40

5.3 Dropout Voltage......................................... .. ... .................... ... .........................................................................40

5.4 RDS (ON) Resistance.....................................................................................................................................40

5.5 IC Case and Inductor Temperature.................................................................................................................41

5.6 Input Voltage Graphs......................................................................................................................................43

5.6.1 Step-Down Regulator .......................................................................................................................44

5.7 Temperature Graphs.......................................................................................................................................45

5.7.1 Step-Down regulator...................... .......................................... .........................................................46

6 Applications Information ........ ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ......................47

6.1 PC Board Layout Considerati ons and Guidelines...........................................................................................47

6.1.1 PC Board Layout Examples for 88PG82XX .....................................................................................50

6.1.2 Bill of Materials (BOM)......................................................................................................................52

7 Mechanical Drawing....................................................................................................................55

7.1 88PG82XX Mechanical Drawing.....................................................................................................................55

7.2 Dimensions .....................................................................................................................................................56

7.3 Typical Pad Layout Dimensions......................................................................................................................57

7.3.1 Recommeded Solder Pad Layout.....................................................................................................57

8 Ordering Information............... ... .... ... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ... .............59

8.1 Ordering Part Numbers and Package Markings..............................................................................................59

8.2 Sample Ordering Part Number........................................................................................................................59

8.3 Package Marking ........ ................................................................................. ...................................................60

8.3.1 88PG82XX Package Marking and Pin 1 Locations ..........................................................................60

List of Tables

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List of Tables

Table 1: DC Loading Current Ratings...............................................................................................................4

1 Signal Description ............................................................................................................................11

Table 2: Pin Type Definitions..........................................................................................................................12

Table 3: Pin Descriptions................................................................................................................................12

2 Electrical Specifications ..................................................................................................................15

Table 4: Absolute Maximum Ratings..............................................................................................................15

Table 5: Recommended Operating Conditions...............................................................................................15

Table 6: Electrical Characteristics Table ........................................................................................................16

Table 7: Switching Step-down Regulator Table..............................................................................................17

3 Functional Description.....................................................................................................................19

Table 8: Logic Programmability Table............................................................................................................22

Table 9: Default Value of Data Field...............................................................................................................24

Table 10: Voltage and Percentage Set.............................................................................................................24

Table 11: Output Voltage Selection..................................................................................................................24

Table 12: AnyVoltage™ Programming Table for 1% Resistors........................................................................25

Table 13: AnyVoltage™ Programming Table for 5% Resistors........................................................................26

Table 14: Output Voltage Option Steps............................................................................................................27

4 Functional Characteristics...............................................................................................................31

5 Typical Characteristics ....................................................................................................................39

6 Applications Information .................... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .............47

Table 15: BOM for 88PG82XX .........................................................................................................................52

Table 16: Ceramic Capacitor Cross Reference................................................................................................54

7 Mechanical Drawing .........................................................................................................................55

Table 17: Package Dimensions........................................................................................................................56

8 Ordering Information.......... .... ... ... ... ................ .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ................59

Table 18: 88PG82XX Ordering Part Numbers..................................................................................................59

A Revision History ...............................................................................................................................61

Table 19: Revision History................................................................................................................................61

88PG82XX

Datasheet

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THIS PAGE INTENTIONALLY LEFT BLANK

List of Figures

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List of Figures

Figure 1: Typical Application Circuit: Output 1.8V/1.5A and 1.2V/1.5A ........ .....................................................3

1 Signal Description ........................................................................................................................... 11

Figure 2: 88PG82XX Family 3X4mm QFN-20 Package—Top View................................................................11

2 Electrical Specifications ................................................................................................................. 15

3 Functional Description.................................................................................................................... 19

Figure 3: 88PG82XX Block Diagram ...............................................................................................................19

Figure 4: Output Voltage Window....................................................................................................................20

Figure 5: Startup without Seque ncing..............................................................................................................20

Figure 6: Startup with Sequencing and Soft Start (COUT= 22 μF) ...................................................................20

Figure 7: Fast Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) .................................................................................21

Figure 8: Soft Start up (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) .....................................................................................21

Figure 9: Inrush Current with COUT = 100 μF ..................................................................................................21

Figure 10: Serial Programmability ......................................................................................................................23

Figure 11: Startu p Sequence ............................................................................................................................27

Figure 12: VSET = 2.5V and PSET = -5%.........................................................................................................27

Figure 13: UVLO and OVP Waveforms .............................................................................................................28

Figure 14: Power-On Reset Waveforms............................................................................................................28

Figure 15: Adaptive Transient Response ................... .. ....................... ...................... ... .....................................29

4 Functional Characteristics.............................................................................................................. 31

Figure 16: Startup Using the Enable Pin ...........................................................................................................31

Figure 17: Turn Off Using the Enable Pin............. ... ...................... ....................... ...................... ... ....................31

Figure 18: Startu p Sequence ............................................................................................................................31

Figure 19: Hot Plug............................................................................................................................................31

Figure 20: UVLO and OVP Thresholds..............................................................................................................32

Figure 21: Input Soft Start and Start up Sequence............................................................................................32

Figure 22: Step-Down Short-Circuit Response .................................................................................................32

Figure 23: Switching Waveforms - PWM mode ................................................................................................33

Figure 24: Switching Waveforms - PWM mode.................................................................................................33

Figure 25: Switching Waveforms - DCM Mode .................................................................................................33

Figure 26: Switching Waveforms - DCM Mode-Zoom........................................................................................33

Figure 27: PWM Output Ripple Voltage ............................................................................................................34

Figure 28: Fast Load Rise Time ........................................................................................................................34

Figure 29: Slow Load Rise Time........................................................................................................................34

Figure 30: Fast Load Fall Time .........................................................................................................................35

Figure 31: Slow Load Fall Time.........................................................................................................................35

Figure 32: Load Transient Response ................................................................................................................35

Figure 33: Double-Pulsed Load Response........................................................................................................35

88PG82XX

Datasheet

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Figure 34: Load Transient Response ................................................................................................................36

Figure 35: Double-Pulsed Load Response........................................................................................................36

Figure 36: Cross-talk Continuous Mode ...........................................................................................................36

Figure 37: Cross-talk Discontin uous M ode........................................................................................................36

Figure 38: VOUT = 1.0V to 1.2V with No Load ...................................................................................................37

Figure 39: VOUT = 1.0V to 1.5V with No Load....................................................................................................37

Figure 40: VOUT = 1.0V to 1.2V with ILOAD = 1.5A.............................................................................................37

Figure 41: VOUT = 1.0V to 1.5V with ILOAD = 1.5A.............................................................................................37

Figure 42: VOUT = 1.2V to 1.0V with ILOAD = 1.5A.............................................................................................38

Figure 43: VOUT = 1.5V to 1.0V with ILOAD = 1.5A.............................................................................................38

Figure 44: Line Transient @ VIN = 3.6V.............................................................................................................38

Figure 45: Line Transient @ VIN = 4.5V.............................................................................................................38

5 Typical Characteristics ................................................................................................................... 39

6 Applications Information .................... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ............ 47

Figure 46: Simpified Schematic .........................................................................................................................48

Figure 47: PC Board Schematic ........................................................................................................................49

Figure 48: Top Silk-Screen, Top Traces, Vias, and Top Copper (Not to Scales) ................. ... ... .......................50

Figure 49: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to Scale)...................................51

7 Mechanical Drawing ........................................................................................................................ 55

8 Ordering Information.......... .... ... ... ... ................ .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ............... 59

Figure 50: Sample Part Number........................................................................................................................59

Figure 51: 88PG8227 Package Marking and Pin 1 Location.............................................................................60

A Revision History ...............................................................................................................................61

Signal Description

Pin Configuration

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1Signal Description

1.1 Pin Configuration

Figure 2: 88PG82XX Family 3X4mm QFN-20 Package—Top View

SFB2

SVIN

SFB1

SDI/ENSEQ

SGND

15 PSET2

14 VSET2

16 POR2

12 PSET1

11 POR1

13 VSET1

89710

PGND1 SW1SW1 PVIN1

19 1820 17

PGND2 SW2SW2 PVIN2

88PG82XX

Datasheet

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1.2 Pin Description

1.2.1 Pin Types

Table 3 provides pin descriptions for the 88PG82XX.

Table 2: Pin Type Definitions

Pin Type Definition

I Input Only

O Output Only

S Supply

NC Not Connected

GND Ground

Table 3: Pin Descriptions

Pin # Pin Name Pin Type Pin Description

1 EN I Enable.

Logic high (> 2.0V) enables both switching regulators. Logic low (<0.8V)

disables the regulators. When disabled, the switch nodes SW1 and SW2 are

Hi-Z. The feedback nodes SFB1 and SFB2 are pulled down by 20K resistors,

and the power on reset nodes POR1 and POR2 are pulled down by internal

open drain NFETs. The low signal has to be at least 20 µs to disable both

regulators . If this pin is left floating, an internal 10 µA current source pulls this

pin high to SVIN, enabling the regulator.

2 SFB2 I Switching Regulator Feedback.

Senses the output voltage of the switching regulator 2.

3 SVIN S Signal Input Voltage.

The input voltage is 2.75V to 5.5V for internal circuitry. Connect a 0.1 µF

decoupling capacitor between SVIN and SGND and position it as close as

possible to the IC.

4 SGND GND Ground.

Connect to a ground plane.

5 SFB1 I Switching Regulator Feedback.

Senses the output voltage of the switching regulator 1.

Signal Description

Pin Description

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6 SDI/ENSEQ I Multi-purpose logic input.

Logic high (> 2.0V) enables soft start and sequence. Buck 1 starts f ollowed by

Buck 2, once VOUT1 is within a specified tolerance. The soft start rise time is

typically 5 ms and is depend ent on ou tput, but indep ende nt of c ap aci tance and

load current. If a short circuit is detected on Buck1, then Buck 2 will be

disabled.

Logic low (< 0.8V) disables the start up sequence. Buck 1 and Buck 2 will start

up together without any soft start.

Serial Data Input.

The input data into this pin is used to program the output voltage (See “Output

Voltage Settings” on page 22). The power-good signal has to be high before

the serial data interface can be used. To implement soft start a 10K pull-up

resistor must be connected to SVIN.

This pin is internally pulled down by a 10 μA current source.

7, 9 SW1 O Switch Node for regulator 1.

Internal power MOSFET drain. Connects to an external inductor.

8 PGND1 GND Power Ground.

The power ground must be connected to the nega tive te rmi nal of the inp ut and

output capacitors.

10 PVIN1 S Power Input Voltage.

Internal power MOSFET source. Connect the 10µF decoupling capacitor

between PVIN and PGND and position it as close as possible to the IC.

NOTE: PVIN and PVIN2 must be connected together and should not be

separated.

11 POR1 O Power-On Reset 1.

This pin is an open drain output t o indicate t he stat us of the output volt age. The

output pin goes high 40 ms after the output voltage is within the specified

tolerance.

POR2 and POR1 can be connected to the same external pull-up resistor to

indicate “both outputs good”.

12 PSET1 I Percent Set for Regulator 1.

1. Resistor Programming: Co nnect an external resistor to ground to set the

output voltage of the switching regulator. See the “Electrical

Characteristics” for resistor values and Output Voltage Settings. Use

resistor values with a tolerance of 5% or better. The total capacitance

across this pin and GND should be equal to 25 pF or less. If the pin is not

used, it must be connected to GND.

2. Logic Programming: Four outp ut vol t age leve ls (1.8 V, 2.5V, 3.0V, 3.3V) can

be set by connecting the VSET and PSET pins to either GND or SVIN.

13 VSET1 I Voltage Set for Regulator 1.

1. Resistor Programming: Co nnect an external resistor to ground to set the

output voltage of the switching regulator. See the “Electrical

Characteristics” for resistor values and Output Voltage Settings. Use

resistor values with a tolerance of 5% or better. The total capacitance

across this pin and GND should be equal to 25 pF or less.

2. Logic Programming: Four outp ut vol t age leve ls (1.8 V, 2.5V, 3.0V, 3.3V) can

be set by connecting the VSET and PSET pins to either GND or SVIN.

Table 3: Pin Descriptions

Pin # Pin Name Pin Type Pin Description

88PG82XX

Datasheet

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14 VSET2 I Voltage Set for Regulator 2.

1. Resistor Programming: Co nnect an external resistor to ground to set the

output voltage of the switching regulator. See the “Electrical

Characteristics” for resistor values and Output Voltage Settings. Use

resistor values with a tolerance of 5% or better. The total capacitance

across this pin and GND should be equal to 25 pF or less.

2. Logic Programming: Four output voltag e levels (0. 8V, 1.0V, 1.2V, and 1.5V)

can be set by connecting the VSET and PSET pins to either GND or SVIN.

15 PSET2 I Percent Set for Regulator 2.

1. Resistor Programming: Co nnect an external resistor to ground to set the

output voltage of the switching regulator. See the “Electrical

Characteristics” for resistor values and Output Voltage Settings. Use

resistor values with a tolerance of 5% or better. The total capacitance

across this pin and GND should be equal to 25 pF or less. If the pin is not

used, it must be connected to GND.

2. Logic Programming: Four output voltag e levels (0. 8V, 1.0V, 1.2V, and 1.5V)

can be set by connecting the VSET and PSET pins to either GND or SVIN.

16 POR2 O Power-On Reset 2.

This pin is an open drain output t o indicate t he stat us of the output volt age. The

output pin goes high 40 ms after the output voltage is within the specified

tolerance.

POR2 and POR1 can be connected to the same external pull up resistor to

indicate “both output good”.

17 PVIN2 S Power Input Voltage for regulator 2: Interna l power MOSFET source. Connect

the 10 µF decoupling capacitor between PVIN2 and PGND2 and position it as

close as possible to the IC.

NOTE: PVIN and PVIN2 must be connected together and should not be

separated.

19 PGND2 GND Power Ground for regulator 2: The power ground must be connected to the

negative terminal of the input and output capacitors.

18, 20 SW2 O Switch Node for regulator 2: Internal power MOSFET drain. Connects to an

external inductor.

Table 3: Pin Descriptions

Pin # Pin Name Pin Type Pin Description

Electri ca l Specific at io ns

Absolute Maximum Ratings

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2Electrical Specifications

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

Table 4: Absolute Maximum Ratings1

1. Exceeding the absolute maximum rating may damage the device

Parameter Symbol Range Units

Signal Input Voltage SVIN -0.3 to 6.0 V

Power Input Voltage PVIN1, PVIN2 -0.3 to 6.0 V

Switch Voltage2

2. -10V to (VIN +0.3)V for less than 50μs

VSW1, VSW2 -0.6 to (SVIN +0.3) V

Switching Regulator Feedback Voltage VSFB1, VSFB2 -0.6 to (SVIN +0.3) V

Voltage Set VVSET1, VVSET2 -0.6 to (SVIN +0.3) V

Percentage Set Voltage VPSET1, VPSET2 -0.6 to (SVIN +0.3) V

Enable VEN -0.6 to (SVIN +0.3) V

POR Voltage VPOR -0.6 to (SVIN +0.3) V

SDI Voltage VSDI -0.6 to (SVIN +0.3) V

Operating Temperature Range3

3. Specifications over the -40°C to 85°C operating temperature ranges are assured by design, characterization and

correction with statistical process controls

TOP -40 to 85 °C

Maximum Junction Temperature TJMAX 125 °C

Storage Temperature Range TSTOR -65 to 150 °C

ESD Rating4

4. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF

2kV

Table 5: Recommended Operating Conditions1

1. This device is not gauranteed to function outside the specified operating range

Parameter Symbol range Units

Single Input Voltage SVIN 2.75 to 5.5 V

Power Input Voltage PVIN1, PVIN2 2.75 to 5.5 V

Package Thermal Resistance2

2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board

θJA 70 °C/W

θJC 19 °C/W

88PG82XX

Datasheet

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2.3 Electrical Characteristics

The following applies unless otherwise noted: SVIN = PVIN1= PVIN2, VVSET1 = VPSET = 0, VOUT1 =

1.8V, VVSET2 = SVIN, VPSET2 = 0, VOUT2 = 1.2V, VEN = SVIN, L (BUCK1) = 2.2 µH, COUT (BUCK1) =

22µF (Ceramic), L (BUCK2) = 2.2 µH, COUT (BUCK2) = 22 µF (Ceramic), TA = 25 °C. Bold values

indicate -40 °C < TA < 85 °C.

Table 6: Electrical Characteristics Table

Parameter Symbol Conditions Min Typ Max Units

Signal Input Voltage Range SVIN SVIN = PVIN 2.75 5.5 V

Power Input Voltage Range PVIN 2.75 5.5 V

Total Quiescent Current No load 2.1 mA

Shutdown Supply Current ISVIN VEN = 0V 1 50 μA

Undervol tage Lo c k out VUVLO High threshold, SVIN

increasing 2.65 2.70 V

Low threshold, SVIN

decreasing 2.44 2.55 V

Over-voltage Protection VOVP High threshold, SVIN

increasing 5.7

Low threshold, SVIN

decreasing 5.6

EN Threshold Voltage VEN Enable regulators 1.70 V

Disable regulators 0.7

EN Pin Input Current IEN VEN = 5.0V 1

μA

VEN = 0V 10 20

Over-temperature Thermal

Shutdown TOTS TJ increasing

(Disable regulat ors) 150 °C

TJ decreasing (Enable

regulators) 105

Electri ca l Specific at io ns

Switching Step-down Regulator

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2.4 Switching Step-down Regulator

The following applies unless otherwise noted: SVIN = PVIN1 = PVIN2, VVSET1 = VPSET = 0, VOUT1 = 1.8V, VVSET2 =

SVIN, VPSET2 = 0, VOUT2 = 1.2V, VEN = SVIN, L (BUCK1) = 2.2 µH, COUT (BUCK1) = 22 µF (Ceramic), L (BUCK2) = 2.2

µH, COUT (BUCK2) = 22 µF (Ceramic), TA = 25 °C. Bold values indicate -40 °C < TA < 85 °C.

Table 7: Switching Step-down Regulator Table

Parameter Symbol Conditions Min Typ Max Units

Minimum Peak Switch

Current Limit ILIM 88PG8204 = VOUT1 1.12

88PG8204 = VOUT2 1.12

88PG8216 = VOUT1 1.5

88PG8216 = VOUT2 2.25

88PG8226 = VOUT1 2.25

88PG8226 = VOUT2 2.25

88PG8227 = VOUT1 2.25

88PG8227 = VOUT2 3.0

88PG8237 = VOUT1 3.0

88PG8237 = VOUT2 3.0

Maximum Output

Current IOUT 88PG8204 = VOUT1, L1 = 4.7 μH0.75

88PG8204 = VOUT2, L2 = 4.7 μH0.75

88PG8216 = VOUT1, L1 = 4.7 μH1.0

88PG8216 = VOUT2, L2 = 3.3 μH1.5

88PG8226 = VOUT1, L1 = 3.3 μH1.5

88PG8226 = VOUT2, L2 = 3.3 μH1.5

88PG8227 = VOUT1, L3 = 3.3 μH1.5

88PG8227 = VOUT2, L4 = 2.0 μH2.0

88PG8237 = VOUT1, L1 = 2.0 μH2.0

88PG8237 = VOUT2, L2 = 2.0 μH2.0

Output Voltage VOUT RVSET = 11K 0.8

RVSET = 18K 1.0

RVSET = 30K 1.2

RVSET = 51K 1.5

RVSET = 100K 1.8

RVSET = 160K 2.5

RVSET = 270K 3.0

RVSET = 470K 3.3

Output V oltage 1, Logic

Programmability VOUT1 VVSET1 = 0V, VPSET1 = 0V 1.8

VVSET1 = 0V, VPSET1 = SVIN 2.5

VVSET1 = SVIN, VPSET1 = 0V 3.0

VVSET1 = SVIN, VPSET1 = SVIN 3.3

88PG82XX

Datasheet

Page 18 Document Classification: Proprietary Information April 23, 2008, 2.00

Output V oltage 2, Logic

Programmability VOUT2 VVSET2 = 0V, VPSET2 = 0V 0.8

VVSET2 = 0V, VPSET2 = SVIN 1.0

VVSET2 = SVIN, VPSET2 = 0V 1.2

VVSET2 = SVIN, VPSET2 = SVIN 1.5

Percentage Set RVSET = 11K -10

RVSET = 18K -7.5

RVSET = 30K -5

RVSET = 51K -2.5

RVSET = 0K 0

RVSET = 100K 2.5

RVSET = 160K 5

RVSET = 270K 7.5

RVSET = 470K 10

Output Voltage Line

Regulation VLNREG SVIN = PVIN = 3.0V to 5.0V

VOUT = 1.5V

ILOAD = IOUT(MAX)/4

0.05 %

Output Voltage Load

Regulation VLDREG SVIN = PVIN = 5.0V

VOUT = 1.5V

ILOAD = IOUT(MAX)/4 to IOUT(MAX)

0.05 %

Switching Frequency fSW ILOAD = IOUT(MAX)/2 1 MHz

Switch Leakage

Current ILSW SVIN = PVIN = 5V, VEN = 0V

VSW = PVIN

150

μA

SVIN = PVIN, VEN = 0V

VSW = SGND = PGND 150

Power-On Reset

Threshold Voltage for

Buck1

VPORTH VOUT > 1.35V VOUT*

90% V

VOUT < 1.32V VOUT-13

0 mV

Power-On Reset

Threshold Voltage for

Buck2

VPORTH VOUT > 1.35V VOUT*

90% V

VOUT < 1.32V VOUT-13

0 mV

Power-On Reset

Output Low Voltage VPORL ISINK = 2 mA, VEN = SVIN 0.4 V

Power-On Reset Leak-

age Current IPOR VEN = 5V 1 μA

Power-On Reset Delay tRESET 40 ms

Parameter Symbol Conditions Min Typ Max Units

Functional Description

Regulation and Start-up

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3Functional Description

Figure 3: 88PG82XX Block Diagram

3.1 Regulation and Start-up

The step-down switching regulator uses Puls e Width Modulation (PWM) and Pulse Frequency

Modulation (PFM) modes to regulate the output voltage using digital control. The mode of operation

depends on the level of output current and the output voltage.

In steady states, the step-down switching regulator monitors the current flowing through the inductor

to determine if the regulator is handling heavy or light load applications. For heavy load applications,

the step-down regulator operates in the PWM mode (B and C) to minimize the ripple current for

optimum efficiency and to minimize the ripple output voltage. The step-down regulator operates in

the PFM and Discontinuous Conduction Mode (DCM) (A and D) to limit the switching actions for

optimum efficiency in light load applications. In this mode, the average output voltage is slightly

higher than the average output voltage for heavy transient load applications.

BAND-GAP

VOLTAGE

REFERENCE

OSCILLATOR

RESISTOR

SENSING

CIRCUITRY

DSP 1 PWM

CONTROL

A/D 1

SW1

SFB1

PSET1

VSET1

SVIN

R8R7

OFF

SGND

PVIN1

INTERNAL

CIRCUITRY

POWER

SUPPLY

PGND1

RESISTOR

NETWORK

THERMAL

SHUTDOWN

150

Serial

Data

Interface

POR1

Vin

VPOR

Vin

2.75V to 5.5V

Vout 1

SW2

SFB2

PGND2

Vout 2

PSET2

R6R5

VSET2

RESISTOR

NETWORK

UNDER-

VOLTAGE

LOCKOUT

FAULT

PVIN2

SFB1

POR2

DSP 2 PWM

CONTROL

A/D 2

RESISTOR

SENSIN G

CIRCUITRY

A/D 1 A/D 2

DSP 2DSP 1

40us/40ms 40us/40ms

PGood2

PGood1

SDI

EN 1

EN 2

Current

Sense

Current

Sense

SW2

88PG82XX

Datasheet

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Figure 4: Output Voltage Window

3.1.1 Soft Start and Sequencing

The 88PG82XX device’s outputs can either be sequenced to start up together or have VOUT1 start

followed by VOUT2. When the SDI pin is low, the VOUT1 and VOUT2 will start up together with a start

up time in the order of 100 μs, as shown in Figure 5. If the SDI pin is high, then VOUT1 will start first

and VOUT2 will start as soon as VOUT1 is within its specified tolerance (see Figure 6). Both outputs

will have a soft start ramp. The POR2 output will go high 40 ms after VOUT2 is within its regulation

limits.

Soft start is a highly desirable property in “Hot-Plug” applications. The 88PG82XX starts up in less

then 100 μs when soft-start is disabled (Figure 7). However in soft-start mode, the 88PG82XX

controls the rise time of the output voltage, thereby dramati c ally reducing the inrush current. The

88PG82XX rise time is roughly 0.25V/ms and it is independent of ou tput capacitance and load

current (see Figure 8). Figure 9 shows the output voltage rise time with a 100 μF output capacitor.

Although there is a difference in output capacitance between Figure 6 and Figure 9, the output

voltage rise time difference is less than 0.1 ms.

Typical V

OUT

PFM Mode

PWM Mode

PFM Mode

VEN

VOUT1

VOUT2

Figure 5: Startup without

Sequencing

2V/DIV

1V/DIV

VIN

VOUT1

VOUT2

Figure 6: Startup with Sequencing

and Soft Start (COUT= 22 μF)

5V/DIV

1.0V/DIV

1V/DIV

1.0 ms/DIV 2.0 ms/DIV

Functional Description

Regulation and Start-up

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VOUT

Figure 7: Fast Startup (0.8V, 1.2V,

1.8V, 2.5V, 3.3V)

500mV/DIV VOUT

Figure 8: Soft Start up (0.8V, 1.2V,

1.8V, 2.5V, 3.3V)

500mV/DIV

20 μs/DIV 2.0 ms/DIV

VOUT

IIN

Figure 9: Inrush Current with COUT =

100 μF

500 mV/DIV

100 mA/DIV

5.0 ms/DIV

88PG82XX

Datasheet

Page 22 Document Classification: Proprietary Information April 23, 2008, 2.00

3.2 Output Voltage Settings

3.2.1 Logic Programmability

The output voltage of the step-down switching regu lator can be programmed by connecting VSET

and PSET pins to SGND and/or SVIN. This can be very useful for standard output voltages.

Table 8: Logic Programmability Table

VVSET1 VPSET1 VOUT1 VVSET2 VPSET2 VOUT2

SGND SGND 1.8V SGND SGND 0.8V

SGND SVIN 2.5V SGND SVIN 1.0V

SVIN SGND 3.0V SVIN SGND 1.2V

SVIN SVIN 3.3V SVIN SVIN 1.5V

SGND 11K≤RPSET2≤475K Hi-Z SGND 11K≤RPSET2≤475K Hi-Z

Functional Description

Output Voltage Settings

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3.2.2 Serial Programmability

The output voltage of the step-down switching regulator can also program by using 18-bit serial data

into the SDI pin.

Figure 10: Serial Programmability

BIT

"1"

Pulse "0"

pulse "0"

pulse

"1"

Pulse

"1"

Pulse

"1"

Pulse "1"

Pulse

DATA FIEL D

D7 D6 D5 D4 D3 D2 D1 D0

The period of a pulse is 1 μs +/- 200 ns

HIGH

> 1. 4V

Low

< 0.8V

HIGH

LOW

For "1" pulse, the hi gh i s 0.75 μs +/- 150 ns

and t he l ow period i s 0.25 μs+/-50 ns

For "0" pul se , the hi gh i s 0. 25 μs +/- 50 ns

and t he l ow period i s 0.75 μs +/-150 ns

LOW

HIGH

The write operati on :

1) E ach write sequence needs 18 pul se s t o compl ete.

2) D urin g a non- wri te operati on, t he i nput nee ds to be at V

LOW

(<0.8V).

3) I n b etween t wo s ucc ess i ve write operations, the SDI i n put need s to

be at V

LOW

(<0 . 8V) f or a m i ni m um of 10 μs

Write

sequence 2

Write

sequence

Low for at l east

10 μs

WR ITE MODE

"1" pulse

"0" pulse

BIT

7BIT

6BIT

5BIT

4BIT

3BIT

1BIT

Registor

Address

Chip

Select

Start Stop

88PG82XX

Datasheet

Page 24 Document Classification: Proprietary Information April 23, 2008, 2.00

The first 4 bits (MSB-bits) of the data field are used to select th e output voltage where the second 4

bits (LSB-bits) of the data field are used to trim the output voltage (percent of output voltage). The

default value for the data field is as follows.

On power up, the output voltage is set according to RPSET and RVSET. The output voltage can then

be field programmed by setting bit 3 and bit 7 to “1”. The output voltage and percent set are selected

according to Table 6.

All combinations of the VSET (Table 8) can be used with all combinations of the PSET (Table 8) to

provide maximum flexibility in output voltage selection (Table 6).

To select the output voltage, use the value from Table 7 to program the address bits.

Table 9: Default Value of Data Field

Data Field

Description Voltage Set Percent Set

Bits 76543210

Default Value 00100100

Table 10: Voltage and Percentage Set

Data Field VOUT (V) Data Field Percent Set

Bits 7654 3210

Value 1 0 0 0 0.8 1 0 0 0 -7.5%

1 0 0 1 1.0 1 0 0 1 -10%

1 0 1 0 1.2 1 0 1 0 -5.0%

1 0 1 1 1.5 1 0 1 1 -2.5%

1 1 0 0 1.8 1 1 0 0 +2.5%

1 1 0 1 2.5 1 1 0 1 +5.0%

1 1 1 0 3.0 1 1 1 0 +7.5%

1 1 1 1 3.3 1 1 1 1 +10%

Table 11: Output Voltage Selection

Description Register Address Output Voltage Selection

Bits 3210

Value 0000 V

OUT1

0010 V

OUT2

Functional Description

Output Voltage Settings

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3.2.3 Output Voltage – AnyVoltage™ Technology

The output voltage of the step-down switching regulator is programmed by using Table 8 or Table 9

to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the

PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 165

kΩ resistor is selected for the VSET pin, and an 11 kΩ resistor is selected for the PSET pin. The 165

kΩ resistor sets the output voltage to 2.5V and the 11 kΩ resistor trims the set voltage by -10%.

Using the VSET resistor’s value greater than 619 kΩ or less than 7.68 kΩ disables the step-down

switching regulator and sets the SW pin to high impedance. If the VSET resistor’s value is outside

the 5% tolerance, the output can be either hig her or lower than the set voltage.

Using resistor values greater than 61 9 kΩ or less than 7.68 kΩ for the PSET pin does not affect the

set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor,

the percent value can be either higher or lower if the PSET resistor’s value is outside the 5%

tolerance.

Table 12: AnyVoltage™ Programming Table for 1% Resistors

PSET

-10.0% -7.5% -5.0% -2.5% 0% 2.5% 5.0% 7.5% 10.0%

11k 18.7k 31.6k 53.6k GND 97.6k 165k 280k 475k

VSET

11k 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880

18.7k 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100

31.6k 1.080 1.110 1.140 1.170 1.200 1.230 1.260 1.290 1.320

53.6k 1.350 1.388 1.425 1.463 1.500 1.538 1.575 1.613 1.650

97.6k 1.620 1.665 1.710 1.755 1.800 1.845 1.890 1.935 1.980

165k 2.250 2.313 2.375 2.438 2.500 2.563 2.625 2.688 2.750

280k 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3.225 3.300

475k 2.970 3.053 3.135 3.218 3.300 3.383 3.465 3.548 3.630

88PG82XX

Datasheet

Page 26 Document Classification: Proprietary Information April 23, 2008, 2.00

The VSET and PSET resistors are read once during start-up before the output voltage is turned on.

After the output voltage is turned on, the output voltage can change to different values using serial

programming interface. Otherwise to configure the output to a different voltage, power has to recycle

or the 88PG82XX has to turn OFF and back ON using the shutdown pin.

Figure 11 shows the startup waveforms of the 88PG82XX. Once the input voltage (VIN) is above the

under voltage lockout (UVLO) upper threshold (UTH), the VSET and PSET pin become active.

Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps.

After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V

reference. If the VSET voltage is below internal reference voltage, the current source proceeds to

the next step. Once the VSET voltage is above the internal reference voltage the sequence stops

and the output voltage (VOUT) is allowed to turn on. The Figure 12 shows the VSET waveform for

VSET = 2.5V and PSET = –5% output. The 88PG82XX keeps track of how many steps are required

to determine the appropriate output voltage. Table 10 provides the number of steps necessary for

each output voltage option. Using a VSET resistor of 165 kΩ requires the current source to step 4

times, and a PSET resistor of 31.6 kΩ requires 7 steps.

Table 13: AnyVoltage™ Programming Table for 5% Resistors

PSET

-10.0% -7.5% -5.0% -2.5% 0% 2.5% 5.0% 7.5% 10.0%

11k 18k 30k 51k GND 100k 160k 270k 470k

VSET

11k 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880

18k 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100

30k 1.080 1.110 1.140 1.170 1.200 1.230 1.260 1.290 1.320

51k 1.350 1.388 1.425 1.463 1.500 1.538 1.575 1.613 1.650

100k 1.620 1.665 1.710 1.755 1.800 1.845 1.890 1.935 1.980

160k 2.250 2.313 2.375 2.438 2.500 2.563 2.625 2.688 2.750

270k 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3.225 3.300

470k 2.970 3.053 3.135 3.218 3.300 3.383 3.465 3.548 3.630

Functional Description

Output Voltage Settings

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The 88PG82XX provides an innovative tech nique to set the output voltage. During start-up it reads

the value of external resistors, which are located outside the regulator’s feedback loop to program

the output voltage. By placing the output voltage programmi ng resistor outside the regulator’s

feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable

regulators use 1% resistors to set the output voltage. However , these resistors are located inside the

feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in

an overall initial accuracy of 3%. Whereas, the 88PG82XX initial accuracy is 2% for any of the eight

output voltages.

The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The

output voltage can potentially be programmed to the lower output voltage if ther e is contamination,

which introduces excessive leakage current on the VSET and PSET pin, especially for a R VSET and

RPSET of 470kΩ. The parasitic resistance on these nodes must be greater than 3 MΩ and the stray

capacitance must be less than 25 pF; otherwise, a 3.3V output can potentially end up at 3V.

VIN

VOUT

VVSET

VPSET

Figure 11: Startup Sequence

2V/DIV

1V/DIV

VVSET

VPSET

Figure 12: VSET = 2.5V and PSET =

-5%

500mV/DIV

2.0 ms/DIV 200 μs/DIV

Table 14: Output Voltage Option Steps

Step VOUT (V) RVSET (K) Step PSET (%) RSPSET (k)

100 100

23.3 475 2+10 475

33.0 280 3+7.5 280

42.5 165 4+5.0 165

51.8 97.6 5+2.5 97.6

61.5 53.6 6-2.5 53.6

71.2 31.6 7-5.0 31.6

81.0 18.7 8-7.5 18.7

90.8 11 9-10 11

88PG82XX

Datasheet

Page 28 Document Classification: Proprietary Information April 23, 2008, 2.00

3.3 Undervoltage Lockout (UVLO)

This feature ensures that the internal MOSFETs have adequate voltage levels to operate properly.

When the input voltage drops below 2.55V (typical), both MOSFETs are off until the input rises

above the upper threshold of 2.65V (typical).

3.4 Over Voltage Protection (OVP)

An over voltage comparator guards against transient overshoots, as well as other serious conditions,

that may damage the IC. When the input voltage is rises above 5.7V (typical), both internal

MOSFETs are turned off until the input voltage drops below the lower thresh old of 5.6V (typical)

Figure 13: UVLO and OVP Waveforms

3.5 Power-On Reset (POR)

The Power-On Reset (POR) pin is an active-high, open-drain output pin. This outpu t is held low

when the output voltage of the step-down regulator is below the threshold. When the output voltage

is above the threshold, the Power-On Reset pin goes hi gh 40 ms later. Setting th e output voltage

greater than 1.35V, the threshold voltage is 0.9% * VOUT (typical). Setting the output voltage less than

1.32V, the threshold voltage is VOUT – 130 mV (typical). A built-in 25 µs (tDELAY) delay is

incorporated to prevent nuisance tripping.

Figure 14: Power-On Reset Waveforms

OVP_HTH

UVLO-HTH

UVLO-LTH

Buck 2 Out put

Disable

OVP-LTH

Undefined

Buck 2 Output

Enable

BUCK 1 Output

Disable

BUCK 1 O utp ut

Enable

VIN

VPOR

VPORH

VPORL

< t DELAY

> t DELAY

40 ms

VOUT

VPOOD_TH

Functional Description

Thermal Shutdown

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3.6 Thermal Shutdown

When the junction temperature of the 88PG82XX e xceeds 150 °C (typical), the thermal shutdown

circuitry disables the step-down regulator. The step-dow n switching regulator is enabled when the

junction temperature is decreased to 105 °C (typical).

3.7 Adaptive Transient Response

The 88PG82XX device’s Smart Technology allows the step-down switching regulator to quickly

respond to the multiple step loads and maintain stability over a wide range of applications. Figure 15

shows an example of a second step-load applied while the output voltage of the step-down switching

regulator increased due to the inductive kick from the first step-loa d.

Condition: VIN = 5.0V, RSVIN = 10Ω, CSVIN = 0.1 µF, CPVIN = 22 µF, L = 3.3 µH, COUT = 22 µF, VOUT

= 1.2V, ILOAD = 500 mA to 1.5A.

The worst case overshoot (VSOAR) during a full-load to light-load transient due to stored inductor

energy (Figure 15) can be calculated as:

Although the VSOAR cannot be eliminate d, its amplitude can be controlled based on the COUT

capacitor value. The appropriate COUT value can easily be calculated for the acceptable VSOAR level

for each specific application.

VOUT

ILOAD

Figure 15: Adaptive Transient

Response

100mV/DIV

1A/DIV

20 μs/DIV

VSOAR ILOAD MAX()

2L•Δ

2COUT VOUT

••

---------------------------------------------

COUT ILOAD MAX()

2L•Δ

2VSOAR VOUT

••

---------------------------------------------

88PG82XX

Datasheet

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THIS PAGE INTENTIONALLY LEFT BLANK

Functional Characteristics

Start-Up Waveforms

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 31

4Functional Characteristics

The following applies un less otherwise noted: TA = 25°C, RSVIN = 10Ω, CSVIN = 0.1 µF, CPVIN = 2 x 22 µF, L1 = L2 = 3.3 µH, COUT

(BUCK1) = 22 µF (ceramic), COUT (BUCK2) = 22 µF (ceramic).

4.1 Start-Up Waveforms

NOTE: When the input voltage rises above the UVLO’s upper threshold, there is a delay (4 ms typ) before the

step-down regulator’s output voltage turns on.

VEN

VBUCK1

VBUCK2

Figure 16: Startup Using the Enable

2V/DIV

1V/DIV

VEN

VBUCK1

VBUCK2

Figure 17: Turn Off Using the

Enable Pin

2V/DIV

1V/DIV

1 ms/DIV 1 ms/DIV

VIN = 5.0V ILOAD = No Load VIN = 5.0V ILOAD = 50 mA

VBUCK1= 1.2V tDLY= 4.0 ms VBUCK1= 1.2V

VBUCK2= 1.2V SDI = 0V VBUCK2= 1.2V

VIN

VBUCK1

VBUCK2

VPOR1

VPOR2

Figure 18: Startup Sequence

5V/DIV

2V/DIV

5V/DIV

VIN

VBUCK1

VBUCK2

VPOR1

VPOR2

Figure 19: Hot Plug

5V/DIV

2V/DIV

5V/DIV

10 ms/DIV 10 ms/DIV

VIN = 5.0V VBUCK2= 1.2V VIN = 5.0V VBUCK2= 1.2V

VBUCK1= 1.2V ILOAD = No Load VBUCK1= 1.2V ILOAD = No Load

SDI = 0V SDI = 0V

88PG82XX

Datasheet

Page 32 Document Classification: Proprietary Information April 23, 2008, 2.00

4.2 Short-Circuit Waveforms

VIN

VBUCK1

VBUCK2

Figure 20: UVLO and OVP Thresholds

2V/DIV

1V/DIV

VIN

VBUCK1

VBUCK2

Figure 21: Input Sof t St art and S tart

up Sequence

5V/DIV

1V/DIV

100 ms/DIV 2.0 ms/DIV

VIN = 0 to 6.0V VUVLO(HTH) = 2.60 8 V VIN = 5V

VBUCK1= 1.0V VUVLO(LTH)= 2.531V VBUCK1= 1.2V

VBUCK2= 1.0V VOVP(HTH) = 5.64V VBUCK2= 1.2V

ILOAD1 = 10 mA VOVP(LTH) = 5.32V ILOAD = No Load

ILOAD2 = 10 mA SDI = SVIN

VSW

VBUCK

IIND

Figure 22: Step-Down Short-Circuit

Response

5V/DIV

500 mV/DIV

2A/DIV

200 μs/DIV

Short Circuit

Peak Current Limit

Functional Characteristics

Switching Waveforms

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4.3 Switching Waveforms

NOTE: For repeatabili ty of measuring outpu t ripple (VBUCK (P-P )) for th e BUCK regul ator, the standard test

procedure limits the scope bandwidth to 20 MHz and uses a coax cable with very short leads

terminated into 50Ω. The coax leads must be routed away from the switching node as much as

possible.

VSW

IIND

VBUCK

VIN

Figure 23: Switching Waveforms -

PWM mode

5V/DIV

1A/DIV

10 mV/DIV

100 mV/DIV

VSW

IIND

VBUCK

VIN

Figure 24: Switching Waveforms -

PWM mode

5V/DIV

1A/DIV

10 mV/DIV

50 mV/DIV

500 ns/DIV 500 ns/DIV

CIN = 22 μFV

IN(P-P) = 77.3 mV CIN = 2 x 22 μFV

IN(P-P) = 58.9 mV

VIN = 5.0V IIND(P-P) = 412.3 mA VIN = 5.0V IIND(P-P) = 446.8 mA

VBUCK= 1.2V IIND(PK) = 1.73A VBUCK= 1.2V IIND(PK) = 1.76A

IOUT = 1.5A Freq = 940 kHz IOUT = 1.5A Freq = 940 kHz

VOUT(P-P) = 5.4 mV (Note) VOUT(P-P) = 5 mV (Note)

VSW

VBUCK

IIND

Figure 25: Switching Waveforms -

DCM Mode

5V/DIV

20 mV/DIV

200 mA/DIV

VSW

VBUCK

IIND

Figure 26: Switching W aveforms - DCM

Mode-Zoom

5V/DIV

20 mV/DIV

200 mA/DIV

5 μs/DIV 500 ns/DIV

VIN = 5.0V IIND(PK) = 440 mA VIN = 5.0V

VBUCK= 1.2V Freq = 187 kHz VBUCK= 1.2V

IOUT = 29 mA IOUT = 29 mA

VOUT(P-P) =22 mV (Note) Ringing Freq = 6.5 MHz

88PG82XX

Datasheet

Page 34 Document Classification: Proprietary Information April 23, 2008, 2.00

4.4 Load Transient Waveforms

4.4.1 Step-Down Regulator

VBUCK1

VBUCK2

Figure 27: PWM Output Ripple

Voltage

10 mV/DIV

100 ms/DIV

VIN = 5.0V IOUT2 = 1.5A

VBUCK1= 1.2V VBUCK1(P-P) = 7.3 mV (Note)

VBUCK2= 1.2V VBUCK2(P-P) = 8.2 mV (Note)

IOUT1 = 1.5A

VSW

VBUCK

ILOAD

IIND

Figure 28: Fast Load Rise Time

5V/DIV

100 mV/DIV

1A/DIV

VSW

VBUCK

ILOAD

IIND

Figure 29: Slow Load Rise Time

5V/DIV

100 mV/DIV

1A/DIV

2 μs/DIV 2 μs/DIV

VIN = 5.0V COUT = 22 μFV

IN = 5.0V COUT = 2 μF

VBUCK= 1.2V tRISE = 13.1 A/μsV

BUCK= 1.2V tRISE = 1.2 A/μs

IOUT = 500 mA to 1.5A IOUT = 500 mA to 1.5A

Functional Characteristics

Load Transient Waveforms

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 35

VSW

VBUCK

ILOAD

IIND

Figure 30: Fast Load Fall Time

5V/DIV

100 mV/DIV

1A/DIV

VSW

VBUCK

ILOAD

IIND

Figure 31: Slow Load Fall Time

5V/DIV

100 mV/DIV

1A/DIV

2 μs/DIV 2 μs/DIV

VIN = 5.0V COUT = 22 μFV

IN = 5.0V COUT = 22 μF

VBUCK= 1.2V tFALL = 88 A/μsV

BUCK= 1.2V tFALL = 1.2 A/μs

IOUT = 500 mA to 1.5A IOUT = 500 mA to 1.5A

VBUCK

ILOAD

Figure 32: Load T ransient Response

100 mV/DIV

1A/DIV

VBUCK

ILOAD

Figure 33: Double-Pulsed Load

Response

100 mV/DIV

1A/DIV

20 μs/DIV 20 μs/DIV

VIN = 5.0V ILOAD = 500 mA to 1.5A VIN = 5.0V ILOAD = 500 mA to 1.5A

VBUCK= 1.2V tRISE = 13.8 A/μsV

BUCK= 1.2V tRISE = 11.2 A/μs

COUT = 22 μFt

FALL = 121 A/μsC

OUT = 22 μFt

FALL = 95.3 A/μs

88PG82XX

Datasheet

Page 36 Document Classification: Proprietary Information April 23, 2008, 2.00

4.4.2 Cross-Talk Waveforms

VBUCK

ILOAD

Figure 34: Load T ransient Response

100 mV/DIV

1A/DIV

VBUCK

ILOAD

Figure 35: Double-Pulsed Load

Response

100 mV/DIV

1A/DIV

20 μs/DIV 20 μs/DIV

VIN = 5.0V ILOAD = 500 mA to 1.5A VIN = 5.0V ILOAD = 500 mA to 1.5A

VBUCK= 1.2V tRISE = 15 A/μsV

BUCK= 1.2V tRISE = 13.2 A/μs

COUT = 2 x 22 μFt

FALL = 95.2 A/μsC

OUT = 2 x 22 μFt

FALL = 91 A/μs

VOUT1

VOUT2

IOUT_2

Figure 36: Cross-talk Continuous

Mode

20 mV/DIV

200 mV/DIV

2A/DIV

VOUT1

VOUT2

IOUT_2

Figure 37: Cross-talk

Discontinuous Mode

20 mV/DIV

200 mV/DIV

2A/DIV

20 μs/DIV 20 μs/DIV

IOUT1 = 30 mA VOUT1 = 1.5V IOUT1 = 500 mA VOUT1 = 1.5V

IOUT2 = 0.5A to 2.0A VOUT2 = 1.5V IOUT2 = 0.5A to 2.0A VOUT2 = 1.5V

Functional Characteristics

Output Voltage Transie nt Waveforms

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 37

4.5 Output Voltage Transient Waveforms

The following graphs show the effect of changing the step-down regulator’s output voltage using the

serial interface. Depending on the change in the step-size of the output voltage, the output load, and

the output capacitance, the power-on reset pin de-asserts when the changes of the output voltage

occur beyond the 25 μs (typical) delay.

4.5.1 Step-Down Regulator

VBUCK

VPOR

SDI

Figure 38: VOUT = 1.0V to 1.2V with

No Load

500 mV/DIV

5V/DIV

VBUCK

VPOR

SDI

Figure 39: VOUT = 1.0V to 1.5V with

No Load

500 mV/DIV

5V/DIV

100 μs/DIV 100 μs/DIV

VIN = 5.0V VIN = 5.0V

COUT= (2 x 22) + 1000 μFC

OUT= (2 x 22) +1000 μF

VBUCK

VPOR

SDI

Figure 40: VOUT = 1.0V to 1.2V with

ILOAD = 1.5A

500 mV/DIV

5V/DIV

VBUCK

VPOR

SDI

Figure 41: VOUT = 1.0V to 1.5V with

ILOAD = 1.5A

500 mV/DIV

5V/DIV

100 μs/DIV 100 μs/DIV

VIN = 5.0V VIN = 5.0V

COUT= (2 x 22) + 1000 μFC

OUT= (2 x 22) +1000 μF

88PG82XX

Datasheet

Page 38 Document Classification: Proprietary Information April 23, 2008, 2.00

4.6 Line Transient Waveforms

VBUCK

VPOR

SDI

Figure 42: VOUT = 1.2V to 1.0V with

ILOAD = 1.5A

500 mV/DIV

5V/DIV

VBUCK

VPOR

SDI

Figure 43: VOUT = 1.5V to 1.0V with

ILOAD = 1.5A

500 mV/DIV

5V/DIV

100 μs/DIV 100 μs/DIV

VIN = 5.0V VIN = 5.0V

COUT= (2 x 22)+1000 μFC

OUT= (2 x 22)+1000 μF

VIN

VBUCK

Figure 44: Line Transient @ VIN = 3.6V

1V/DIV

20 mV/DIV

VIN

VBUCK

Figure 45: Line Transient @ VIN = 4.5V

1V/DIV

20 mV/DIV

2 ms/DIV 2 ms/DIV

VIN = 3.6V VBUCK = 1.2V VIN = 4.5V VBUCK = 1.2V

CIN= 22 μFI

LOAD = 1.5A CIN= 22 μFI

LOAD = 1.5A

3.2V 3.6V

4.1V 4.5V

Typica l Ch ara cteris t ics

Efficiency Graphs

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 39

5Typical Characteristics

5.1 Efficiency Graphs

5.1.1 Efficiency Graphs in Log Scale

Efficiency vs. Output Current

Vi n = 5.0V

100

00.511.5

Out p ut Cu rren t (A)

Efficiency (%)

3.3V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G1

Effic i enc y vs. O ut put Current

Vi n = 3.3V

100

00.511.5

Output Current (A )

Efficiency (%)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G2

Efficiency vs . Output Current

Vi n = 5.0V

100

0.01 0.1 1 10

Out p ut Current (A)

Efficiency (%)

3.3V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G3

Efficiency vs . Output Current

Vin = 3. 3V

100

0.01 0.1 1 10

Output Current (A)

Efficiency (%)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G4

88PG82XX

Datasheet

Page 40 Document Classification: Proprietary Information April 23, 2008, 2.00

5.2 Load Regulation

5.3 Dropout Voltage

5.4 RDS (ON) Resistance

Output V ol t age vs. O ut put Current

Vout = 1. 5V

1.40

1.45

1.50

1.55

1.60

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Out put Current (A )

Output Voltage (V )

3.3V

5.0V

26 G5

88PG8226

Buck Dropout vs. Load Cur r ent

Vin = 3.2, Vout = 3.3V

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

00.511.52

Load Current(A)

Buck Dropout (V)

85C

25C

-40C

26 G6

TOP Switch

Re sist an ce vs. Te mperatu re

0.070

0.080

0.090

0.100

0.110

0.120

0.130

-40-200 20406080

Temperature (C)

Resistance (ohm )

Vi n = 3.0V

Vi n = 4.0V

Vi n = 5.0V

26 G7

BOT Switch

Resist an ce vs. Temperature

0.020

0.030

0.040

0.050

0.060

0.070

-40-200 20406080

Temperature (C)

Resistance (ohm)

Vi n = 3.0V

Vi n = 4.0V

Vi n = 5.0V

26 G8

Typica l Ch ara cteris t ics

IC Case and Inductor Temperature

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 41

5.5 IC Case and Inductor Temperature

The following data was taken using a 1.4 square inch PCB 1 oz. copper and L = 1.2 μH. Actual

results depend upon the size of the PCB proximity to other heat emitting components.

TOP S wi tch

R e sistance v s. Input Voltage

0.070

0.080

0.090

0.100

0.110

0.120

0.130

3 3.5 4 4.5 5

Input Voltage(V)

Resis tance (o h m)

85C

25C

-40C

26 G9

BOT Switch

Resistance vs. Input Volta ge

0.020

0.030

0.040

0.050

0.060

0.070

3 3.5 4 4.5 5

Input Voltage (V)

Resistance (ohm)

85C

25C

-40C

26 G10

Input Current vs. O ut put Cur rent

Vin = 5V, Ta = 25 ° C

0.0

0.5

1.0

1.5

2.0

0 0.5 1 1.5 2

Out put Curr ent (A)

Input Curr ent ( A)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G11

Input Current vs. Output Current

Vin = 3.3V, Ta = 25°C

0.0

0.5

1.0

1.5

2.0

00.511.52

Output Current (A)

Input Current (A)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G12

IC Case Temperature vs. Out put Current

Vin = 5V, T a = 25°C

0 0.5 1 1.5 2

Out put Curr e nt ( A)

Temperat ur e ( ° C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G13

IC Case Temperature vs. O utput Current

Vin = 3.3V, Ta = 25°C

00.511.52

Output Current ( A)

Temperature (°C)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G14

88PG82XX

Datasheet

Page 42 Document Classification: Proprietary Information April 23, 2008, 2.00

Inductor Temperat ur e vs. O ut put Cur r ent

Vin = 5V, Ta = 25° C

00.511.52

Output Current (A)

Temperature(°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G15

Inductor Temperatur e vs. Output Current

Vin = 3.3V, T a = 25°C

0 0.5 1 1.5 2

Output Current (A)

Temper ature (°C)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G16

I nd uctor Temper at ure vs. Ou tp ut Current 2

Output Current 1 = 2A

Vin = 3.3V, Ta = 25°C

0 0.5 1 1.5 2

Output Curr e nt 2 (A)

Temperat ure ( ° C)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G17

IC Case Temperatur e vs. Output Current 2

Output Current 1 = 2A

Vin = 3.3V, T = 25°C

0 0.5 1 1.5 2

Out put Current 2 ( A)

Temperat u re ( °C)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

26 G1 8

Typica l Ch ara cteris t ics

Input Voltage Graph s

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 43

5.6 Input Voltage Graphs

The 88PG8237 part was used to determine the fol lowing graph data.

Load = No Load VEN = GND

Supply Current vs. Input Voltage

0.0

1.0

2.0

3.0

4.0

2.533.544.55

Input Vol tag e (V )

Supply Current (mA )

26 G19

Shutdow n Supply Current vs. Input Voltage

See Test Conditions

2.5 3 3.5 4 4.5 5 5.5 6

Input Voltage (V)

Shutdown Current (uA)

Ena bl e Threshol d V out 1 vs. Input Vol t age

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2.533.544.55

Input Vo ltage (V )

Enabl e T hreshol d (V)

UTH-Enable

LTH-Disable

26 G21

88PG82XX

Datasheet

Page 44 Document Classification: Proprietary Information April 23, 2008, 2.00

5.6.1 Step-Down Regulator

IOUT(BUCK) = 375 mA VOUT(BUCK) = 1.5V

IOUT(BUCK) = 0.75A

VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V

IOUT(BUCK) = 0.375A - 1.5A IOUT(BUCK) = 0.75A

Out put V ol tage vs. Input Vol t ag e

1.47

1.485

1.5

1.515

1.53

33.544.55

Input V ol tage (V )

Out pu t Voltag e (V)

Vout1

Vout2

26 G22

E fficie n cy vs. Inpu t V o lta g e

80%

85%

90%

95%

100%

33.544.55

Input Volt age (V)

Efficiency

Vout1

Vout2

26 G23

Load Regulati on vs . Input V ol t age

-0.20%

-0.10%

0.00%

0.10%

0.20%

33.544.55

I n pu t Voltage (V )

Load Regulation

Vout1

Vout2

26 G24

Frequenc y vs. Input Voltage

800

850

900

950

1000

33.544.55

Input Vol tage (V )

Frequency (kHz)

Vout1

Vout2

26 G25

Average Output Current Li m i t vs. Input V ol tage

0.0

1.0

2.0

3.0

4.0

5.0

33.544.55

Input Voltage (V)

Current Limit (A)

Vout1

Vout2

26 G26

Typica l Ch ara cteris t ics

Temperature Graphs

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 45

5.7 Temperature Graphs

The 88PG8237 part was used to determine the fol lowing graph data.

IOUT(BUCK1) = No Load VIN = 5V

IOUT(BUCK2) = No Load VEN = GND

VIN= 5V VIN = 5V

IOUT(BUCK) = 10mA IOUT(BUCK) = 10mA

Supply Current vs. Temperature

-40-200 20406080

Temperature (°C)

Suppl y Current (m A )

26 G27

Shutdown Supply Curr ent vs. Temperature

0.0

20.0

40.0

60.0

80.0

100.0

120.0

-40 -20 0 20 40 60 80

Temperat ure (°C)

Shut down Current(uA)

26 G28

UVLO vs. Temperature

2.4

2.5

2.6

2.7

-40-200 20406080

Temperatur e (°C)

UVL O (V )

UTH

LTH

26 G29

Enable Threshold V out 1 vs. Temperat ure

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-40 -20 0 20 40 60 80

Temperature (°C)

Enabl e T reshol d (V )

UTH - E nabl e

LTH - Disabl e

26 G30

88PG82XX

Datasheet

Page 46 Document Classification: Proprietary Information April 23, 2008, 2.00

5.7.1 Step-Down regulator

VIN = 5.0V VIN = 5.0V

IOUT(BUCK) = 750 mA VOUT(BUCK) = 1.5V

IOUT(BUCK) = 1.5A

VIN = 5.0V VIN = 3.0V - 5.0V

VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V

IOUT(BUCK) = 750 mA - 3A IOUT(BUCK) = 1.5A

VIN = 5.0V

IOUT(BUCK) = 1.5A

Output V olt age vs . Temperature

1.47

1.485

1.5

1.515

1.53

-40-20 0 20406080

Tem perature (°C)

Output Vol t age (V)

Vout1

Vout2

26 G31

Buc k E ffici ency vs . Temperature

80%

85%

90%

95%

100%

-40 -20 0 20 40 60 80

Temperature (°C)

Efficiency

Vout1

Vout2

26 G32

Buck Load Regulat i on vs. Temperat ure

-0.20%

-0.10%

0.00%

0.10%

0.20%

-40-200 20406080

Temperature (°C)

Load Regulat i on

Vout1

Vout2

26 G33

Buc k Line Regulati on vs . Temperature

-0.20%

-0.10%

0.00%

0.10%

0.20%

-40 -20 0 20 40 60 80

Temperature (°C )

Line Regulation

Vout1

Vout2

26 G34

Buck Current Limit vs. Temperature

-40-20020406080

Temperat ure ( °C)

Current L i mi t (A )

Vout1

Vout2

26 G35

Frequency vs. Temperature

800

850

900

950

1000

-40-200 20406080

Temperature (°C)

Frequency (kHz)

Vout1

Vout2

26 G36

Applications Information

PC Board Layout Considerations and Guid el ines

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 47

6Applications Information

6.1 PC Board Layout Considerations and Guidelines

The PC board layout is very critical in any switching converter. An improper layout can contribute to

system instability, excessive EMI (Electro-magnetic interference), and high switching loss. Follow

these basic guidelines for good PC layout:

1. This is a 2-layer board with 1 ground pla ne and 1 routing layer.

2. Copy th e la yout i npu t Figure 48 and Figure 49 as much as possible and use the recommended

BOM in Table 15. Contact the factory where substitutions are made.

3. Review the recommended solder pad layout and notes on page 50.

4. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of

capacitor can be placed in parallel with the input capacitor as long as the Ceramic input

capacitor is placed next to the IC. If Tantalum input capacitor is used, it must be rated for

switching regulator applicatio ns and the operating voltage must be derated by 50%.

5. Any type of capacitor can be placed in parallel with the output capacitor.

6. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors

as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide

the lowest noise and smallest foot print solution.

7. Use planes for the ground, input and output power to maintain good voltage filtering, and to

keep power losses low.

8. If there is not enough space for a power plane for the input supply, then the input supply trace

must be at least 3/8 inch wide.

9. If there is not enough space for a power plane for the output supplie s, th en place the output as

close to the load as possible with a trace at least 3/8 inch wide.

10. Do not lay out the inductor first. The input capacitor placement is the most critical for proper

operation. The AC current circulating throu gh the input capacitor and loop 1 (LP1) are square

wave with rise and fall times of 8 ns and slew rates as high as 300 A/µs (see Figure 46). At

these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per

inch of PCB trace, VIND = L * di/dt. Therefore, the ceramic input capacitor (C2 and C5) must be

placed as close as possible to the PVIN and PGND pins with a short and wide trace as

possible. Also, the PVIN and PGND traces must be placed on the top layer . This will isolate the

fast AC currents from interfering with the analog grou nd plane.

11. The 88PG82XX has two internal grounds, analog (SGND) and power (PGND). The analog

ground ties to all the noise sensitive signal s (PSET, VSET, and SVIN) while the power ground

ties to the higher current power paths. Noise on an analog ground can cause problems with the

IC’s internal control and bias signals. For this reason, separate analog and power ground traces

are recommended. The signal ground is connected to the power ground at one point, which is

the (-) terminal of the output capacitor.

12. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as

close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as

shown in Figure 48, is recommended for best results.

13. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing

capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle.

14. T ry not to route analog or digital lines in close proximity to the power supply especially the VSW

node. If this can’t be avoi ded, shield these lines with a power pla ne placed between the VSW

node and the signal lines.

88PG82XX

Datasheet

Page 48 Document Classification: Proprietary Information April 23, 2008, 2.00

15. PVIN1 and PVIN2 must be connected together and should not be separated.

16. The type of solder paste recommended for QFN packages is “No clean”, due to the difficulty of

cleaning flux residues from beneath the QFN package.

Figure 46: Simpified Schematic

LP1

LP2

I Cin

LP1

I Cout

LP2

LP2 LP1

100k

2.5V/1.5A

Vin

10 ohm

POR 2

100k

51k

88PG82XX

2.75V - 5.5V

1.5V/2.0A

160k R6

Vin

SDI

Vout 2

PGND1

SW2 20

SFB2

SW2 18

SVIN

SW1

PVIN1

PGND2 19

SW1

SFB1

VSET2 14

PSET2 15

POR1 11

POR2 16

PVIN2 17

VSET1 13

PSET1 12

SDI

SGND

Vin

Vout1

0.1uF

100k

POR 1

Applications Information

PC Board Layout Considerations and Guid el ines

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 49

Figure 47: PC Board Schematic

2.5V/1.5A

POR 1

Vin

10 ohm

22uF/6.3V

POR 2

100k

51k

88PG8226

2.75V - 5.5V

1.5V/1.5A

160k R6

Vin

SDI

Vout 2

PGND1

SW2 20

SFB2

SW2 18

SVIN

SW1

PVIN1

PGND2 19

SW1

SFB1

VSET2 14

PSET2 15

POR1 11

POR2 16

PVIN2 17

VSET1 13

PSET1 12

SDI

SGND

3.3uH

22uF/6.3V

Vout 1

Vin

22uF/6.3V

3.3uH

0.1uF

100k

88PG82XX

Datasheet

Page 50 Document Classification: Proprietary Information April 23, 2008, 2.00

6.1.1 PC Board Layout Examples for 88PG82XX

Actual board size = 570 mil x 630 mil; Area = 0.359 Sq. Inches.

Total copper layers = 2 (Top and Bottom)

All the components are on the top layer

Figure 48: Top Silk-Screen, Top Traces, Vias, and Top Copper (Not to Scales)

Actual board size = 711 mil x 1060 mil

Total copper layer = 2

Connect the

BUCK2 output

voltage at

this point

Connect to

the ground

plane of the

board

Connect to

the ground

plane of the

board

Connect to

the ground

plane of the

board

Connect the

BUCK1 output

voltage at

this point

Applications Information

PC Board Layout Considerations and Guid el ines

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 51

Figure 49: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to Scale)

Connect the

POR 2 signal

at this

trace.

Connect the

POR 2 signal

at this

trace.

Connect to

the input

voltage plane

of the board.

Connect to

the ground

plane of the

board.

Connect to

the input

voltage plane

of the board.

Connect to

the input

voltage plane

of the board.

88PG82XX

Datasheet

Page 52 Document Classification: Proprietary Information April 23, 2008, 2.00

6.1.2 Bill of Materials (BOM)

The following tables list the components used with the 88PG82XX.

Table 15: BOM for 88PG82XX

Item Qty. Ref. Manufacturer Part # Manufacturer Description

11U1 88PG8204 Marvell Semiconductor 1MHz, Dual (0.75A/0.75A) Step-Down

Regulator

2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1μF,±10%,X7R,16V,0603 Case Size,

Ceramic

34C2,C3,

C4,C5 C2012X5R0J106MT TDK 10μF,±20%,X5R,6.3V,0805 Case Size,

Ceramic

4 2 L1,L2 1117AS-4R7M Toko 4.7μH, 0.91A, 170mΩ, H=1mm, L=2.8mm,

W=3.0mm

5 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0Ω, 1/16W, 1%, 0402 Case Size

61R2,R3,

R4 ERJ-3GEYJ104V Pansonic - ECG 100Ω, 1/10W, 5%, 0603 Case Size

74R5,R6,

R7,R8 Pansonic - ECG See AnyVoltage Programming Table

1/16W, 1%, 0402 Case Si ze

Item Qty. Ref. Manufacturer Part # Manufacturer Description

11U1 88PG8216 Marvell Semiconductor 1MHz, Dual (1.0A/1.5A) Step -Down Regulator

2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1μF,±10%,X7R,16V,0603 Case Size,

Ceramic

3 1 C3 C2012X5R0J106MT TDK 10μF,±20%,X5R,6.3V,0805 Case Size,

Ceramic

43C2,C4,

C5 C2012X5R0J226MT TDK 22μF,±20%,X5R,6.3V,0805 Case Size,

Ceramic

5 1 L1 A918CY-4R7M=P3 Toko 4.7μH, 0.91A, 170mΩ, H=1mm, L=2.8mm,

W=3.0mm

6 1 L2 A918CY-2R0M=P3 Toko 3.3μH, 1.99A, 39mΩ, H=2mm, L=6.2mm,

W=6.3mm

7 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0Ω, 1/16W, 1%, 0402 Case Size

83R2,R3,

R4 ERJ-3GEYJ104V Pansonic - ECG 100Ω, 1/10W, 5%, 0603 Case Size

94R5,R6,

R7,R8 Pansonic - ECG See AnyVoltage Programming Table

1/16W, 1%, 0402 Case Si ze

Item Qty. Ref. Manufacturer Part # Manufacturer Description

11U1 88PG8227 Marvell Semiconductor 1MHz, Dual (1.5A/2.0A) Step -Down Regulator

2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1μF,±10%,X7R,16V,0603 Case Size,

Ceramic

3 2 C2,C5 C2012X5R0J226MT TDK 22μF,±20%,X5R,6.3V,0805 Case Size,

Ceramic

4 2 C3,C4 C2012X5R0J226MT TDK 22μF,±20%,X5R,6.3V,0805 Case Size,

Ceramic

5 1 L1 A918CY-3R3M=P3 Toko 3.3μH, 1.99A, 39mΩ, H=2mm, L=6.2mm,

W=6.3mm

6 1 L2 A918CY-2R0M=P3 Toko 2.0μH, 2.47A, 24mΩ, H=2mm, L=6.2mm,

W=6.3mm

7 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0Ω, 1/16W, 1%, 0402 Case Size

83R2,R3,

R4 ERJ-3GEYJ104V Pansonic - ECG 100Ω, 1/10W, 5%, 0603 Case Size

Applications Information

PC Board Layout Considerations and Guid el ines

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 53

94R5,R6,

R7,R8 Pansonic - ECG See AnyVoltage Programming Table

1/16W, 1%, 0402 Case Si ze

Item Qty. Ref. Manufacturer Part # Manufacturer Description

11U1 88PG8226 Marvell Semiconductor 1MHz, Dual (1.5A/1.5A) Step -Down Regulator

2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1μF, ±10%, X7R, 16V, 0603 Case Size,

Ceramic

3 2 C2,C5 C2012X5R0J226MT TDK 22μF, ±20%, X5R, 6.3V, 0805 Case Size,

Ceramic

4 2 C3,C4 C2012X5R0J226MT TDK 22μF, ±20%, X5R, 6.3V, 0805 Case Size,

Ceramic

5 2 L1,L2 A918CY-3R3M=P3 Toko 3.3μH, 1.99A, 39mΩ, H=2mm, L=6.2mm,

W=6.3mm

6 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0Ω, 1/16W, 1%, 0402 Case Size

73R2,R3,

R4 ERJ-3GEYJ104V Pansonic - ECG 100Ω, 1/10W, 5%, 0603 Case Size

84R5,R6,

R7,R8 Pansonic - ECG See AnyVoltage Programming Table

1/16W, 1%, 0402 Case Si ze

Item Qty. Ref. Manufacturer Part # Manufacturer Description

11U1 88PG8237 Marvell Semiconductor 1MHz, Dual (2.0A/2.0A) Step -Down Regulator

2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1μF, ±10%, X7R, 16V, 0603 Case Size,

Ceramic

3 2 C2,C5 C2012X5R0J226MT TDK 22μF, ±20%, X5R, 6.3V, 0805 Case Size,

Ceramic

4 2 C3,C4 C2012X5R0J226MT TDK 22μF, ±20%, X5R, 6.3V, 0805 Case Size,

Ceramic

5 2 L1,L2 A918CY-2R0M=P3 Toko 2.0μH, 2.47A, 24mΩ, H=2mm, L=6.2mm,

W=6.3mm

6 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0Ω, 1/16W, 1%, 0402 Case Size

73R2,R3,

R4 ERJ-3GEYJ104V Pansonic - ECG 100Ω, 1/10W, 5%, 0603 Case Size

84R5,R6,

R7,R8 Pansonic - ECG See AnyVoltage Programming Table

1/16W, 1%, 0402 Case Si ze

Table 15: BOM for 88PG82XX

Item Qty. Ref. Manufacturer Part # Manufacturer Description

88PG82XX

Datasheet

Page 54 Document Classification: Proprietary Information April 23, 2008, 2.00

Table 16: Ceramic Capacitor Cross Reference

Manufacturer Manufacturer Part # Description

Taiyo-Yuden CE JMK212BJ226MG-T 22µF

TDK C2012X5R0J226MT

Murata GRM21BR60J226ME39L

Taiyo-Yuden CE JMK212BJ106MG-T 10µF

TDK C2012X5R0J106MT

Murata GRM219R60J106KE190

Taiyo-Yuden RM LMK105BJ104KV-F 0.1µF

TDK C1005X5R1A104K

Mechanical Drawing

88PG82XX Mechanical Drawing

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 55

7Mechanical Drawing

7.1 88PG82XX Mechanical Drawing

88PG82XX

Datasheet

Page 56 Document Classification: Proprietary Information April 23, 2008, 2.00

7.2 Dimensions

Notes:

1. CONTROLLING DIMENSION: MILLIMETER

2. SPECIAL CHARACTERISTICS C CLASS: ccc

Table 17: Package Dimensions

Symbol Dimension in mm

MIN NOM MAX

A 0.80 0.85 1.00

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.20 0.25 0.30

D3.00 BSC

E4.00 BSC

e0.50 BSC

L 0.45 0.50 0.55

R0.10

aaa 0.15

bbb 0.10

ccc 0.10

ddd 0.05

Mechanical Drawing

Typical Pad Layout Dimensions

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 57

7.3 Typical Pad Layout Dimensions

7.3.1 Recommeded Solder Pad Layout

Notes:

1. TOP VIEW

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE IN MILLIMETERS

4. OVERSIZE SOLDER MASK BY 4 MILS OVER PAD SIZE (2 MIL ANNULAR RING)

5. 0.148mm SOLDER MASK (SM) BETWEEN PADS

6. TOLERANCE ±0.05mm

4 x3 Q FN-20

Land Pattern (mm)

3.00

0.50

Package

Outline

4.30

0.25

QFN L ead wi th

No n -S o lder M ask Defin ed T ermin al

(Not to S cale)

0.051 mm

2.0 mils

0.25 mm

9.84 mils

Pad

0.25 mm

9.84 mils

0.148 mm

5.84 mils

SM Pad Pad

0.65

88PG82XX

Datasheet

Page 58 Document Classification: Proprietary Information April 23, 2008, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Ordering Information

Ordering Part Numbers and Package Markings

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 59

8Ordering Information

8.1 Ordering Part Numbers and Package Markings

Figure 50 shows the ordering part numbering scheme for the 88PG82XX devices. Contact Marvell®

FAEs or sales representatives for complete ordering information.

Figure 50: Sample Part Number

8.2 Sample Ordering Part Number

The standard ordering part numbers for the respective solutions are as follows:

Part Number

88PG8204

88PG8216

88PG8226

88PG8227

88PG8237

Custom Code

Custom (Optional)

XX – XXX 1 C000 - T88PG82XX

Environmental

1 = RoHS 6/6 compliant

“-” = RoHS 5/6 compliant

Package Code

NFE = 20-pin QFN

Table 18: 88PG82XX Ordering Part Numbers1

Booking Part

Number Marking Current Ambient

Temperature

Range2

Package3

VOUT1 VOUT2

88PG8204A0-NFE1C000 G204 0.75A 0.75A -40C to 85C 3 X 4 QFN-20

88PG8216A1-NFE1C000 G216 1.0A 1.5A -40C to 85C 3 X 4 QFN-20

88PG8226A1-NFE1C000 G226 1.5A 1.5A -40C to 85C 3 X 4 QFN-20

88PG8227A1-NFE1C000 G227 1.5A 2.0A -40C to 85C 3 X 4 QFN-20

88PG8237A1-NFE1C000 G237 2.0A 2.0A -40C to 85C 3 X 4 QFN-20

1. Contact Marvell for details.

2. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and

correlation with statistical process controls.

3. Package dimensions are in mm.

88PG82XX

Datasheet

Page 60 Document Classification: Proprietary Information April 23, 2008, 2.00

8.3 Package Marking

8.3.1 88PG82XX Package Marking and Pin 1 Locations

Figure 51 is an example of the package marking and pin 1 location for the 88PG847 part. Markings

for the other variants are similar .

Figure 51: 88PG8227 Package Marking and Pin 1 Location

MRVL

G227

YWW#

Marvell Semiconductor

Marking

Year, Work week, Assembly code

Y = Last digit of year

WW = Work week

# = Assembly code

Pin 1 location

Note: The above example is not drawn to scal e. Locations of markings are approximate.

April 23, 2008, 2.00 Document Classification: Proprietary Information Page 61

ARevision History

Table 19: Revision History

Document Type Document Revision

Release Rev. C

• Document brought into new template.

• “Confidential” removed.

• Functional Characteristic Graphs edited.

• Replaced Mechanical Drawing

Marvell. Moving Forward Faster

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

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