KSZ8091MNXCA TR - MICROCHIP TECHNOLOGY

KSZ8091RNA/KSZ8091RND

10Base-T/100Base-TX

Physical Layer Transceiver

Revision 1.2

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • US A • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

August

31, 2015

Revision 1.2

General Description

The KSZ8091RNA is a single-supply 10Base-T/100Base-

TX Ethernet physical-layer transceiver for transmission

and reception of data over standard CAT-5 unshielded

twisted pair (UTP) cable.

The KSZ8091RNA is a highly-integrated PHY solution. It

reduces board cost and simplifies board layout by using

on-chip termination resistors for the differential pairs and

by integrating a low-noise regulator to supply the 1.2V

core, and by offering a flexible 1.8/2.5/3.3V digital I/O

interface.

The KSZ809 1RNA offer s the Reduced Media Inde pendent

Interface (RMII) for direct connection with RMII-compliant

Ethernet MAC processors and switches.

As the po wer-up default, the KSZ 8091RNA uses a 25MHz

crystal to generate all required clocks, including the

50MHz RMII reference clock output for the MAC. The

KSZ8091 RND tak es in the 50MHz RMI I ref erence c lock as

the power-up default.

Energy Efficient Ethernet (EEE) provides further power

saving d urin g idl e traf fic periods a nd Wake-On-LAN (WOL)

provides a m echanism for the KSZ8091RNA to wake up a

system that is in standby power mode.

The KSZ8091RNA and KSZ8091RND are available in 24-

pin, lead-free QFN packages (see Ordering Information).

Datasheets and support documentation are available on

website at: www.micrel.com.

Features

• Single-chip 10Base-T/100Base-TX IEEE 802.3

compliant Ethernet transceiver

• RMII v1.2 interface support with a 50MHz reference

clock output to MAC, and an option to input a 50MHz

reference clock

• RMII back-to-back mode support for a 100Mbps copper

repeater

• MDC/MDIO management interface for PHY register

configuration

• Programmable interrupt output

• LED outputs for link and activity status indication

• On-chip termination resistors for the differential pairs

• Baseline wander correction

• HP Auto MDI/MDI-X to reliably detect and correct

straight-through and crossover cable connections with

disable and en able opt ion

• Auto-Negotiation to automatically select the highest link-

up speed (10/100Mbps) and duplex (half/full)

• Energy Efficient Ethernet (EEE) support with low-power

idle (LPI) mode for 100Base TX and transmit amplitude

reduction w ith 10 Base-Te option

• Wake-On-LAN (WOL) support with either magic packet,

link status change, or robust custom-packet detection

• LinkMD® TDR-based cable diagnostics to identify faulty

copper cabling

• HBM ESD rating (6kV)

Functional Diagram

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 2 Revision 1.2

Features (Continued)

• Parametric NAND Tree support for fault detection

between chip I/Os and the board

• Loopback modes for diagnostics

• Power-down and power-saving modes

• Single 3.3V power supply with VDD I/O options for 1.8V,

2.5V, or 3.3V

• Built-in 1.2V regulator for core

• Available in 24-pin (4mm × 4mm) QFN package

Applications

• Game console

• IP phone

• IP set-top box

• IP TV

• LOM

• Printer

Ordering Information

Ordering Pa rt Number Temperature

Range Package Lead

Finish Description

KSZ8091RNACA 0°C to 70°C 24-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz

RMII REF_CLK output, EEE and WoL Support,

Commercial Temperature.

KSZ8091RNAIA(1) −40°C to 85°C 24-Pin QF N Pb-Free RMII with 25MHz crystal/clock input and 50MHz

RMII REF_CLK output, EEE and WoL Support,

Industrial Temperature.

KSZ8091RNDCA 0°C to 70°C 24-Pin QFN Pb-Free RMII normal mode with 50MHz clock input, EEE

and WoL Support, Commercial Temperature.

KSZ8091RNDIA(1) −40°C to 85°C 24-P in QFN Pb-Free RMII normal mode with 50MHz clock input, EEE

and WoL Support, Industrial Temperature.

KSZ8091RNA-EVAL KSZ8091RNA Evaluation Board

(Mount ed with KSZ8081R NA dev ice in

commercial temperature)

KSZ8091RND-EVAL KSZ8091RND Evaluation Board

(Mounted with KSZ8091RN D dev ice in

commercial temperature)

Note:

1. Contact factory for lead time.

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 3 Revision 1.2

Revision History

Date Change Description/Edits by: Rev.

9/24/13 New datasheet. 1.0

12/2/14 Added silver wire bonding part numbers to Order ing Informati on.

Updated Ordering Information to include Ordering Part Number and Device Marking. 1.1

8/31/15 Add Max frequency for MDC in MII Management (MIIM) Interface section.

Updated ordering information Table.

Updated descriptions for Figure 19.

Add a note for Figure 20.

Updated descriptions in local loopback section for data loopback path.

Updated Table 16.

Add a note for Table 18.

Updated description and add an equation in LinkMD section.

Add HBM ESD rating in Features.

1.2

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 4 Revision 1.2

Contents

List of Figures .......................................................................................................................................................................... 6

List of Tables ........................................................................................................................................................................... 7

Pin Configuration ..................................................................................................................................................................... 8

Pin Description ........................................................................................................................................................................ 9

Strapping Options ................................................................................................................................................................. 12

Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 13

100Base-TX Transmit ........................................................................................................................................................ 13

100Base-TX Receive ......................................................................................................................................................... 13

Scrambler/De-Scrambler (100Base-TX Only) ................................................................................................................... 13

10Base-T Transmit ............................................................................................................................................................ 14

10Base-T Receive ............................................................................................................................................................. 14

PLL Clock Synthesizer ...................................................................................................................................................... 14

Auto-Negotiation ................................................................................................................................................................ 14

RMII Data Interface ............................................................................................................................................................... 16

RMII Signal Definition ........................................................................................................................................................ 16

Reference Clock (REF_CLK) ......................................................................................................................................... 16

Transmit Enable (TXEN) ................................................................................................................................................ 16

Transmit Data[1:0] (TXD[1:0]) ........................................................................................................................................ 16

Carrier Sense/Receive Data Valid (CRS_DV) ............................................................................................................... 17

Receive Data[1:0] (RXD[1:0]) ........................................................................................................................................ 17

Receive Error (RXER) .................................................................................................................................................... 17

Collision Detection (COL) .............................................................................................................................................. 17

RMII Signal Diagram – 25/50MHz Clock Mode ................................................................................................................. 17

RMII – 25MHz Clock Mode ............................................................................................................................................ 17

RMII – 50MHz Clock Mode ............................................................................................................................................ 18

Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 19

RMII Back -to-Back Mode ................................................................................................................................................... 19

MII Management (MIIM) Interface ......................................................................................................................................... 20

Interrupt (INTRP) ................................................................................................................................................................... 20

HP Auto MDI/MDI-X .............................................................................................................................................................. 21

Straight Cab le .................................................................................................................................................................... 21

Crossover Cable ................................................................................................................................................................ 22

Loopback Mode ..................................................................................................................................................................... 22

Local (Digital) Loopback .................................................................................................................................................... 22

Remote (Analog) Loopback ............................................................................................................................................... 23

LinkMD® Cab le Di agn os tic .................................................................................................................................................... 25

NAND Tree Support .............................................................................................................................................................. 26

NAND Tree I/O Testing ..................................................................................................................................................... 27

Power Management .............................................................................................................................................................. 28

Power-Saving Mode .......................................................................................................................................................... 28

Energy-Detect Power-Down Mode .................................................................................................................................... 28

Power-D o wn Mode ............................................................................................................................................................ 28

Slow-Oscillator Mode ......................................................................................................................................................... 28

Energ y Efficient Ethernet (EEE) ............................................................................................................................................ 29

Transmit Direction Control (MAC-to-PHY) ........................................................................................................................ 30

Receive Direction Control (PHY-to-MAC) ......................................................................................................................... 30

Register s Ass ociate d w ith EEE ......................................................................................................................................... 30

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KSZ8091RNA/KSZ8091RND

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31, 2015 5 Revision 1.2

Wake-On-LAN ....................................................................................................................................................................... 31

Magic-Packet Detection ..................................................................................................................................................... 31

Customized-Packet Detection ........................................................................................................................................... 32

Link Status Change Detection ........................................................................................................................................... 32

Reference Circuit for Power and Ground Connections ......................................................................................................... 33

Typical Current/Power Consumption .................................................................................................................................... 34

Register Map ......................................................................................................................................................................... 36

Standard Reg is ters ............................................................................................................................................................... 38

IEEE-Defined Registers – Descriptions ............................................................................................................................. 38

Vendor-Specific Registers – Descriptions ......................................................................................................................... 43

MMD Registers...................................................................................................................................................................... 48

MMD Register Write .......................................................................................................................................................... 49

MMD Register Read .......................................................................................................................................................... 49

MMD Registers – Descriptions .......................................................................................................................................... 50

Absolute Maximum Ratings .................................................................................................................................................. 55

Operating Ratings ................................................................................................................................................................. 55

Electrical Characteristics ....................................................................................................................................................... 55

Timing Diagrams ................................................................................................................................................................... 57

RMII Timing ....................................................................................................................................................................... 57

Auto-Negotiation Timing .................................................................................................................................................... 58

MDC/MDIO Timing ............................................................................................................................................................ 59

Power-Up/Reset Timing .................................................................................................................................................... 60

Reset Circuit .......................................................................................................................................................................... 61

Reference Circuits – LED Str ap-I n Pin ................................................................................................................................. 62

Reference Clock – Connection and Selection ...................................................................................................................... 63

Magnetic – Connection and Selection .................................................................................................................................. 64

Package Information and Recommended Land Pattern ....................................................................................................... 66

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 6 Revision 1.2

List of Figures

Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................ 15

Figure 2. KSZ8091RNA/RND RMII Interface (RMII – 25MHz Clock Mode) ....................................................................... 18

Figure 3. KSZ8091RNA/RND RMII Interface (RMII – 50MHz Clock Mode) ....................................................................... 18

Figure 4. KSZ8091RNA/RND to KSZ8091RNA/RND Back-to-Back Copper Repeater ...................................................... 19

Figure 5. T ypical Stra ig ht Cabl e Co nnect io n ...................................................................................................................... 21

Figure 6. Typical Crossover Cable Connection .................................................................................................................. 22

Figure 7. Local (Digital) Loopback ...................................................................................................................................... 23

Figure 8. Remote (Analog) Loopback ................................................................................................................................. 24

Figure 9. LPI Mode (Refresh Transmissions and Quiet Periods) ....................................................................................... 29

Figure 10. LPI T rans itio n – RMII (100Mbps) Transmit .......................................................................................................... 30

Figure 11. LPI T rans itio n – RMII (100Mbps) Receive ........................................................................................................... 30

Figure 12. KSZ8091RNA/RND Power and Ground Connections ......................................................................................... 33

Figure 13. RMII Timing – Data Received from RMII ............................................................................................................. 57

Figure 14. RMII Timing – Data Input to RMII ........................................................................................................................ 57

Figure 15. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 58

Figure 16. MDC/ MDIO Timing ............................................................................................................................................... 59

Figure 17. Power -Up/Reset Timing ....................................................................................................................................... 60

Figure 18. Recom mended Reset Cir c uit ............................................................................................................................... 61

Figure 19. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 61

Figure 20. Reference Circuits for LED Strapping Pin ........................................................................................................... 62

Figure 21. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 63

Figure 22. 50MHz Oscillator/Reference Clock Connection .................................................................................................. 63

Figure 23. Typical Magnetic Interface Circuit ........................................................................................................................ 64

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 7 Revision 1.2

List of Tables

Table 1. RMII Signal Definition............................................................................................................................................ 16

Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ..................................... 19

Table 3. MII Management Frame Format for the KSZ8091RNA/RND ............................................................................... 20

Table 4. MDI/MDI-X Pin Definition ...................................................................................................................................... 21

Table 5. NAND Tree Test Pin Order for KSZ8091RNA/RND ............................................................................................. 26

Table 6. KSZ8091RNA/RND Power Pin Description .......................................................................................................... 33

Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) ........................................................... 34

Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V) ........................................................... 34

Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) ........................................................... 35

Table 10. Standard Registers Supported by KSZ8091RNA/RND ........................................................................................ 36

Table 11. MMD Registers Supported by KSZ8091RNA/RND .............................................................................................. 37

Table 12. Portal Registers (Access to Indirect MMD Registers) ........................................................................................... 48

Table 13. RMII Timing Parameters – KSZ8091RNA/RND (25MHz input to XI pin, 50MHz output from REF_CLK pin) ..... 57

Table 14. RMII Timing Parameters – KSZ8091RNA/RND (50MHz input to XI pin) ............................................................. 57

Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................ 58

Table 16. MDC/MDIO Timing Parameters ............................................................................................................................ 59

Table 17. Power-Up/Reset Timing Parameters .................................................................................................................... 60

Table 18. 25MHz Crystal/Reference Clock Selection Criteria .............................................................................................. 63

Table 19. 50MHz Oscillator/Reference Clock Selection Criteria .......................................................................................... 63

Table 20. Magnetics Selection Criteria ................................................................................................................................. 65

Table 21. Compatible Single-Port 10/100 Magnetics ........................................................................................................... 65

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 8 Revision 1.2

Pin Configuration

24-Pin (4mm × 4mm) QFN

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 9 Revision 1.2

Pin Description

Pin Number Pin Name Type

(2)

Pin Function

1 VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8091RNA/KSZ8091RND). Decouple with

2.2µF and 0.1µF capacitors to ground.

2 VDDA_3.3 P 3.3V analog VDD.

3 RXM I/O Physical receive or transmit si gnal ( – differential).

4 RXP I/O Physical receive or transmit signal (+ differential).

5 TXM I/O Physical trans mit or receiv e si gnal (– differential).

6 TXP I/O Physical transmit or receive signal (+ differential).

7 XO O Crystal Feedback for 25MHz Crystal. This pin is a no connect if an oscillator or

external clock source is used.

8 XI I

RMII – 25MHz Mode: 25MHz ±50ppm Crystal/Oscillator/External Clock Input

RMII – 50MHz Mode: 50MHz ±50ppm Oscillator/External Clock Inpu t

For unmanaged mode (power-up default setting),

• KSZ8091RNA takes in the 25MHz crystal/clock on this pin.

• KSZ8091RND takes in the 50MHz clock on this pin.

After power-up, both the KSZ8091RNA and KSZ8091RND can be programmed to

either the 25MHz mode or 50MHz mode using PHY Register 1Fh, Bit [7].

See also XI (Pin 8).

17 RXER /

PME_EN Ipd/O RMII Mode: RMII Receive Error Output

Config Mode: The pull-up/pull-down value is latched as PME_EN at the de-assertion of

reset. See the Strapping Options s ect ion f or detai ls.

18 INTRP/

PME_N2 Ipu/Opu

Interrupt Output: Programmable interrupt output, with Register 1Bh as the Interrupt

Control/Status register, for programming the interrupt conditions and reading the

interrupt status. Register 1Fh, Bit [9] sets the interrupt output to active low (default) or

active high.

PME_N Output: Programmable PME_N output (pin option 2). When asserted low, this

pin signals that a WOL event has occurred.

This pin has a weak pull-up an d is an open-drain.

For Interrupt (when active low) and PME functions, this pin requires an external 1.0kΩ

pull-up resistor to VDDIO (digital VDD).

19 TXEN I RMII Transmit Enable Input

20 TXD0 I RMII Transmit Data Input[0](4)

21 TXD1 I/O RMII Mode: RMII Transmit Data Input[1](4)

NAND Tree Mode: NAND Tree Output

22 GND GND Ground

Note:

4. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits

of data are received by the PHY from the MAC.

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 11 Revision 1.2

Pin Description (Continued)

Pin Number Pin Name Type

(2)

Pin Function

23 LED0/

PME_N1/

ANEN_SPEED Ipu/O

LED Output: Programmable LED0 output

PME_N Output: Programmable PME_N Output (pin option 1). When asserted low, this

pin signals that a WOL event has occurred. In this mode, this pin has a weak pull-up, is

an open-drain, and requires an external 1.0kΩ pull-up resistor to VDDIO (digital VDD).

Config Mode: Latched as Auto -Negotiation enable (Register 0h, Bit [12]) and Speed

(Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping Options section for

details.

The LED0 pin is programmable using Register 1Fh, Bits [5:4], and is defined as follows.

LED Mode = [00]

Link/Activity Pin State LED Definition

No link High OFF

Link Low ON

Activity Toggle Blinking

LED Mode = [01]

Link Pin State LED Definition

No link High OFF

Link Low ON

LED Mode = [10], [11] Reserved

24 RST# Ipu Chip Reset (activ e low)

PADDLE GND GND Ground

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 12 Revision 1.2

Strapping Options

Pin Number Pin Name Type

(

)

Pin Function

15 PHYAD[1:0] Ipd/O

The PHY Address is latched at the de-

assertion of reset and i s confi gurab le t o either one

of the following two values:

Pull-up = PHY Address is set to 00011b (3h)

Pull-down (default) = PHY Address is set to 00000b (0h)

PHY Address 0 is assigned by default as the broadcast PHY address, but it can be

assigned as a unique PHY address after writing a ‘1’ to Register 16h, Bit [9].

PHY Address bits [4:2] are set to 000 by default.

17 PME_EN Ipd/O

PME Output for Wake-On-LAN

Pull-up = Enable

Pull-down (default) = Disable

At the de-assertion of reset, this pin value is latched into Register 16h, Bit [15].

23 ANEN_SPEED Ipu/O

Auto-Negotiation Enable and Speed Mode

Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed

Pull-down = Disable Auto-Neg otiation and set 10Mbps Spee d

At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12] for Auto-

Negotiation enable/disable, Register 0h, Bit [13] for the Speed select, and Register 4h

(Auto-Negotiation Advertisement) for the Speed capability support.

Note:

5. Ipu/O = Input with internal pull -up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.

The PHYAD[1:0] and PME_EN strap-in pins are latched at the de-assertion of reset. In some systems, the RMII MAC

receive input pins may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] and PME_EN

strap-in pins , shared pin wi th the R MII CRS_DV and R XER signa ls respect ivel y, to be latch ed to t he uninte nded h igh/low

state. In this case an external pull-up (4.7kΩ) or pull-down (1.0kΩ) should be added on the PHYAD[1:0] and PME_EN

strap-in pins to ensure that the intended value is strapped-in correctly.

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 13 Revision 1.2

Functional Description: 10Base-T/100Base-TX Transcei ver

The KSZ8091RNA is an integrated single 3.3V suppl y Fast Ethernet transceiver. It is fully com pliant with the IEEE 802.3

Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two

differential pairs and by integrating the regulator to supply the 1.2V core.

On the cop per media s ide, the KSZ8 091RNA sup ports 10B ase-T and 100 Base-TX for tr ansmission and rec eption of dat a

over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and

correction for straight-through and crossover cables.

On the MAC processor side, the KSZ8091RNA offers the Reduced Media Independent Interface (RMII) for direct

connection with RMII-compli ant Ethernet MAC processors and switches

The MII management bus option gives the MAC processor complete access to the KSZ8091RNA control and status

registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.

As the power-up default, the KSZ8091RNA uses a 25MHz crystal to generate all required clocks, including the 50MHz

RMII refer ence clock outp ut f or the MAC. T he KSZ809 1RND version uses the 5 0MH z RMII r efer ence c lock as the pow er-

up default.

The KSZ8091RNA/RND is used to refer to both KSZ8091RNA and KSZ8091RND versions in this datasheet.

100Base-TX Transmit

The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI

conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the RM II data from the MAC into a 125MHz serial

bit stream . The data and c ontrol stream is then converted into 4B/5B coding and followed by a scram bler. The serialized

data is fur ther convert ed fr om NR Z-to-NRZI f orm at, and then trans m itted in MLT3 c urrent outpu t. T he outpu t current is set

by an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX

transmitter.

100Base-TX Receive

The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The rec eiving s ide starts with the eq ualization filter to compensate for inter-symbol interf erence (ISI) over the tw isted pair

cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

compar isons of incom ing si gnal str ength a gains t som e k nown cable charac ter istic s, then tunes itse lf f or optim ization. This

is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit

compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit

converts MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used

to convert t he NRZI signal to NRZ format. T his signal is sent through the de-scram bler, then the 4B/5B decoder. Finally,

the NRZ serial data is converted to RMII format and provided as the input data to the MAC.

Scrambler/De-Scr amb le r ( 100Ba se-TX Only)

The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and

baseline wander. The de-scrambler recovers the scrambled signal.

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KSZ8091RNA/KSZ8091RND

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31, 2015 14 Revision 1.2

10Base-T Transmit

The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.

The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of

2.5V peak f or standard 10Base-T mode and 1.75 V peak for energ y-eff icient 10Base-Te m ode. The 10B ase-T/10Base-Te

signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones

Manchester-encoded signal.

10Base-T Receive

On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A sq uelch circuit rejects sig nals with le vels less than 400mV, or with short p ulse widths , to prevent

noise at the differential line receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit,

the PLL locks onto the incoming signal and the KSZ8091RNA/RND decodes a data frame. The receive clock is kept

active during idle periods between data receptions.

PLL Clock Synthesizer

The KSZ8091RNA/RND in RMII – 25MHz Clock mode generates all internal clocks and all external clocks for system

timing from an external 25MHz crystal, oscillator, or reference clock. For the KSZ8091RNA/RND in RMII – 50MHz clock

mode, these clocks are generated from an external 50MHz oscillator or system clock.

Auto-Negotiation

The KSZ8091RNA/RND conforms to the Auto-Negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.

Auto-Negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.

During Auto-Negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own

capabil ities with those the y received from their link partners . The highest speed a nd duplex setting th at is common to the

two link partners is selected as the mode of operation.

The following list shows the speed and duplex operation mode from highest to lowest priority.

• Priorit y 1: 100Base-TX, full-duplex

• Priorit y 2: 100Base-TX, half-duplex

• Priorit y 3: 10Base-T, full-duplex

• Priorit y 4: 10Base-T, half-duplex

If Auto-Negotiation is not s upported or t he KSZ8091RNA/RND link partner is f orced to b ypass Auto-Negotiation, then the

KSZ8091RNA/RND sets its operating mode by observing the signal at its receiver. This is known as parallel detection,

which allows the KSZ8091RNA/RND to establ ish a link b y list ening for a f ixed signal protocol in the abs ence of the Auto-

Negotiation advertisement protocol.

Auto-Negotiation is enabled by either hardware pin strapping (ANEN_SPEED, Pin 23) or software (Register 0h, Bit [12]).

By default, Auto-Negotiation is enabled after power-up or hardware reset. After that, Auto-Negotiation can be enab led or

disabled by Reg ister 0h, Bi t [12]. If Auto-Ne gotiation is disabled, the sp eed is set b y Regist er 0h, Bit [13], an d the duplex

is set by Register 0h, Bit [8].

The Auto-Negotiation link-up process is shown in Figure 1.

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 15 Revision 1.2

Figure 1. Auto-Negotiation Flo w Chart

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 16 Revision 1.2

RMII Data Interface

The Reduc ed Medi a Indep endent Int erf ace (RMI I) spec ifies a lo w pin count M edia Inde pen dent Inter face ( MII). It prov ides

a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock).

• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each 2 bits wide, a dibit.

RMII Signal Definition

Table 1 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.

Table 1. RMII Signal Definition

RMII Signal

Name

Direction

(with respect to PHY,

KSZ8091RNA/RND signal)

Direction

(with respect to MAC) Description

REF_CLK Output (25MHz clock mode)/

<no connect> (50MH z clock mode) Input/

Input or <no connect> Synchronous 50MHz reference clock for receive,

transmit, and control interface

TXEN Input Output Transm it Enable

TXD[1:0] Input Output Transmit Data[1:0]

CRS_DV Output Input Carrier Sense/Receive Data Valid

RXD[1:0] Output Input Receive Data[1:0]

RXER Output Input, or (not required) Receive Error

Reference Clock (REF_CLK)

REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and

RX_ER.

For RMII – 25MHz Cl ock Mode, the KSZ809 1RN A/RN D generat es and outp uts the 50 MH z RMII REF _CL K to the MAC at

REF_CLK (Pin 16).

For RMII – 50MHz Clock Mode, the KSZ8091RNA/RND takes in the 50MHz RMII REF_CLK from the MAC or system

board at XI (Pin 8) and leaves the REF_CLK (Pin 16) as no connect.

Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted s ynchronousl y with the first

dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated

before the first REF_CLK following the final dibit of a frame.

TXEN transitions synchronously with respect to REF_CLK.

Transmit Data[1:0] (TXD[1:0])

When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission.

When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI

state (EEE mode).

TXD[1:0] transitions synchronously with respect to REF_CLK.

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Carrier Sen se/Receive Data Valid (CRS_DV)

The PH Y asser ts CRS_ DV when the receive medium is non-id le. It is ass er ted asynchronous ly when a carr ie r is detect ed.

This happens when squelch is passed in 10Mbps mode, and when two non-contiguous 0s in 10 bits are detected in

100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.

While carr ier detect ion cri teria ar e m et, CR S_DV rem ai ns ass erted con tinuo usl y from the f irst recovered dibit of the fr ame

through the f ina l rec ov ered dibit. It is ne gat ed bef or e th e f ir st REF_CLK th at follows the f inal di bit. T he data o n R XD [1:0] is

considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to

REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.

Receive Data[1:0] (RXD[1:0])

For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY.

W hen CRS_ DV is de-asser ted, the P HY drives R XD[1:0] to e ither 00 for the idle s tate (non-EEE mode) or 01 for the LPI

state (EEE mode).

RXD[1:0] transitions synchronously with respect to REF_CLK.

Receive Error (RXER)

When CRS_DV is asserted, RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for

example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected

somewhere in the frame that is being transferred from the PHY to the MAC.

RXER transitions synchronously with respect to REF_CLK.

Collision Detection (COL)

The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.

RMII Signal Diagram – 25/50MHz Clock Mode

The KSZ8091RNA/RND RMII pin conn ectio ns to the MAC for 25MHz cl ock mode are s hown in Fi gure 2 . The conn ectio ns

for 50MHz clock mode are shown in Figur e 3.

RMII – 25MHz Clock Mode

The KSZ8091RNA is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:

• A 25MHz crystal connected to XI, XO (Pins 8, 7), or an external 25MHz clock source (oscillator) connected to XI

The KSZ80 91RN D can optionally be configured to RMI I – 25MHz c lock mode af ter it is po wer ed up or hardwar e res et and

software programmed with the following:

• A 25MHz crystal connected to XI, XO (Pins 8, 7), or an external 25MHz clock source (oscillator) connected to XI

• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 25MHz clock mode

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Figure 2. KSZ8091RNA/RND RMII Interface (RMII – 25MH z Clock Mode)

RMII – 50MHz Clock Mode

The KSZ8091RND is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:

• An external 50MHz clock source (oscillator) connected to XI (Pin 8)

The KSZ 8 091RNA can o pti ona lly be config ur ed t o R MI I – 50MHz cl oc k mode after it is powered up or hardware r eset an d

software programmed with the following:

• An external 50MHz clock source (oscillator) connected to XI (Pin 8)

• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50MHz clock mode

Figure 3. KSZ8091RNA/RND RMII Interface (RMII – 50MHz Clock Mode)

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Back-to-Back Mode – 100Mbps Copper Repeater

Two KSZ8091RNA/RND devices can be connected back-to-back to form a managed 100Base-TX copper repeater.

Figure 4. KSZ8091RNA/RND to KSZ8091RNA/RND Back-to-Back Copper Repeater

RMII Back-to-Back Mode

In RMII back-to-back mode, a KSZ8091RNA/RND interfaces with another KSZ8091RNA/RND to provide a 100Mbps

copper repeater solution.

The KSZ8091RNA/RND devices are configured to RMII back-to-back mode after power-up or reset, and software

programming, with the following:

• A common 50MHz reference clock connected to XI (Pin 8) of both KSZ8091RNA/RND devices.

• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50MHz clock mode for KSZ8091RNA.

(KSZ8091RND is set to RMII – 50MHz clock mode as the default after power up or hardware reset).

• Register 16h, Bits [6] and [1] programmed to ‘1’ and ‘1’, respectively, to enable RMII back-to-back mode.

• RMII signals connected as shown in Table 2.

Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)

KSZ8091RNA/RND (100Base-TX copper)

[Device 1] KSZ8091RNA/RND (100Base-TX copper)

[Device 2]

Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type

CRSDV 15 Output TXEN 19 Input

RXD1 12 Output TXD1 21 Input

RXD0 13 Output TXD0 20 Input

TXEN 19 Input CRSDV 15 Output

TXD1 21 Input RXD1 12 Output

TXD0 20 Input RXD0 13 Output

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MII Management (MIIM) Interface

The KSZ8091RNA/RND supports the IEEE 802.3 MII management interface, also known as the Management Data

Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and

control t he state of the KSZ8091 RNA/R ND. An ex ter nal device wit h MIIM c apabili ty is us ed to r ead th e PHY s tatus an d/or

configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3

Specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the phy sical connection mentioned earlier, which allows the external controller

to communicate with one or more PHY devices.

• A 32-regis ter address space f or direct acc ess to IEEE -defined re gisters and v endor-s pecific regis ters, and fo r indirect

access to MMD addresses and registers. See the Reg is ter Map section.

The KSZ80 91RNA/RN D support s only two u nique PH Y address es. The PH YAD[1:0] str apping p in is used t o select eith er

0h or 3h as the unique PHY address for the KSZ8091RNA/RND device.

PHY Addr ess 0h is def ined as the broadcas t PH Y add ress accor ding to the IEEE 802. 3 Specif ication, and can be used t o

read/write to a single PHY device, or write to multiple PHY devices simultaneously. For the KSZ8091RNA/RND, PHY

Address 0 h d ef aults t o th e broadcas t PH Y a ddres s af ter po wer -up, but PH Y A ddress 0h c an be disa ble d as t he br o adc ast

PHY address using software to assign it as a unique PHY address.

For applications that require two KSZ8091RNA/RND PHYs to share the same MDIO interface with one PHY set to

Address 0h an d the other PHY set to Addres s 3h, use PH Y Address 0h (def aults to broadcast af ter power -up) to set both

PHYs’ Register 16h, Bit [9] to ‘1’ to assign PHY Address 0h as a unique (non-broadcast) PHY address.

The MIIM interface can operates up to a maximum clock speed of 10MHz MAC clock.

Table 3 shows the MII management frame format for the KSZ8091RNA/RND.

Table 3. MII Management Frame Format for the KSZ8091RNA/RND

Preamble Start of

Frame

Read/Write

OP Code

PHY Address

Bits [4:0]

REG Address

Bits [4:0]

TA Data

Bits [15:0]

Idle

Read 32 1’s 01 10 000AA RRRRR Z0 DDDDDDDD_DDDDDDDD Z

Write 32 1’s 01 01 000AA RRRRR 10 DDDDDDDD_DDDDDDDD Z

Interrupt (INTRP)

INTRP (Pin 18) is an optional interrupt signal that is used to inform the external controller that there has been a status

update to the KSZ8091RNA/RND PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and

disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate

which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.

Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.

The MII m anagement bus option gives the MAC proces sor com plete access to the KSZ8091RNA/RND c ontrol and stat us

registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.

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HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable

between the KSZ8091RNA/RND and its link partner. This feature allows the KSZ8091RNA/RND to use either type of

cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and

receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8091RNA/RND accordingly.

HP Auto MD I/MDI-X is ena bled b y def ault. It is disab led by wri ting a ‘1’ t o Registe r 1Fh, Bit [13]. MDI and MDI-X m ode is

selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.

An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.

Table 4 shows how the IEEE 802.3 Standar d def ines MDI and MDI-X.

Table 4. MDI/MDI-X Pin Definition

MDI MDI-X

RJ-45 Pin

Signal

RJ-45 Pin

Signal

1 TX+ 1 RX+

2 TX− 2 RX−

3 RX+ 3 TX+

6 RX− 6 TX−

Straight Cable

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 5 shows a

typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).

Figure 5. Typical Straight Cable Connection

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Crossover C able

A cross over cable conn ects an MDI de vice to anoth er MDI device, or an MDI -X device to an other MDI -X devic e. Figure 6

shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

Figure 6. Typical Crossover Cable Connection

Loopback Mode

The KSZ8091RNA/RND supports the following loopback operations to verify analog and/or digital data paths.

• Local (digital) loopback

• Remote (analog) loopback

Local (Di gital) Loopback

This loopback mode checks the RMII transmit and receive data paths between the KSZ8091RNA/RND and the external

MAC, and is supported for both speeds (10/100Mbps) at full-duplex.

The loopback data path is shown in Figure 7.

1. The RMII MAC transmits frames to the KSZ8091RNA/RND.

2. Frames are wrapped around inside the KSZ8091RNA/RND.

3. The KSZ8091RNA/RND transmits frames back to the RMII MAC.

4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.

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Figure 7. Local (Digital) Loopback

The following programming action and register settings are used for local loopback mode.

For 10/100Mbps loopbac k,

Set Register 0h,

Bit [14] = 1 // Enable local loopback mode

Bit [13] = 0/1 // Select 10Mbps/1 00Mbps speed

Bit [12] = 0 // Disable Auto-Negotiation

Bit [8] = 1 // Select full-duplex mode

Remote (Ana log) Loopback

This loopb ack m ode checks the li ne (diff erenti al pairs , trans form er , RJ-45 c onnector, Eth ernet c able) tr ansm it and rece ive

data paths between the KSZ8091RNA/RND and its link partner, and is supported for 100Base-TX full-duplex mode only.

The loopback data path is shown in Figure 8.

1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8091RNA/RND.

2. Frames are wrapped around inside the KSZ8091RNA/RND.

3. The KSZ8091RNA/RND transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.

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Figure 8. Remote (Analog) Loopback

The following programming steps and register settings are used for remote loopback mode.

1. Set Register 0h,

Bit [13] = 1 // Select 100Mbps speed

Bit [12] = 0 // Disable Auto-Negotiation

Bit [8] = 1 // Select full-duplex mode

Or just auto-negotiate and link up with the link partner at 100Base-TX full-duplex mode.

2. Set Register 1Fh,

Bit [2] = 1 // Enable remote loopback mode

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LinkMD® Cable Diagnostic

The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.

These include open circuits, short circuits, and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape

of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the

approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a

numerical value that can be translated to a cable distance.

LinkMD is initiated by accessing Register 1Dh, the LinkMD Cable Diagnostic Register, in conjunction with Register 1Fh,

the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as

the cable differential pair for testing.

Usage

The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:

3. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].

4. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.

5. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.

6. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:

00 = normal condition (valid test)

01 = open condition detected in cable (valid test)

10 = short condition detected in cable (valid test)

11 = cable diagnostic test failed (invalid tes t)

The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is

not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal

generated or a signal from another source.

7. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The

distance to the cable fault can be determined by the following formula:

D (distance to cable fault) = 0.38 x (Register 1Dh, bits [8:0])

D (distance to cable fault) is expressed in meters.

Concatenated value of Registers 1Dh bits [8:0] shou ld be converted to decimal before multiplying by 0.38.

The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation

that varies significantly from the norm.

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NAND Tree Support

The KSZ8091RNA/RND provides parametric NAND tree support for fault detection between chip I/Os and board. The

NAND tree is a chain of nested NAND gates in which each KSZ8091RNA/RND digital I/O (NAND tree input) pin is an

input to on e NAND gat e along the ch ain. At the end of the c hain, the TX D1 pin provides the output f or the nested N AND

gates.

The NAND tree test process includes:

• Enabling NAND tree mode

• Pulling all NAND tree input pins high

• Driving each NAN D tree in put pin lo w, sequ ent ia ll y, accor ding to the NAND tree pi n order

• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input

driven low

Table 5 lists the NAND tree pin order

Table 5. NAND Tree Test Pin Order for KSZ 8091RNA/RND

Pin Number Pin Name NAND Tree Description

10 MDIO Input

11 MDC Input

12 RXD1 Input

13 RXD0 Input

15 CRS_DV Input

16 REF_CLK Input

18 INTRP Input

19 TXEN Input

23 LED0 Input

20 TXD0 Input

21 TXD1 Output

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NAND Tree I/O Testing

Use the following procedure to check for faults on the KSZ8091RNA/RND digital I/O pin connections to the board:

1. Enable NAND tree mode by setting Register 16h, Bit [5] to ‘1’.

2. Use board logic to drive all KSZ8091RNA/RND NAND tree input pins high.

3. Use board logic to drive each NAND tree input pin, in KSZ8091RNA/RND NAND tree pin order, as follows:

a. Toggle the f irs t pin (MD IO) f r om high to low , and ver ify that the TXD1 pin switches f r om high to lo w to ind icate t hat

the first pin is connected properly.

b. Leave the first pin (MDIO) low.

c. Toggle the s econd p in (MDC) from high to low, a nd verif y that the TXD1 pin switches f rom low to high to i ndicate

that the second pin is connected properly.

d. Leave the first pin (MDIO) and the second pin (MDC) low.

e. Toggle the third pin (RXD1) from high to low, and verify that the TXD1 pin switches from high to low to indicate

that the third pin is connected properly.

f. Continue with this sequence until all KSZ8091RNA/RND N AND tree input pins ha ve bee n toggl ed.

Each KSZ8091RNA/RND NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to

indicate a good c on nec ti on. If the TXD1 pin f ails to to g gle when the KSZ8091RNA/RND input pi n tog gl es f r om high to low ,

the input pin has a fault.

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Power Management

The KSZ8091RNA/RND incorporates a number of power-management modes and features that provide methods to

consume less energy. These are discussed in the following sections.

Power-Saving Mode

Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by

writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when Auto-Negotiation mode is enabled and the cable is

disconnected (no link).

In this mode, the KSZ 8091RNA/RND shuts d o wn all transcei ver b loc k s , ex c ept f or the trans mitter, en ergy detect, an d P LL

circuits.

By default, power-saving mode is disabled after power-up.

Energy-Detect Pow er-Down Mode

Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is

unplugged. It is enab led by writing a ‘0’ to Regis ter 18h, Bit [11], and is in ef fect when Auto-Negotiat ion mode is ena bled

and the cable is disconnected (no link).

EDPD m ode works with t he PLL off (set by writin g a ‘1’ to Regis ter 10h, Bit [4] to autom atically turn t he PLL off in EDPD

mode) to turn off all KSZ8091RNA/RND transcei ver bl oc k s except the transmitter and energy-d etect circu its.

Power can be reduced further by extending the time interval between transmissions of link pulses to check for the

presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091RNA/RND and its

link partner , whe n op er ati n g in t he s ame low-power s t ate a nd with Aut o MD I/ MDI-X disabled, can w ak e up when the cable

is connected between them.

By default, EDPD mode is disabled after power-up.

Power-Down Mode

Power-down mode is used to power down the KSZ8091RNA/RND device when it is not in use after power-up. It is

enabled by writing a ‘1’ to Register 0h, Bit [11].

In this mode, the KSZ8091RNA/RND disables all internal functions except the MII management interface. The

KSZ8091RNA/RND exits (disables) power-down mode after Register 0h, B it [11] is set back to ‘0’.

Slow-Oscil lator Mode

Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 8) and select the on-chip slow

oscillator when the KSZ8091RNA/RND device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,

Bit [5].

Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091RNA/RND device in the lowest

power state, with all internal functions disabled except the MII management interface. To properly exit this mode and

return to normal PHY operation, use the following programming sequence:

1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].

2. Disable power-do wn mode b y writing a ‘0’ to Regist er 0h, Bit [11] .

3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].

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Energy Efficient Ethernet (EEE)

The KSZ8091RNA/RND implements Energy Efficient Ethernet (EEE) as described in the IEEE Standard 802.3az for

100Base-TX copper signaling by the two differential pairs (analog side) and according to the multisource agreement

(MSA) of collaborating Fast Ethernet chip vendors for the RMII (digital side). The MSA agreement is based on the IEEE

Standard’s EEE implementation for the 100Mbps Media Independent Interface (MII). The IEEE Standard is defined

around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support special

signaling ass ociated with E EE. EEE sav es power by keep ing the AC si gna l on t h e c opper Et her n et c abl e at appr oximatel y

0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up status. This is

referred to as low-power idle (LPI) mode or state.

During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation

imm ediately, without b lockage of tr af f ic or los s of pack et. This involv es ex it ing LPI m ode an d r eturning to norm al 100Mbps

operating mode. Wake-up time is <30µs for 100Base-TX.

The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for:

• Transmit cable path only

• Receive cable path only

• Both transmit and receive cable paths

The KSZ8091RNA/RND has the EEE function disabled as the power-up default setting. To enable the EEE function for

100Mbps mode, use the following programming sequence:

1. Enable 100Mbps EEE mode advertisement by writing a ‘1’ to MMD Address 7h, Register 3Ch, Bit [1].

2. Restart Auto-Negotiation by writing a ‘1’ to standard Register 0h, Bit [9].

For standard (non-EEE) 10Base-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are

used to maintain the link during the idle period when there is no traffic activity. To save more power, the

KSZ8091RNA/RND provides the option to enable 10Base-Te mode, which saves additional power by reducing the

transm itted signal am plitud e from 2.5V to 1. 75V. To enable 1 0Base-Te m ode, wr ite a ‘1’ to s tandard Regis ter 13h, Bit [4]

and write a ‘0’ to MMD Addres s 1Ch, Register 4h, Bi t [13].

During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approximately

every 20ms to 22ms, a refresh transm ission of 200µs to 220µs is sent to the link partner. The refresh transmissions and

quiet periods are shown in Figure 9.

Figure 9. LPI Mode (Refresh Transmissions and Quiet Periods)

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Transmit Direction Control (MAC-to-PHY)

The KSZ8091RNA/RND enters LPI mode for the transmit direction when its attached EEE-compliant RMII MAC de-

asserts TXEN and sets TXD[1:0] to 01. The KSZ8091RNA/RND remains in the LPI transmit state while the RMII MAC

maintains the states of these signals. When the RMII MAC changes any of the TXEN or TX data signals from their LPI

state values, t he KSZ8 09 1 RNA/R N D exits the LPI transmit state.

Figure 10 shows the LPI transition for RMII (100Mbps) transmit.

Figure 10. LPI Transition – RMII (100Mbps) Transmit

Recei ve Direction Control (PHY-to-MAC)

The KSZ8091RNA/RND enters LPI mode for the receive direction when it receives the /P/ code bit pattern

(Sleep/Refresh) from its EEE-compliant link partner. It then de-asserts CRS_DV and drives RXD[1:0] to 01. The

KSZ8091RNA/RND remains in the LPI r eceive st ate while it cont inues to rec eive the ref resh from its link partner, s o it will

continue to maintain and drive the LPI output states for the RMII receive signals to inform the attached EEE-compliant

RMII MAC that it is in the LPI receive state. When the KSZ8091RNA/RND receives a non /P/ code bit pattern (non-

refresh), it exits the LPI receive state and sets the CRS_DV and RX data signals to set a normal frame or normal idle.

Figure 11 shows the LPI transition for RMII (100Mbps) receive.

Figure 11. LPI Transition – RMII (100Mbps) Receive

Registers Associated with EEE

The following registers are provided for EEE configuration and management:

• Standard Register 13h – AFE Control 4 (to enable 10Base-Te mode)

• MMD Address 1h, Register 0h – PMA/PMD Control 1 (to enable LPI)

• MMD Address 1h, Register 1h – PMA/PMD Status 1 (for LPI status)

• MMD Address 7h, Register 3Ch – EEE Advertisement

• MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement

• MMD Address 1Ch, Register 4h – DSP 10Base-T/10Base-Te Control

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Wake-On-LAN

Wake-On-LAN (WOL) is norm ally a MAC-based f unction to wake up a host s yst em (f or example, an Ethern et end de vice,

such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet

(comm onl y referred to as the “magic pack et” ) that is sent b y the rem ote l ink par tner. The KSZ 8091RNA/RND can perform

the same WOL function if the MAC address of its associated MAC device is entered into the KSZ8091RNA/RND PHY

Registers for magic-packet detection. When the KSZ8091RNA/RND detects the magic packet, it wakes up the host by

driving its power management event (PME) output pin low.

By default, the W OL func tion is disabl ed. It is enable d by sett ing th e enabling bit and c onfiguri ng the as sociated register s

for the selected PME wake-up detection method.

The KSZ8091RNA/RND provides three methods to trigger a PME wake-up:

• Magic-packet detection

• Customized-packet detection

• Link status change detection

Magic-Packet Detection

The m agic packet’s fram e form at star ts with 6 b ytes of 0xFFh and is followed b y 16 repetitions of the MAC address of its

associated MAC device (local MAC device).

When the magic packet is detected from its link partner, the KSZ8091RNA/RND asserts its PME output pin low.

The following MMD Address 1Fh registers are provided for magic-packet detection:

• Magic-packet detecti on is enab led b y writing a ‘1’ to MMD Address 1Fh, Register 0h, Bit [6]

• The MAC address (for the local MAC device) is written to and stored in MMD Address 1Fh, Registers 19h – 1Bh

The KSZ8091RNA/RND does not generate the magic packet. The magic packet must be provided by the external system.

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Customized-Packet Detection

The c ustom ized pac ket has ass ociated r egister /bit m asks to s elect which b yte, or bytes, of the firs t 64 b ytes of the p ack et

to use in the CRC calculation. After the KSZ8091RNA/RND receives the packet from its link partner, the selected bytes for

the rece ived pac ket are us ed to c alculate the C RC. The calcu lat ed CRC is c ompared to th e expec t ed CRC va lue that was

previously written to and stored in the KSZ8091RNA/RND PHY Registers. If there is a match, the KSZ8091RNA/RND

asserts its PME output pin low.

Four cus tomized pac kets are provided t o suppor t four t ypes of wak e-up scenar ios. A ded icated s et of regis ters is used to

configure and enable each customized packet.

The following MMD Registers are provided for customized-packet detection:

• Each of the four customized packets is enabled via MMD Address 1Fh, Register 0h,

Bit [2] // For customized packets, type 0

Bit [3] // For customized packets, type 1

Bit [4] // For customized packets, type 2

Bit [5] // For customized packets, type 3

• Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:

MMD Address 1Fh, Registers 1h – 4h // For customized packets, type 0

MMD Address 1Fh, Registers 7h – Ah // For customized packets, type 1

MMD Address 1Fh, Registers Dh – 10h // For customized packets, type 2

MMD Address 1Fh, Registers 13h – 16h // For customized packets, type 3

• 32-bit expected CRCs are written to and stored in:

MMD Address 1Fh, Registers 5h – 6h // For customized packets, type 0

MMD Address 1Fh, Registers Bh – Ch // For customized packets, type 1

MMD Address 1Fh, Registers 11h – 12h // For customized packets, type 2

MMD Address 1Fh, Registers 17h – 18h // For customized packets, type 3

Link Sta tu s Change Detection

If link status change detec tion is ena bled, the K SZ8091RNA/RND as serts its PME output pin l ow whene ver there is a link

status change, using the following MMD Address 1Fh register bits and their enabled (1) or disabled (0) settings:

• MMD Address 1Fh, Register 0h, Bit [0] // For link-up detection

• MMD Address 1Fh, Register 0h, Bit [1] // For link-down detection

The PME output signal is available on either INTRP/PME_N2 (Pin 18) or LED0/PME_N1 (pin 23), and is enabled using

standard Register 16h, Bit [15]. MMD Address 1Fh, Register 0h, Bits [15:14] defines and selects the output functions for

Pins 18 and 23.

The PME out put is ac tive low and r equires a 1k Ω pull-up to the VDDIO sup pl y. W hen ass erted, t he PME out put is c leared

by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change).

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Reference Circuit for Power and Ground Connections

The KSZ8091RNA/RND is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and

ground connections are shown in Figure 12 and Table 6 for 3.3V VDDIO.

Figure 12. KSZ8091RNA/RND Power and Ground Connections

Table 6. KSZ8091RNA/RND Power Pin Description

Power Pin

Pin Number

Description

VDD_1.2 1 Decouple with 2.2µF and 0.1µF capacitors to ground.

VDDA_3.3 2 Connect to board’s 3.3V supply through a ferrite bead.

Decouple with 22µF and 0.1µF capacitors to ground.

VDDIO 14 Connect to board’s 3.3V supply for 3.3V VDDIO.

Decouple with 22µF and 0.1µF capacitors to ground.

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Typical Current/Power Consumption

Table 7, Table 8, and Table 9 show typic al values for current co nsumption by the transce iver (VDDA_ 3.3) and digital I/O

(VDDIO) power pins, and typical values for power consumption by the KSZ8091RNA/RND device for the indicated

nominal op erating voltag es. These cur rent and power consum ption values inc lud e the transm it driver current and on-chip

regulator current for the 1.2V core.

Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)

Transceiver (3.3V), Digital I/Os (3.3V)

Condition 3.3V Transceiver

(VDDA_3.3) 3.3V Digital I/Os

(VDDIO) Total Chip Power

mA mA mW

100Base-TX Link-up (no traffic) 34 12 152

100Base-TX Full-duplex @ 100% utilization 34 13 155

10Base-T Link-up (no tr affic) 14 11 82.5

10Base-T Ful l-duplex @ 100% utilization 30 11 135

EEE 100Mbps Link-up mode

(transmit and receive in LPI state with no traffic) 13 10 75.9

Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 10 75.9

EDPD mode (Reg. 18h, Bit [11] = 0) 10 10 66.0

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1) 3.77 1.54 17.5

Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 1.51 13.5

Software power-down mode (Reg. 0h, Bit [11] =1) and

slow-oscill at or mod e (Reg. 11 h, Bit [5] =1) 1.36 0.45 5.97

Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)

Transceiver (3.3V), Digital I/Os (2.5V)

Condition 3.3V Transceiver

(VDDA_3.3) 2.5V Digital I/Os

(VDDIO) Total Chip Power

100Base-TX Link-up (no traffic) 34 11 140

100Base-TX Full-duplex @ 100% utilization 34 12 142

10Base-T Link-up (no tr affic) 15 10 74.5

10Base-T Ful l-duplex @ 100% utilization 27 10 114

EEE 100Mbps Link-up mode

(transmit and receive in LPI state with no traffic) 13 10 67.9

Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 10 67.9

EDPD mode (Reg. 18h, Bit [11] = 0) 11 10 61.3

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1) 3.55 1.35 15.1

Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 1.34 10.9

Software power-down mode (Reg. 0h, Bit [11] =1) and

slow-oscill at or mod e (Reg. 11 h, Bit [5] =1) 1.15 0.29 4.52

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Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)

Transceiver (3.3V), Digital I/Os (1.8V)

Condition 3.3V Transceiver

(VDDA_3.3) 1.8V Digital I/Os

(VDDIO) Total Chip Power

mA mA mW

100Base-TX Link-up (no traffic) 34 11 132

100Base-TX Full-duplex @ 100% utilization 34 12 134

10Base-T Link-up (no tr affic) 15 9.0 65.7

10Base-T Ful l-duplex @ 100% utilization 27 9.0 105

EEE 100Mbps Link-up mode

(transmit and receive in LPI state with no traffic) 13 9.0 59.1

Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 9.0 59.1

EDPD mode (Reg. 18h, Bit [11] = 0) 11 9.0 52.5

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1) 4.05 1.21 15.5

Software power-down mode (Reg. 0h, Bit [11] =1) 2.79 1.21 11.4

Software power-down mode (Reg. 0h, Bit [11] =1) and

slow-oscill ator mod e (Reg. 11 h, Bit [5] =1) 1.65 0.19 5.79

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The register space within the KSZ8091RNA/RND consists of two distinct areas.

• Standard registers: // Direct regis ter ac c ess

• MDIO manageable device (MMD) registers: // Indirect register access

The KSZ8091RNA/RND supports the following standard registers:

Table 10. Standard Registers Supported by KSZ8091RNA/RND

IEEE-Defined Registers

0h Basic Control

1h Basic Status

2h PHY Identifier 1

3h PHY Identifier 2

4h Auto-Negotiation Advertisement

5h Auto-Negotiation Lin k Part ner A bility

6h Auto-Negotiation Expansion

7h Auto-Negotiation Next Page

8h Auto-Negotiation Link Partner Next Page Ability

9h – Ch Reserved

Dh MMD Access – Control

Eh MMD Access – Register/Data

Fh Reserved

Vendor-Specific Registers

10h Digital Reserved Control

11h AFE Control 1

12h Reserved

13h AFE Control 4

14h Reserved

15h RXER Counter

16h Operation Mode Strap Override

17h Operation Mode Strap Status

18h Expanded Control

19h – 1Ah Reserved

1Bh Interrupt Control/Status

1Ch Reserved

1Dh LinkMD Cable Diagnostic

1Eh PHY Control 1

1Fh PHY Control 2

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The KSZ8091RNA/RND supports the following MMD device addresses and their associated register addresses, which

make up the indirect MMD registers:

Table 11. MMD Registers Supported by KSZ8091RNA/RND

Device Address (Hex) Register Address (Hex) Description

1h 0h PMA/PMD Control 1

1h PMA/PMD Status 1

7h 3Ch EEE Advertisement

3Dh EEE Link Partner Advertisement

1Ch 4h DSP 10Base-T/10Base-Te Control

1Fh

0h Wake-On-LAN – Control

1h Wake-On-LAN – Customized Packet, Type 0, Mask 0

2h Wake-On-LAN – Customized Packet, Type 0, Mask 1

3h Wake-On-LAN – Customized Packet, Type 0, Mask 2

4h Wake-On-LAN – Customized Packet, Type 0, Mask 3

5h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0

6h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1

7h Wake-On-LAN – Customized Packet, Type 1, Mask 0

8h Wake-On-LAN – Customized Packet, Type 1, Mask 1

9h Wake-On-LAN – Customized Packet, Type 1, Mask 2

Ah Wake-On-LAN – Customized Packet, Type 1, Mask 3

Bh Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0

Ch Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1

Dh Wake-On-LAN – Customized Packet, Type 2, Mask 0

Eh Wake-On-LAN – Customized Packet, Type 2, Mask 1

Fh Wake-On-LAN – Customized Packet, Type 2, Mask 2

10h Wake-On-LAN – Customized Packet, Type 2, Mask 3

11h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0

12h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1

13h Wake-On-LAN – Customized Packet, Type 3, Mask 0

14h Wake-On-LAN – Customized Packet, Type 3, Mask 1

15h Wake-On-LAN – Customized Packet, Type 3, Mask 2

16h Wake-On-LAN – Customized Packet, Type 3, Mask 3

17h Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0

18h Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1

19h Wake-On-LAN – Magic Packet, MAC-DA-0

1Ah Wake-On-LAN – Magic Packet, MAC-DA-1

1Bh Wake-On-LAN – Magic Packet, MAC-DA-2

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Standard Registers

Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE

802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the

IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.

IEEE-Defin ed R egist e rs – Descriptions

Address Name Description Mode

(6)

Default

0.15 Reset 1 = Software reset

0 = Normal operation

This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.14 Loopback 1 = Loopback mode

0 = Normal operation RW 0

0.13 Speed Select

1 = 100Mbps

0 = 10Mbps

This bit is ignored if Auto-Negotiat ion is enab led

(Register 0.12 = 1).

Set by the ANEN_SPEED

strapping pin.

See the Strapping Options section

for details.

0.12 Auto-

Negotiation

Enable

1 = Enable Auto-Negotiation process

0 = Disable Auto-Negotiation process

If enabled, the Auto-Negotiation result overrides

the settings in Registers 0.13 and 0.8.

Set by the ANEN_SPEED

strapping pin.

See the Strapping Options section

for details.

0.11 Power-Down

1 = Power-down mode

0 = Normal opera t ion

If software reset (Register 0.15) is used to exit

power-down m ode (Register 0.11 = 1), two

software reset writes (Register 0.15 = 1) are

required. The first write clears power-down

mode; the second write resets the chip and re-

latches the pin strapping pin values.

RW 0

0.10 Isolate 1 = Electric al iso lation of P HY from RMII

0 = Normal operation RW 0

0.9 Restart Auto-

Negotiation

1 = Restart Auto-Negoti ation process

0 = Normal operation.

This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.8 Duplex Mode 1 = Full-duplex

0 = Half-duplex RW 1

0.7 Collision Test 1 = Enable COL test

0 = Disable COL test RW 0

0.6:0 Reserved Reserved RO 000_0000

Note:

6. RW = Read/Write.

RO = Read only.

SC = Self-cleared.

LH = Latch high.

LL = Latch low.

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IEEE-Defin ed R egist e rs – Descriptions (Continued)

Address Name Description Mode

(6)

Default

1.15 100Base-T4 1 = T4 capable

0 = Not T4 capable RO 0

1.14 100Base-TX

Full-Duplex 1 = Capable of 100Mbps full-duplex

0 = Not capable of 100Mbps full-duplex RO 1

1.13 100Base-TX

Half-Duplex 1 = Capable of 100Mbps half-duplex

0 = Not capable of 100Mbps half-duplex RO 1

1.12 10Base-T

Full-Duplex 1 = Capable of 10Mbps full-duplex

0 = Not capable of 10Mbps full-duplex RO 1

1.11 10Base-T

Half-Duplex 1 = Capable of 10Mbps half-duplex

0 = Not capable of 10Mbps half-duplex RO 1

1.10:7 Reserved Reserved RO 000_0

1.6 No Preamble 1 = Preamble suppression

0 = Normal preamble RO 1

1.5 Auto-

Negotiation

Complete

1 = Auto-Negot iat i on proc es s completed

0 = Auto-Negot iat i on proc es s not comp let ed RO 0

1.4 Remote Fault 1 = Remote fault

0 = No remote fault RO/LH 0

1.3 Auto-

Negotiation

Ability

1 = Can perform Auto-Negotiation

0 = Cannot perform Auto-Negotiation RO 1

1.2 Link Status 1 = Link is up

0 = Link is down RO/LL 0

1.1 Jabber Detect 1 = Jabber detected

0 = Jabber not detected (default is low) RO/LH 0

1.0 Extended

Capability 1 = Supports extended capability registers RO 1

2.15:0 PHY ID

Number

Assigned to the 3rd through 18th bits of the

Organizationally Unique Identifier (OUI).

KENDIN Communication’s OUI is 0010A1

(hex).

RO 0022h

3.15:10 PHY ID

Number

Assigned to the 19th through 24th bits of the

Organizationally Unique Identifier (OUI).

KENDIN Communication’s OUI is 0010A1

(hex).

RO 0001_01

3.9:4 Model Number Six-bit manufacturer’s model number RO 01_0110

3.3:0 Revision

Number Four-bit manufacturer’s revision number RO Indicates silicon revision

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IEEE-Defin ed R egist e rs – Descriptions (Continued)

Address Name Description Mode

(6)

Default

4.15 Next Page 1 = Next page capable

0 = No next page capability RW 0

4.14 Reserved Reserved RO 0

4.13 Remote Fault 1 = Remote fault supported

0 = No remote fault RW 0

4.12 Reserved Reserved RO 0

4.11:10 Pause

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

RW 00

4.9 100Base-T4 1 = T4 capable

0 = No T4 capability RO 0

4.8 100Base-TX

Full-Duplex 1 = 100Mbps full-duplex capable

0 = No 100Mbps full-duplex capability RW

Set by the ANEN_SPEED

strapping pin.

See the Strapping Options section

for details.

4.7 100Base-TX

Half-Duplex 1 = 100Mbps half-duplex capable

0 = No 100Mbps half-duplex capability RW

Set by the ANEN_SPEED

strapping pin.

See the Strapping Options section

for details.

4.6 10Base-T

Full-Duplex 1 = 10Mbps full-duplex c apable

0 = No 10Mbps full-duplex capability RW 1

4.5 10Base-T

Half-Duplex 1 = 10Mbps half-duplex capable

0 = No 10Mbps hal f-duplex capability RW 1

4.4:0 Selector Fiel d [00001] = IEEE 802.3 RW 0_0001

5.15 Next Page 1 = Next page capable

0 = No next page capability RO 0

5.14 Acknowledge 1 = Link code word received from partner

0 = Link code word not yet received RO 0

5.13 Remote Fault 1 = Remote fault detected

0 = No remote fault RO 0

5.12 Reserved Reserved RO 0

5.11:10 Pause

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

RO 00

5.9 100Base-T4 1 = T4 capable

0 = No T4 capability RO 0

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IEEE-Defin ed R egist e rs – Descriptions (Continued)

Address Name Description Mode(6) Default

5.8 100Base-TX

Full-Duplex 1 = 100Mbps full-duplex capable

0 = No 100Mbps full-duplex capability RO 0

5.7 100Base-TX

Half-Duplex 1 = 100Mbps half-duplex capable

0 = No 100Mbps half-duplex capability RO 0

5.6 10Base-T

Full-Duplex 1 = 10Mbps full-duplex c apable

0 = No 10Mbps full-duplex capability RO 0

5.5 10Base-T

Half-Duplex 1 = 10Mbps half-duplex capable

0 = No 10Mbps hal f-duplex capability RO 0

5.4:0 Selector Fiel d [00001] = IEEE 802.3 RO 0_0001

6.15:5 Reserved Reserved RO 0000_0000_000

6.4 Parallel

Detection Fault 1 = Fault detected by parallel detection

0 = No fault detected by parallel detection RO/LH 0

6.3 Link Partner

Able

1 = Link partner has next page capability

0 = Link partner does not have next page

capability RO 0

6.2 Next Page

Able

1 = Local device has next page capability

0 = Local device does not have next page

capability RO 1

6.1 Page Received 1 = New page received

0 = New page not received yet RO/LH 0

6.0

Link Partner

Auto-

Negotiation

Able

1 = Link partner has Auto-Negotiation capabil ity

0 = Link partner does not have Auto-

Negotiation capability RO 0

7.15 Next Page 1 = Additional next pages will follow

0 = Last page RW 0

7.14 Reserved Reserved RO 0

7.13 Message Page 1 = Message page

0 = Unforma t ted pag e RW 1

7.12 Acknowledge2 1 = Will comply with message

0 = Cannot comply with message RW 0

7.11 Toggle

1 = Previous value of transmitted link code

word equal to logic 0

0 = Previous value of transmitted link code

word equal to logic 1

RO 0

7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001

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IEEE-Defined Registers – Descriptions (Conti n u ed)

Address Name Description Mode(6) Default

8.15 Next Page 1 = Additional next pages will follow

0 = Last page RO 0

8.14 Acknowledge 1 = Successful receipt of link word

0 = No successful receipt of link word RO 0

8.13 Message Page 1 = Message page

0 = Unforma t ted pag e RO 0

8.12 Acknowledge2 1 = Can act on the informat ion

0 = Cannot act on the information RO 0

8.11 Toggle

1 = Previous value of transmitted link code

word equal to logic 0

0 = Previous value of transmitted link code

word equal to logic 1

RO 0

8.10:0 Message Field 11-bit wide field to encode 2048 messages RO 000_0000_0000

Registe r Dh – MMD Access – Control

D.15:14 MMD –

Operation

Mode

For the selected MMD Device Address (Bits

[4:0] of this register), these two bits select one

of the following register or data operations and

the usage for MMD Access – Register/Data

(Reg. Eh).

00 = Register

01 = Data, no post increment

10 = Data, post increment on reads and writes

11 = Data, post increment on writes only

RW 00

D.13:5 Reserved Reserved RW 00_0000_000

D.4:0 MMD –

Device

Address These five bits set the MMD device address. RW 0_0000

E.15:0 MMD –

For the selected MMD Device Address (Reg.

Dh, Bits [4:0]),

When Reg. Dh, Bits [15:14] = 00, this register

contains the read/write register address for the

MMD Device Address.

Otherwise, this register contains the read/write

data value for the MMD Device Address and its

selected register address.

See also Reg. Dh, Bits [15:14], for descriptions

of post increment reads and writes of this

RW 0000_0000_0000_0000

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Vendor-S pecific Registers – Descriptions

Address Name Description Mode(7) Default

10.15:5 Reserved Reserved RW 0000_0000_000

10.4 PLL Off 1 = Turn PLL off automatically in EDPD mode

0 = Keep PLL on in EDPD mode.

See also Register 18h, Bit [11] for EDPD mode RW 0

10.3:0 Reserved Reserved RW 0000

11.15:6 Reserved Reserved RW 0000_0000_00

11.5 Slow-Oscillator

Mode Enable

Slow-oscillator mode is used to disconnect the

input reference crystal/clock on the XI pin and

select the on-chip slow oscillator when the

KSZ8091RNA/RND device is not in use after

power-up.

1 = Enable

0 = Disable

This bit automatically sets software power-down

to the analog side when enabled.

RW 0

11.4:0 Reserved Reserved RW 0_0000

13.15:5 Reserved Reserved RW 0000_0000_000

13.4 10Base-Te

Mode

1 = EEE 10Base-Te (1.75V TX amplitude) and

also set MMD Address 1Ch, Register 4h, Bit

[13] to ‘0’.

0 = Standard 10Base-T (2.5V TX amplitude)

and also set MMD Address 1Ch, Register 4h,

Bit [13] to ‘1’.

RW 0

13.3:0 Reserved Reserved RW 0000

15.15:0 RXER Counter Receive error counter for s ymbol error frames RO/SC 0000h

16.15 PME Enable

PME for Wake-On-LAN

1 = Enable

0 = Disable

This bit works in conjunction with MMD Address

1Fh, Reg. 0h, Bits [15:14] to define the output

for Pins 18 and 23.

RW Set by the PME_EN strap pin g pin.

See the Strapping Options section

for details.

16.14:11 Reserved Reserved RW 000_0

16.10 Reserved Reserved RO 0

16.9 B-CAST_OFF

Override

1 = Override to disable broadcast (default

setting) for PHY Address 0

If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0

16.8:7 Reserved Reserved RW 0_0

Note:

7. RW = Read/Write.

RO = Read only.

SC = Self-cleared.

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Vendor-S pecific Registers – Descriptions (Continued)

Address Name Description Mode

(7)

Default

16.6 RMII B-to-B

Override 1 = Override to enable RMII Back-to-Back

mode (also set Bit 1 of this register to ‘1’) RW 0

16.5 NAND Tree

Override 1 = Override to enable NAND Tree mode RW 0

16.4:2 Reserved Reserved RW 0_00

16.1 RMII Override 1 = Override to enable RMII mode RW 1

16.0 Reserved Reserved RW

17.15 Reserved Reserved RO

17.14:13 PHYAD[1:0]

Strap-In Status

[00] = Strap to PHY Address 00000b (0h)

[11] = Strap to PHY Address 00011b (3h)

The KSZ8091RNA/RND supports PHY

addresses 0h and 3h only.

Set by the PHYAD[1:0] strapping

pin.

See the Strapping Options section

for details.

17.12:2 Reserved Reserved RO

17.1 RMII Strap-In

Status 1 = Strap to RMII mode RO

17.0 Reserved Reserved RO

18.15:12 Reserved Reserved RW 0000

18.11 EDPD

Disabled

Energy-detect power-down mode

1 = Disable

0 = Enable

See also Register 10h, Bit [4] for PLL off.

RW 1

18.10:0 Reserved Reserved RW 000_0000_0001

1B.15 Jabber

Interrupt

Enable

1 = Enable jabber interrupt

0 = Disable jabber interrupt RW 0

1B.14 Receive Error

Interrupt

Enable

1 = Enable receive error interrupt

0 = Disable receive error interrupt RW 0

1B.13 Page Received

Interrupt

Enable

1 = Enable page received interrupt

0 = Disable page received interrupt RW 0

1B.12 Parallel Detect

Fault Interrupt

Enable

1 = Enable parallel detect fault interrupt

0 = Disable parallel detect fault interrupt RW 0

1B.11

Link Partner

Acknowledge

Interrupt

Enable

1 = Enable link partner acknowledge interrupt

0 = Disable link partner acknowledge interrupt RW 0

1B.10 Link-Down

Interrupt

Enable

1= Enable link-down interrupt

0 = Disable link-down interrupt RW 0

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Vendor-S pecific Registers – Descriptions (Continued)

Address Name Description Mode

(7)

Default

1B.9 Remote Fault

Interrupt

Enable

1 = Enable remote fault interrupt

0 = Disable remote fault interrupt RW 0

1B.8 Link-Up

Interrupt

Enable

1 = Enable link-up interrupt

0 = Disable link-up interrupt RW 0

1B.7 Jabber

Interrupt 1 = Jabber occurred

0 = Jabber did not occur RO/SC 0

1B.6 Receive Error

Interrupt 1 = Receive error occurred

0 = Receive error did not occur RO/SC 0

1B.5 Page Receive

Interrupt 1 = Page receive occurred

0 = Page receive did not occur RO/SC 0

1B.4 Parallel Detect

Fault Interrupt 1 = Parallel detect fault occurred

0 = Parallel detect fault did not occur RO/SC 0

1B.3 Link Partner

Acknowledge

Interrupt

1 = Link partner acknowledge occurred

0 = Link partner acknowledge did not occur RO/SC 0

1B.2 Link-Down

Interrupt 1 = Link-down oc curred

0 = Link-down did not occur RO/SC 0

1B.1 Remote Fault

Interrupt 1 = Remote fault occurred

0 = Remote fault did not occur RO/SC 0

1B.0 Link-Up

Interrupt 1 = Link-up occurred

0 = Link-up did not occur RO/SC 0

1D.15 Cable

Diagnostic

Test Enable

1 = Enable cable diagnostic test. After test has

completed, this bit is self-cleared.

0 = Indicates cable diagnostic test (if enabled)

has completed and the stat us i nfor m atio n is

valid for read.

RW/SC 0

1D.14:13 Cable

Diagnostic

Test Result

[00] = Normal condition

[01] = Open condition has been detected in

cable

[10] = Short condition has been detected in

cable

[11] = Cable diagnostic test h as failed

RO 00

1D.12 Short Cable

Short Indicator 1 = A short cable (<10 meter) short condition

has been detected by LinkMD RO 0

1D.11:9 Reserved Reserved RW 000

1D.8:0 Cable Fault

Counter D istan ce to fault RO 0_0000_0000

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Vendor-Specific Registers – Descriptions (Continued)

Address Name Description Mode

(7)

Default

1E.15:10 Reserved Reserved RO 0000_00

1E.9 Enable Pause

(Flow Control) 1 = Flow control capable

0 = No flow control capability RO 0

1E.8 Link Status 1 = Link is up

0 = Link is down RO 0

1E.7 Polarity Status 1 = Polarity is reversed

0 = Polarity is not reversed RO

1E.6 Reserved Reserved RO 0

1E.5 MDI/MDI-X

State 1 = MDI-X

0 = MDI RO

1E.4 Energy Detect 1 = Signal present on receive differential pair

0 = No signal detected on receive

differential pair RO 0

1E.3 PHY Isolate 1 = PHY in isolate mode

0 = PHY in normal operation RW 0

1E.2:0 Operation

Mode

Indication

[000] = Still in Auto-Negotiation

[001] = 10Base-T half-duplex

[010] = 100Base-TX half-duplex

[011] = Reserved

[100] = Reserved

[101] = 10Base-T full-duplex

[110] = 100Base-TX full-duplex

[111] = Reserved

RO 000

1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode

0 = Micrel Auto MDI/MDI-X mode RW 1

1F.14 MDI/MDI-X

Select

When Auto MDI/MDI-X is disabled,

1 = MDI-X mode

Transmit on RXP,RXM (pins 4, 3) and Receive

on TXP,TXM (pins 6, 5)

0 = MDI mode

Transmit on TXP,TXM (pins 6, 5) and Receive

on RXP,RXM (pins 4, 3)

RW 0

1F.13 Pair Swap

Disable 1 = Disable Auto MDI/MDI-X

0 = Enable Auto MDI/MDI-X RW 0

1F.12 Reserved Reserved RW 0

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Vendor-S pecific Registers – Descriptions (Continued)

Address Name Description Mode

(7)

Default

1F.11 Force Lin k

1 = Force link pass

0 = Normal link operation

This bit bypasses the control logic and allows

the transmitter to send a pattern even if there is

no link.

RW 0

1F.10 Power Saving 1 = Enable power saving

0 = Disable power saving RW 0

1F.9 Interrupt Level 1 = Interrupt pin active high

0 = Interrupt pin active low RW 0

1F.8 Enable Jabber 1 = Enable jabber coun ter

0 = Disable jabber counter RW 1

1F.7 RMII

Reference

Clock Select

1 = For KSZ8091RNA, clock input to XI (Pin 8)

is 50MHz for RMII – 50MHz Clock Mode.

For KSZ8091RND, clock input to XI (Pin 8) is

25MHz for RMII – 25MHz Clock Mode.

0 = For KSZ8091RNA, clock input to XI (Pin 8)

is 25MHz for RMII – 25MHz Clock Mode.

For KSZ8091RND, clock input to XI (Pin 8) is

50MHz for RMII – 50MHz Clock Mode.

RW 0

1F.6 Reserved Reserved RW 0

1F.5:4 LED Mode [00] = LED0: Link/Activity

[01] = LED0: Link

[10], [11] = Reserved RW 00

1F.3 Disable

Transmitter 1 = Disable transmitter

0 = Enable transmitter RW 0

1F.2 Remote

Loopback 1 = Remote (analog) loopback is enabled

0 = Normal mode RW 0

1F.1 Reserved Reserved RW 0

1F.0 Disable Data

Scrambling 1 = Disable scrambler

0 = Enable scrambler RW 0

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

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MMD Registers

MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up to

65,536 16-bit r egisters, as def ined in Clause 22 of the IEEE 802.3 S pecification. The KSZ8091RN A/RND, ho wever, us es

only a small fraction of the available registers. See the Register Map section for a list of supported MMD device addresses

and their associated register addresses.

The following two standard registers serve as the portal registers to access the indirect MMD registers.

• Standard Register Dh – MMD Access – Control

• Standard Register Eh – MMD Access – Register/Data

Table 12. Portal Registers (Access to Indirect MMD Registers)

Address Name Description Mode Default

Registe r Dh – MMD Access – Control

D.15:14 MMD –

Operation

Mode

For the selected MMD Device Address (Bits

[4:0] of this register), these two bits select one

of the following register or dat a oper atio ns and

the usage for MMD Access – Register/Data

(Reg. Eh).

00 = Register

01 = Data, no post increment

10 = Data, post increment on reads and writes

11 = Data, post increment on writes only

RW 00

D.13:5 Reserved Reserved RW 00_0000_000

D.4:0 MMD –

Device

Address These five bits set the MMD device address. RW 0_0000

E.15:0 MMD –

For the selected MMD Device Address (Reg.

Dh, Bits [4:0]),

When Reg. Dh, Bits [15:14] = 00, this register

contains the read/write register address for

the MMD Device Address.

Otherwise, this register contains the

read/write data value for the MMD Device

Address and its selected register address.

See also Register Dh, Bits [15:14] descriptions

for post increment reads and writes of this

RW 0000_0000_0000_0000

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Examples:

MMD Register Write

Write MMD – Device Address 1Fh, Register 0h = 0001h to enable link-up detection to trigger PME for WoL.

1. Write Register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.

2. Write Regist er Eh with 000 0h // Select Register 0h of MMD – Device Address 1Fh.

3. Write Register Dh with 401Fh // Select register data for MMD – Device Address 1Fh, Register 0h.

4. Write Register Eh with 000 1h // Write value 0001h to MMD – Device Address 1Fh, Register 0h.

MMD Register Read

Read MMD – Device Address 1Fh, Register 19h – 1Bh for the magic packet’s MAC address

1. Write Register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.

2. Write Regis ter Eh with 001 9h // Select Register 19h of MMD – Device Address 1Fh.

3. Write Register Dh with 801Fh // Select register data for MMD – Device Address 1Fh, Register 19h

// with post increments

4. Read Register Eh // Read data in MMD – Device Address 1Fh, R eg ister 19h.

5. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 1Ah.

6. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 1Bh.

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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MMD Registers – Descriptions

Address Name Description Mode

(8)

Default

MMD Address 1h, Register 0h – PMA/PMD Control 1

1.0.15:13 Reserved Reserved RW 000

1.0.12 LPI enable Lower Power Idle enable RW 0

1.0.11:0 Reserved Reserved RW 0000_0000_0000

MMD Address 1h, Register 1h – PMA/PMD Status 1

1.1.15:9 Reserved Reserved RO 0000_000

1.1.8 LPI State

Entered 1 = PMA/PMD has entered LPI state

0 = PMA/PMD has not entered LPI state RO/LH 0

1.1.7:4 Reserved Reserved RO 0000

1.1.3 LPI State

Indication 1 = PMA/PMD is currently in LPI state

0 = PMA/PMD is currently not in LPI state RO 0

1.1.2:0 Reserved Reserved RO 000

MMD Address 7h, Register 3Ch – EEE Advertisement

7.3C.15:3 Reserved Reserved RO 0000_0000_0000_0

7.3C.2 1000Base-T

EEE Capable 0 = 1000Mbps EEE is not supported RO 0

7.3C.1 100Base-TX

EEE Capable

1 = 100Mbps EEE capable

0 = No 100Mbps EEE capability

This bit is set to ‘0’ as the default after power-up

or reset. Set this bit to ‘1’ to enable 100Mbps

EEE mode.

RW 0

7.3C.0 Reserved Reserved RO 0

MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement

7.3D.15:3 Reserved Reserved RO 0000_0000_0000_0

7.3D.2 1000Base-T

EEE Capable 1 = 1000Mbps EEE capable

0 = No 1000Mbps EEE capability RO 0

7.3D.1 100Base-TX

EEE Capable 1 = 100Mbps EEE capable

0 = No 100Mbps EEE capability RO 0

7.3D.0 Reserved Reserved RO 0

MMD Address 1Ch, Register 4h – DSP 10Base-T/10Base-Te Control

1C.4.15 Reserved Reserved RW 0

1C.4.14 Reserved Reserved RO 0

1C.4.13 DSP 10Base-

T/10Base-Te

Mode Select

1 = Standard 10Base-T (2.5V TX amplitude)

and also set Standard Register 13h, Bit [4] to

‘0’.

0 = EEE 10Base-Te (1.75V TX amplitude) and

also set Standard Register 13h, Bit [4] to ‘1’.

RW 1

1C.4.12 Reserved Reserved RW 0

1C.4.11:0 Reserved Reserved RO 0000_0000_0000

Note:

8. RW = Read/Write.

RO = Read only.

LH = Latch high.

Micrel, Inc.

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August

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MMD Registers – Descriptions (Continued)

Address Name Description Mode

(8)

Default

MMD Address 1Fh, Register 0h – Wake-On-LAN – Control

1F.0.15:14 PME Output

Select

These two bits work in conjunction with Reg.

16h, Bit [15] for PME enable to define the

output for Pins 18 and 23.

INTRP/PME_N2 (Pin 18)

00 = INTRP output

01 = PME_N2 output

10 = INTRP and PME_N2 output

11 = Reserved

LED0/PME_N1 (Pin 23)

00 = PME_N1 output

01 = LED0 output

10 = LED0 output

11 = PME_N1 output

RW 00

1F.0.13:7 Reserved Reserved RO 00_0000_0

1F.0.6 Magic Packet

Detect Enable 1 = Enable magic-packet detection

0 = Disable magic-packet det ection RW 0

1F.0.5 Custom-

Packet Type 3

Detect Enable

1 = Enable custom-packet, Type 3 detection

0 = Disable custom-packet, Type 3 detection RW 0

1F.0.4 Custom-

Packet Type 2

Detect Enable

1 = Enable custom-packet, Type 2 detection

0 = Disable custom-packet, Type 2 detection RW 0

1F.0.3 Custom-

Packet Type 1

Detect Enable

1 = Enable custom-packet, Type 1 detection

0 = Disable custom-packet, Type 1 detection RW 0

1F.0.2 Custom-

Packet Type 0

Detect Enable

1 = Enable custom-packet, Type 0 detection

0 = Disable custom-packet, Type 0 detection RW 0

1F.0.1 Link-Down

Detect Enable 1 = Enable link-down detection

0 = Disable link-down detection RW 0

1F.0.0 Link-Up Detect

Enable 1 = Enable link-up detection

0 = Disable link-up detection RW 0

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

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MMD Registers – Descriptions (Continued)

Address Name Description Mode

(8)

Default

MMD Address 1Fh, Register 1h – Wake-On-LAN – Customized Packet, Type 0, Mask 0

MMD Address 1Fh, Register 7h – Wake-On-LAN – Customized Packet, Type 1, Mask 0

MMD Address 1Fh, Register D h – Wake-On-LAN – Customized Packet, Type 2, Mask 0

MMD Address 1Fh, Register 13h – Wake-On-LAN – Customized Packet, Type 3, Mask 0

1F.1.15:0

1F.7.15:0

1F.D.15:0

1F.13.15:0

Custom Packet

Type X Mask 0

This register selects the bytes in the first 16

bytes of the packet (bytes 1 thru 16) that will be

used for CRC calculation.

For each bit in this register,

1 = Byte is selected for CRC calculation

0 = Byte is not selected for CRC calculation

The register-bit to packet-by te mapp ing is as

follows:

Bit [15] : byte-16

… : …

Bit [1] : byte-2

Bit [0] : byte-1

RW 0000_0000_0000_0000

MMD Address 1Fh, Register 2h – Wake-On-LAN – Customized Packet, Type 0, Mask 1

MMD Address 1Fh, Register 8h – Wake-On-LAN – Customized Packet, Type 1, Mask 1

MMD Address 1Fh, Register Eh – Wake-On-LAN – Customized Packet, Type 2, Mask 1

MMD Address 1Fh, Register 14h – Wake-On-LAN – Customized Packet, Type 3, Mask 1

1F.2.15:0

1F.8.15:0

1F.E.15:0

1F.14.15:0

Custom Packet

Type X

Mask 1

This register selects the bytes in the second 16

bytes of the packet (bytes 17 thru 32) that will

be used for CRC calculation.

For each bit in this register,

1 = Byte is selected for CRC calculation

0 = Byte is not selected for CRC calculation

The register-bit to packet-by te mapp ing is as

follows:

Bit [15] : byte-32

… : …

Bit [1] : byte-18

Bit [0] : byte-17

RW 0000_0000_0000_0000

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

31, 2015 53 Revision 1.2

MMD Registers – Descriptions (Continued)

Address Name Description Mode

(

)

Default

MMD Address 1Fh, Register 3h – Wake-On-LAN – Customized Packet, Type 0, Mask 2

MMD Address 1Fh, Register 9h – Wake-On-LAN – Customized Packet, Type 1, Mask 2

MMD Address 1Fh, Register Fh – Wake-On-LAN – Customized Packet, Type 2, Mask 2

MMD Address 1Fh, Register 15h – Wake-On-LAN – Customized Packet, Type 3, Mask 2

1F.3.15:0

1F.9.15:0

1F.F.15:0

1F.15.15:0

Custom Packet

Type X

Mask 2

This register selects the bytes in the third 16

bytes of the packet (bytes 33 thru 48) that will

be used for CRC calculation.

For each bit in this register,

1 = Byte is selected for CRC calculation

0 = Byte is not selected for CRC calculation

The register-bit to packet-by te mapp ing is as

follows:

Bit [15] : byte-48

… : …

Bit [1] : byte-34

Bit [0] : byte-33

RW 0000_0000_0000_0000

MMD Address 1Fh, Register 4h – Wake-On-LAN – Customized Packet, Type 0, Mask 3

MMD Address 1Fh, Register Ah – Wake-On-LAN – Customized Packet, Type 1, Mask 3

MMD Address 1Fh, Register 10h – Wake-On-LAN – Customized Packet, Type 2, Mask 3

MMD Address 1Fh, Register 16h – Wake-On-LAN – Customized Packet, Type 3, Mask 3

1F.4.15:0

1F.A.15:0

1F.10.15:0

1F.16.15:0

Custom Packet

Type X

Mask 3

This register selects the bytes in the fourth 16

bytes of the packet (bytes 49 thru 64) that will

be used for CRC calculation.

For each bit in this register,

1 = Byte is selected for CRC calculation

0 = Byte is not selected for CRC calculation

The register-bit to packet-by te mapp ing is as

follows:

Bit [15] : byte-64

… : …

Bit [1] : byte-50

Bit [0] : byte-49

RW 0000_0000_0000_0000

MMD Address 1Fh, Register 5h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0

MMD Address 1Fh, Register Bh – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0

MMD Address 1Fh, Register 11h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0

MMD Address 1Fh, Register 17h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0

1F.5.15:0

1F.B.15:0

1F.11.15:0

1F.17.15:0

Custom Packet

Type X CRC 0

This register stores the lower two bytes for the

expected CRC.

Bit [15:8] = Byte 2 (CRC [15:8])

Bit [7:0] = Byte 1 (CRC [7:0])

The upper two bytes for the expected CRC are

stored in the follow ing reg ist er.

RW 0000_0000_0000_0000

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

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MMD Registers – Descriptions (Continued)

Address Name Description Mode

(8)

Default

MMD Address 1Fh, Register 6h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1

MMD Address 1Fh, Register Ch – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1

MMD Address 1Fh, Register 12h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1

MMD Address 1Fh, Register 18h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1

1F.6.15:0

1F.C.15:0

1F.12.15:0

1F.18.15:0

Custom Packet

Type X

CRC 1

This register stores the upper two bytes for the

expected CRC.

Bit [15:8] = Byte 4 (CRC [31:24])

Bit [7:0] = Byte 3 (CRC [23:16])

The lower two bytes for the expected CRC are

stored in the previou s regis ter.

RW 0000_0000_0000_0000

MMD Address 1Fh, Register 19h – Wake-On-LAN – Magic Packet, MAC-DA-0

1F.19.15:0

Magic Packet

MAC-DA-0

This register stores the lower two bytes of the

destination MAC address for the magic packet.

Bit [15:8] = Byte 2 (MAC Address [15:8])

Bit [7:0] = Byte 1 (MAC Address [7:0])

The upper four bytes of the destination MAC

address are store d in the follo wing two

registers.

RW 0000_0000_0000_0000

MMD Address 1Fh, Register 1Ah – Wake-On-LAN – Magic Packet, MAC-DA-1

1F.1A.15:0

Magic Packet

MAC-DA-1

This register stores the middle two bytes of the

destination MAC address for the magic packet.

Bit [15:8] = Byte 4 (MAC Address [31:24])

Bit [7:0] = Byte 3 (MAC Address [23:16])

The lower two bytes and upper two bytes of the

destination MAC address are stored in the

previous and following registers, respectively.

RW 0000_0000_0000_0000

MMD Address 1Fh, Register 1Bh – Wake-On-LAN – Magic Packet, MAC-DA-2

1F.1B.15:0

Magic Packet

MAC-DA-2

This register stores the upper two bytes of the

destination MAC address for the magic packet.

Bit [15:8] = Byte 6 (MAC Address [47:40])

Bit [7:0] = Byte 5 (MAC Address [39:32])

The lower four bytes of the destination MAC

address are store d in the previ ous tw o

registers.

RW 0000_0000_0000_0000

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

August

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Absolute Maximum Ratings(9)

Supply Voltage (VIN)

(VDD_1.2) .................................................. –0.5V to +1.8V

(VDDIO, VDDA_3.3) ...................................... –0.5V to +5.0V

Input Voltage (all inputs) .............................. –0.5V to +5.0V

Output Voltage (all outputs) ......................... –0.5V to +5.0V

Lead Temperature (soldering, 10s) ............................ 260°C

Storage Temperature (TS) ......................... –55°C to +150°C

Operating Ratings(10)

Supply Voltage

(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V

(VDDIO_2.5) ........................................ +2.375V to +2.625V

(VDDIO_1.8) ........................................ +1.710V to +1.890V

Ambient Temperature

(TA, Commercial) ...................................... 0°C to +70°C

(TA, Industrial) ....................................... –40°C to +85°C

Maximum Junction Temperature (TJ max.) ................ 125°C

Thermal Resistance (θJA) .................................... 49.22°C/W

Thermal Resistance (θJC) .................................... 25.65°C/W

Electrical Characteristics(11)

Symbol Parameter Condition Min. Typ. Max. Units

Supply Current (VDDIO, VDDA_3.3 = 3.3V)

(12)

IDD1_3.3V 10Base-T Full-duplex traffic @ 100% utilization 41 mA

IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA

IDD3_3.3V EEE (100Mbps) Mode TX and RX paths in LPI state with no traffic 23 mA

IDD4_3.3V EDPD Mode Ethernet cable disconnected (Reg. 18h.11 = 0) 20 mA

IDD5_3.3V Power-Down Mode Software power-down (Reg. 0h.11 = 1) 4 mA

CMOS Level Inputs

VIH Input High Voltage

VDDIO = 3.3V 2.0

VDDIO = 2.5V 1.8

VDDIO = 1.8V 1.3

VIL Input Low Voltag e

VDDIO = 3.3V 0.8

V VDDIO = 2.5V 0.7

VDDIO = 1.8V 0.5

|IIN| Input Current VIN = GND ~ VDDIO 10 µA

CMOS Level Outputs

VOH Output High Voltage

VDDIO = 3.3V 2.4

V VDDIO = 2.5V 2.0

VDDIO = 1.8V 1.5

VOL Output Low Voltage

VDDIO = 3.3V 0.4

V VDDIO = 2.5V 0.4

VDDIO = 1.8V 0.3

|Ioz| Output Tri-State Leakage 10 µA

LED Output

ILED Output Drive Current LED0 pin 8 mA

Notes:

9. Exceeding the absolute maximum ratings may damage the device. Stresses greater than the absolute maximum rating can cause permanent

damage to the device. Operation of the device at these or any other conditions above those specified i n the operating secti ons of this specification i s

not implied. Maximum condit i ons for extended periods may affect reliabil i t y.

10. The device is not guarant eed to function outside its operat i ng ratings.

11. TA = 25°C. Specification for packaged product only.

12. Current consumption is for the single 3.3V supply KSZ8091RNA/RND device only, and includes the transmit driver current and the 1.2V supply

voltage (VDD_1.2) that are suppli ed by the KSZ8091RNA/RND

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Electrical Characteristics(11) (Continued)

Symbol Parameter Condition Min. Typ. Max. Units

All Pull-Up/Pull-Down Pins (including Strapping Pins)

pu Internal Pull-Up Resistance

VDDIO = 3.3V 30 45 73

kΩ VDDIO = 2.5V 39 61 102

VDDIO = 1.8V 48 99 178

pd Internal Pull-Down Resistance

VDDIO = 3.3V 26 43 79

kΩ VDDIO = 2.5V 34 59 113

VDDIO = 1.8V 53 99 200

100Base-TX Transmit (measured differentially after 1:1 transformer)

VO Peak Differential Output Voltage 100Ω termination across differential output 0.95 1.05 V

VIMB Output Voltage Imbalance 100Ω termination across differential output 2 %

tr, tf Rise/Fall Time 3 5 ns

Rise/Fall Time Imbalance 0 0.5 ns

Duty Cycle Di stortion ±0.25 ns

Overshoot 5 %

Output Jitter Peak-to-peak 0.7 ns

10Base-T Transmit (measured differentially after 1:1 transformer)

VP Peak Differential Output Voltage 100Ω termination across differential output 2.2 2.8 V

Jitter Added Peak-to-peak 3.5 ns

tr, tf Rise/Fall Time 25 ns

10Base-T Receive

VSQ Squelch Threshold 5MH z square wave 400 mV

Transmitter – Drive Setting

VSET Reference Voltage of ISET R(ISET) = 6.49kΩ 0.65 V

REF_CLK Output

50MHz RMII Clock Output Jitter Peak-to-peak

(Applies only to RMII – 25MH z clock mode) 300 ps

100Mbps Mode – Industr ial Applications Parameters

tllr Link Loss Reaction (Indication)

Time

Link loss detected at receive differential inputs to

PHY signal indication time for each of the

following:

1. For LED mode 01, Link LED output changes

from low (link-up) to high (link-down).

2. INTRP pin asserts for link-down status change.

4.4 µs

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Timing Diagrams

RMII Timing

Figure 13. RMII Timing – Data Received from RMII

Figure 14. RMII Timing – Data Input to RMII

Table 13. RMII Timing Parameters – KSZ8091RNA/RND (25MHz input to XI pin, 50MHz output from REF_CLK pin)

Timing Parameter Description Min. Typ. Max. Unit

tCYC Clock cycle 20 ns

t1 Setup time 4 ns

t2 Hold time 2 ns

tOD Output delay 7 10 13 ns

Table 14. RMII Timing Parameters – KSZ8091RNA/RND (50MHz input to XI pin)

Timing Parameter Description Min. Typ. Max. Unit

tCYC Clock cycle 20 ns

t1 Setup time 4 ns

t2 Hold time 2 ns

tOD Output delay 8 11 13 ns

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Auto-Negotiation Timing

Figure 15. Auto-Negotiation Fast Link Pulse (FLP) Timing

Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

tBTB FLP burst to FLP burst 8 16 24 ms

tFLPW FLP burst width 2 ms

tPW Clock/D ata pul se w idth 100 ns

tCTD Clock pulse to data pulse 55.5 64 69.5 µs

tCTC Clock pulse to clock pulse 111 128 139 µs

Number of clock/data pulses per FLP burst 17 33

Micrel, Inc.

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MDC/MDIO Timing

Figure 16. M DC/MDIO Timing

Table 16. MDC/MDIO Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

fc MDC Clock Frequency 2.5 10 MHz

tP MDC period 400 ns

tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns

tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns

tMD3 MDIO (PHY output) delay from rising edge of MDC 5 222 ns

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Power-Up/Reset Timing

The KSZ8091RNA/RND reset timing requirement is summarized in Figure 17 and Table 17.

Figure 17. Power-Up/Reset Timing

Table 17. Power-Up/Reset Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 µs

tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 ms

tCS Configurat i on setu p time 5 ns

tCH Configuration hold time 5 ns

tRC Reset to strap-in pin output 6 ns

The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from

10% to 90%.

For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read

and updated at the de-assertion of reset.

After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.

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Reset Circuit

Figure 18 shows a reset circuit recommended for powering up the KSZ8091RNA/RND if reset is triggered by the power

supply.

Figure 18. Recommended Reset Circuit

Figure 19 Shows a reset circuit recomm ended for applications where reset is driven by another device (for example, the

CPU or a n FPG A). T he res et out R ST _OUT _n fr om CPU/FPG A pro vides th e war m res et after power up reset. D2 is used

if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If

different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,

MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO

voltage, D2 c an be remove d to connect both de vices directl y. Usually, Eth ernet device and CP U/FPGA sho uld use same

VDDIO voltag e.

Figure 19. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Reference Circuits – LED Strap-In Pin

The pull-up, float, a nd pull-down reference circuits for the LED 0/ANEN_SPEED strapping pin are shown in Figure 20 for

3.3V and 2.5V VDDIO.

Figure 20. Reference Circuits for LED Strapping Pin

For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the

ANEN_SPEED stra pping pin is functional with a 4.7kΩ pull-up to 1.8V VDDIO or float f or a value of ‘1’, and with a 1.0kΩ

pull-down to ground for a value of ‘0’.

Note: If using RJ45 jacks with integrated LEDs and 1.8V VDDIO, a level shifting is required from LED 3.3V to 1.8V. For

example, use a bipolar transistor or a level shift device.

Micrel, Inc.

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Reference Clock – Connection and Selection

A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8091RNA/RND.

For the KSZ8091RNA/RND in RMII – 25MHz clock mode, the reference clock is 25MHz. The crystal/reference clock

connecti ons to XI ( Pin 8) and X O (Pin 7), an d the c r yst a l / ref erenc e clock selec tion criteria , are pro vided in Figur e 21 and

Table 18.

Figure 21. 25MHz Crystal/Oscillator Reference Clock Connection

Table 18. 25MHz Crystal/Reference Clock Selection Criteria

Characteristics Value Units

Frequency 25 MHz

Frequency tolerance (max.)() ±50 ppm

Crystal series resistance (typ.) 40 Ω

Crystal load capacitance (typ.) 22 pF

Note:

13. ±60ppm for overtemperature crystal.

For the K SZ8091RNA/RND in RMII – 50MH z clock m ode, the reference c lock is 50MH z. The refer ence clock connection

to XI (Pin 8) and the reference clock selection criteria are provided in Figure 22 and Table 19.

Figure 22. 50MHz Oscillator/Reference Clock Connection

Table 19. 50MHz Oscillator/Reference Clock Selection Criteria

Characteristics Value Units

Frequency 50 MHz

Frequency tolerance (max.) ±50 ppm

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Magnetic – Connection and Selection

A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs

exceeding FCC requirements.

The KSZ8091RNA/RND design incorporates voltage-mode transmit drivers and on-chip terminations .

With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential

pairs. Therefore, the two transformer center tap pins on the KSZ8091RNA/RND side should not be connected to any

power supply source on the board; instead, the center tap pins should be separated from one another and connected

through separate 0.1µF common-mode capacitors to ground. Separation is required because the comm on-mode voltage

is different between transmitting and receiving differential pairs.

Figure 23 shows the typical magnetic interface circuit for the KSZ8091RNA/RND.

Figure 23. Typical Magnetic Interface Circuit

Micrel, Inc.

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Table 20 lists recommended magnetic characteristics.

Table 20. Magnetics Selection Criteria

Parameter Value Test Condition

Turns ratio 1 CT : 1 CT

Open-circuit induct ance (min.) 350µH 100mV, 100kHz, 8mA

Insertion lo ss (typ.) –1.1dB 100kHz to 100M Hz

HIPOT (min.) 1500Vrms

Table 21 is a l ist of compati ble si ng le-por t magnetics with s ep ar ate d trans f or mer center tap p ins on the PHY c hip sid e that

can be used with the KSZ8091RNA/RND.

Table 21. Compatible Single-Port 10/100 Magnetics

Manufacturer Part Number Temperature

Range Magnetic + RJ-45

Bel Fuse S558-5999-U7 0°C to 70°C No

Bel Fuse SI-46001-F 0°C to 70°C Yes

Bel Fuse SI-50170-F 0°C to 70°C Yes

Delta LF8505 0°C to 70°C No

HALO HFJ11-2450E 0°C to 70°C Yes

HALO TG110-E055N5 –40°C to 85°C No

LANKom LF-H41S-1 0°C to 70°C No

Pulse H1102 0°C to 70°C No

Pulse H1260 0°C to 70°C No

Pulse HX1188 –40°C to 85°C No

Pulse J00-0014 0°C to 70°C Yes

Pulse JX0011D21NL –40°C to 85°C Yes

TDK TLA-6T718A 0°C to 70°C Yes

Transpower HB726 0°C to 70°C No

Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No

Micrel, Inc.

KSZ8091RNA/KSZ8091RND

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Package Information and Recommended Land Pattern(14)

24-Pin (4mm × 4mm) QFN

Note:

14. Package i nformat i on is correct as of the publication date. For updat es and most current informati on, go to www.micrel.com.

Micrel, Inc.

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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel, Inc. is a leading global manufacturer of IC s olutions for the worldwide high perform ance linear and power, LAN, and tim ing & communic ations

markets. The Company’s products include advanced

mixed-signal, analog & power semiconductors; high-

performance communication, clock

management,

MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs.

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customers include leading manufact

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Corporation headquarters and state

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Additionally, the Company maintains an extensive network

of distribut ors and reps worldwide.

Micrel makes no representations or warranties with respect to the accuracy

or completeness of the information furnished in this datasheet. This

information is not intended as a warranty and Micrel does not assume responsibility for its use.

Micrel reserves the right to change circuitry,

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