MM4018/MM5018 triple 64-bit dynamic shift register general description The MM4018/MM5018 triple 64:bit dynamic shift register is a monolithic MOS integrated circuit utilizing P-channel enhancement mode low thres- hold technology to achieve bipolar compatibility. features Bipolar compatibility +5V, -12V operation No pull-up or pull-down resistors required Dynamic Shift Registers System flexibility Guaranteed minimum operating frequency of 600 Hz at 25C Military and commercial temperature ranges MM4018 = -58C to +128C MMS01B -25C to +70C applications Calculator storage register CRT refresh memory " Serial data storage. connection diagram Metal Can Package iw CLOCK a (5) oata output a BB | (7) vara iets ko (+) oats oureur2 Tor view typical application TTL/MOS interface aay TTLDT DEVICE SLOSWW/SLOV AWy C2) jl = i . . ; absolute maximum ratings Ss Voltage at Any Pin Vgs + 0.3V to Vgs - 22.0V nN Operating Temperature Range MM4018 -88C to +125 C eo MM5018 -25C to +70 C 5 Storage Temperature Range ~65C to +150C Lead Temperature (Soidering, 9 sec} 300C Ss electrical characteristics (T, within operating temperature range, Vgs = +5.0V 15% and Vgq = -12.0V +10%, unless otherwise specitied.) PARAMETER CONDITIONS MIN Tve MAX UNIT Data Input Levels Logical High Level (Via) Vss - 2.0 Vsg + 0.3 v f Logical Low Level (V,.) Vgg - 18.5 Vss - 4.2 v f Data Input Leakage Vin = -20V, Ta = 28C, 0.01 05 HA ; All other pins GND i Data Input Capacitance Vin = 0.0V, f = 1 MHz, 3.0 5.0 pF i All other pins GND Clock input Levels Logicat High Level (Von) Vg - 1.5 Vg + 0.3 Vv Logical Low Level (Vo.} V5 - 18.5 Veg - 14.5 v Clock Input Leakage V, = -20V, Ta = 28C, 0.05 1.0 BA All other pins GND Clock Input Capacitance Vv. = 0.0V, f = 1 MHz, 45 60 pF q All other pins GND h Data Output Levels i Logical High Level (Von) Isounce = 70.5 mA 2.4 Vss Vv FI Logical Low Level {Voi} Isinx = 1.6mA 0.4 v i Power Supply Current (Igg) Ta = 28C, Vag = -12V, Pew = 0.15 us, Vou = -12V 0.01 MHz < < 0.4 MHz 29 45 mA r= 1 MHz 38 5.5 mA y= 2.5 MHz 5.8 7.0 mA Clock Frequency (;} OL, = Oty = 20 ns (Note 1) 0.01 3.3 2.5 MH Clock Pulsewidth (@pw! Ot + Opw tot < 10.5 us 0.15 10 us Clock Phase Delay Times (q oF Gg) Note 1 10 ns Clack Transition Times Risetme (ty) Or + Dew + Ot, S 10.5 ws 2 Hs Falltime (ot) Oty + Pow t Ot, < 10.5 us 2 # Partial Bit Times Input Partial Bit Time (Tin) Note 1 0.20 100 Bs Output Partial Bit Time (Tout) 0.20 100 us Data input Setup Time (tag) 80 30 ns Data Input Hold Time (tan) 20 ) a Data Output Propagation Delay from dour See AC Test Circuit Delay to Output High Level (toa) 150 200 ns Delay 10 Output Low Level (tpai} 150 200 ns Note 1; Minimum clock frequency is a function of temperature and partial bit times (Tn and Tout) as shown by the dy versus temperature and Tin, Tour versus temperature curves. The jowest guar- anteed clock frequency for any temperature can be attained by making Tj, equal to Tour. The Minimum guaranteed clock frequency: @yimin) = Tottous" where T,y and Toyt do not exceed the guaranteed maximums. In * Tout i 38performance characteristics Power Supply Current vs Maximum Power Dissipation Clock Frequency son za - 5 = g 3 = 1 Bb o8 % 125 TEMPERATURE (C) Guaranteed Maximum Tiny and Tout vs Temperature ae MAXIMUM Tay, Tour (mst oe 20 so to 140 TEMPERATURE (C) timing diagram steomvt AVERAGE I (mA) OUTPUT SOUACE CURRENT (mA) IMUM CLOCK FREQUENCY {hdiz) 10 0.001 oot o 10 10.8 CLOCK FREQUENCY ., (MH2) Data Output Source Current vs Data Output Voltage 6 TT Ta = 55 C 5 4+ + Et Tar Boe aft.--f- ape Vf z " mo fence 4 Vsq 15 OV ' Veo + -12.0 Vea = -120V 0 Vour (VE Guaranteed Minimum Clock Frequency vs Temperature Ti OR Tour = 200 a +40 20 20 a 100 1400 TEMPERATURE ( C} AVERAGE Igg (mA) OUTPUT SINK CURRENT ima} Power Supply Current vs Vag, DATA=101.0 18 16 iy i Vss - Vou (Vd Data Output Sink Current va Dats Output Voltage TTF Tas 550! MN og Them bo SSS Ta2 76 Vg = +5.0 b Vag * -12.0--+- Vou + 12.0 14 T ~b 4 c ade b 4 3 2 Your (b ac test circuit SLOSWW/SLODWWChannel Matching Channel matching and crosstalk efficiency are largely dependent on board layout. The layout of Nationals dual amplifier evaluation boards are optimized to produce maximum channel matching and isolation. Typical channel matching for the CLC417 is shown in Figure 3. Channel (Bap) eseyd Channel A Magnitude (0.5dB/div) 1 10 100 Frequency (MHz) Figure 3: Channel Matching The CLC417s channel-to-channel isolation is better than 70dB for input frequencies of 4MHz. Input referred crosstalk vs. frequency is illustrated in Figure 4. -20 & @ & 3 3 s Crosstalk (dB) 2 S nN oS 1 10 100 Frequency (MHz) Figure 4: Input Referred Crosstalk vs. Frequency Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC417 will improve stability. The A, vs. Capacitive Load plot, in the Typical Performance section, gives the recommended series resistance value for optimum flatness at various capacitive loads. Power Dissipation The power dissipation of an amplifier can be described in two conditions: = Quiescent Power Dissipation - Pg (No Load Condition) = Total Power Dissipation - P+ (with Load Condition) The following steps can be taken to determine the power consumption for each CLC417 amplifier: 1. Determine the quiescent power Pa = (Vcc - Vee) * Ice 2. Determine the RMS power at the output stage Po = (Voc - Vioad) (lioad) WHETE Vicad aNd load are the RMS voltage and current across the external load. 3. Determine the total RMS power Py = Pa + Po Add the total RMS powers for both channels to determine the power dissipated by the dual. The maximum power that the package can dissipate at a given temperature is illustrated in the Power Derating curves in the Typical Performance section. The power derating curve for any package can be derived by utiliz- ing the following equation: (175 Tamb) Aja where: Tamb = Ambient temperature (C) 034 = Thermal resistance, from junction to ambient, for a given package (C/W) P= Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC417 (CLC730038 - DIP, CLC730036 - SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. Supply bypassing is required for best performance. The bypass capacitors provide a low impedance return current path at the supply pins. They also provide high frequency filtering on the power supply traces. Other layout factors play a major role in high frequency performance. The following are recommended as a basis for high frequency layout: 1. Include 6.8uF tantalum and 0.1pF ceramic capacitors on both supplies. 2. Place the 6.8uF capacitors within 0.75 inches of the power pins. 3. Place the 0.1uF capacitors less than 0.1 inches from the power pins. 4. Remove the ground plane near the input and output pins to reduce parasitic capacitance. 5. Minimize all trace lengths to reduce series inductances. Additional information is included in the evaluation board literature. Special Evaluation Board Considerations To optimize off-isolation of the CLC417, cut the R; trace on both the 730038 and 730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and output. Figure 5 indicates the alterations recommended to improve off-isolation. http:/Avww.national.com730036 Top Cut traces here 730038 Bottom e * Le e e ee? m e ee ? e eaui@u 730038 e REV B e Cut traces here Figure 5: Optional Evaluation Board Alterations SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for Nationals monolithic amplifiers that: = Support Berkeley SPICE 2G and its many derivatives m Reproduce typical DC, AC, Transient, and Noise performance = Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parame- ters. The application note OA-18, Simulation SPICE Models for Nationals Op Amps, contains schematics and a reproduction of the readme file. http:/Avww.national.com Applications Circuits Video Cable Driver The CLC417 was designed to produce exceptional video performance at all three closed-loop gains. A typical cable driving configuration is shown in Figure 6. In this example, the amplifier is configured with a gain of 2. ao ou < a IL u AML a fo) co - a V7 NOTE: i con The same technique can | 2 er also be applied . to Channel A. | | 3 PF) 250936 [6 bw, -5V a1 : L4 | 4 6.8uF >= ==0.1uF v Figure 6: Typical Cable Driver Single to Differential Line Driver The topology in Figure 7 accomplishes a single-ended to differential conversion with no external components. With this configuration, the value of Vin is limited to the common mode input range of the CLC417. +5V Voutt 7-2 VY ra | O.1NF a= 75 6.8HF i 2502 [z 2500 [pr 7] Vout2 3 ! 25008 0 1/6 HK -5V Mm : 14) [5 ty 6.8nF == ==0.1nF v Ay, = 1V/V Avy = -1V/V Vout = Vin Vin Voutz = -Vin Figure 7: Single to Differential Line Driver