CS4270-DZZR - Cirrus Logic, Inc.

http://www.cirrus.com

Preliminary Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

High Performance

– 105 dB Dynamic Range

– -95 dB THD+N

Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit

– I²S up to 24-bit

– Right-Justified 16-, and 24-Bit

Control Output for External Muting

On-Chip Digital De-Emphasis

Popguard® Technology

Multi-bit ∆Σ Conversion

Digital Volume Control

Single-Ended Output

A/D Features

High Performance

– 105 dB Dynamic Range

– -95 dB THD+N

Multi-bit ∆Σ Conversion

High-Pass Filter to Remove DC Offsets

Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit

– I²S up to 24-bit

Single-Ended Input

System Features

Direct Interface with Logic Levels 1.8 V to 5 V

Internal Digital Loopback

Stand-Alone or Control Port Functionality

Single-Ended Analog Architecture

Supports all Audio Sample Rates from 4 kHz to

216 kHz

3.3 V or 5 V Core Supply

Control Port Supply

1.8 V to 5 V

Configuration

Internal Voltage

Reference

Reset

Serial Interface

Level Translator

Digital Supply

3.3 V to 5 V

Hardware Mode or

I2C/SPI Software Mode

Control Data

Analog Supply

3.3 V to 5 V

Single-Ended

Outputs

PCM Serial

Audio In put Volume

Controls Digital

Filters Switch-Cap

DAC and

Analog Filters

Multi-bit ∆Σ

Modulators

External Mute

Control Mute Signals

Switch-Cap

ADC Single-Ended

Inputs

Digital

Filters

High-Pass

Filter

PCM Serial

Audio Output

MAY '06

DS686PP1

CS4270

2DS686PP1

CS4270

Stand-Alone Mode Feature Set

System Features

– Serial Audio Port Master or Slave Operation

– Single-, Double-, or Quad-Speed Operation

D/A Features

– Auto-Mute on Static Samples

– 44.1 kHz 50/15 µs De-emphasis Available

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

A/D Features

– High-Pass Filter

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

Software Mode Feature Set

System Features

– Serial Audio Port Master or Slave Operation

– Internal Digital Loopback Available

D/A Features

– Selectable Auto-mute

– 44.1-kHz De-emphasis Filters

– Configurable Muting Controls

– Volume Control

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

• Right-Justified 16, and 24-bit

A/D Features

– Selectable High-Pass Filter or DC Offset

Calibration

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

General Description

The CS4270 is a high-performance, integrated audio

CODEC. The CS4270 perfor ms stereo analog- to-digital

(A/D) and digital-to-analog (D/A) conversion of up to

24-bit serial values at sample rates up to 216 kHz.

Standard 50/15 µs de-emphasis is available for sam-

pling rates of 44.1 kHz for compatibility with digital audio

programs mastered using the 50/15 µs pre-emphasis

technique.

Integrated level translators allow easy interfacing be-

tween the CS4270 and other devices operating over a

wide range of logic levels.

Independently addressable high-pass filters are avail-

able for the right and left channe l of the A/D. This allows

the A/D to be used in a wide variety of applications

where one audio channel and one DC measurement

channel is desired.

The CS4270 is availa ble in a 24-pin TSSOP p ackage in

both Commercial (-10° to +70° C) and Automotive

grades (-40° to +85° C). The CDB4270 Custo mer Dem-

onstration board is also available for device evaluation

and implementation sugg estions. Please refer to

“Ordering Information” on page 47 for complete order-

ing information.

The CS4270’s wide dynamic range, negligible distor-

tion, and low noise make it ideal for applications such as

DVD-recorders, digital televisions, set-top boxes, ef-

fects processors, and automotive audio systems.

DS686PP1 3
CS4270
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE MODE ........................................................................................... 6
2. PIN DESCRIPTIONS - STAND-ALONE MODE ..................................................................................... 7
3. TYPICAL CONNECTION DIAGRAM  ..................................................................................................... 8
4. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9
SPECIFIED OPERATING CONDITIONS ............................................................................................... 9
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 9
THERMAL CHARACTERISTICS ... .... ... ... ... ... .... ............................................................. ........................ 9
DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE .......................................................... 10
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE  .......................................................... 10
DAC ANALOG CHARACTERISTICS - ALL MODES  ........................................................................... 11
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 12
ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE .......................................................... 13
ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE  .......................................................... 14
ADC DIGITAL FILTER CHAR ACTERI S TI CS .............................. ... ... ... ... .... ... ... ... .................... ... ... ... ... 15
DC ELECTRICAL CHARACTERISTICS  .............................................................................................. 16
DIGITAL CHARACTERIS TICS ............................. ... ... .... ................... ... ... .... ... ... ... .... ... ......................... 16
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................... 17
SWITCHING CHARACTERISTI CS - I²C MODE CO NTROL PORT ..................................................... 20
SWITCHING CHARACTERISTICS - SPITM CONTROL PORT .......................................................... 21
5. APPLICATIONS  ................................................................................................................................... 22
5.1 Stand-Alone Mode .......................................................................................................... ............... 22
5.1.1 Recommended Power-Up Sequence .................................................................................... 22
5.1.2 Master/Slave Mode  ............................................................................................................... 22
5.1.3 System Clocking ......................................................................................................... ........... 22
5.1.4 Clock Ratio Selection ............................................................................................................ 23
5.1.5  Interpolation Filter ................................................................................................................. 23
5.1.6 High-Pass Filter ..................................................................................................................... 23
5.1.7 Mode Selection & De-Emphasis .. ... ....... ...... ....... ...... ....... ...... ....... ...... ... ....... ...... ....... ...... ...... 24
5.1.8 Serial Audio Interface Format Selection ................................................................................ 24
5.2 Control Port Mode  ......................................................................................................................... 24
5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode ................................... 24
5.2.2 Master / Slave Mode Selection .............................................................................................. 24
5.2.3 System Clocking ......................................................................................................... ........... 25
5.2.4 Clock Ratio Selection ............................................................................................................ 25
5.2.5 Internal Digital Loopback ....................................................................................................... 26
5.2.6 Auto-Mute .............................................................................................................................. 26
5.2.7 High-Pass Filter and DC Offset Calibration ........................................................................... 26
5.2.8 De-Emphasis ......................................................................................................................... 27
5.2.9 Oversampling Modes  ............................................................................................................ 27
5.3 De-Emphasis Filter ........................................................................................................................ 27
5.4 Analog Connections ...................................................................................................................... 28
5.4.1 Input Connections  ................................................................................................................. 28
5.4.2 Output Connections ............................................................................................................... 30
5.5 Mute Control .................................................................................................................................. 30
5.6 Synchronization of Multiple Devices ................. .......................... .......................... ......................... 31
5.7 Grounding and Power Supply Decoupling  .................................................................................... 31
6. CONTROL PORT INTERFACE ............................................................................................................ 32
6.1 SPI™ Mode ................................................................................................................................... 32
6.2 I²C® Mode ............ ... ... .... ... ... ... .... ................... ... ... .... ... ... ... .................... ... ... ... .... ... ... ...................... 33
7. REGISTER QUICK REFERENCE ........................................................................................................ 34
8. REGISTER DESCRIPTION .................................................................................................................. 35
8.1 Chip ID - Address 01h ................................................................................................................... 35

4DS686PP1
CS4270
8.2 Power Control - Address 02h  ........................................................................................................ 35
8.2.1 Freeze (Bit 7) ............ ... ................... .... ... ... ... .... ... ................... ... .... ... ... ... .... ............................ 35
8.2.2 PDN_ADC (Bit 5) ................................................................................................................... 35
8.2.3 PDN_DAC (Bit 1) ................................................................................................................... 35
8.2.4 Power Down (Bit 0)  ............................................................................................................... 35
8.3 Mode Control - Address 03h  .................. .... ... ................... .... ... ... ... ... .... ... ... ... .... ... ... ...................... 36
8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4)  .......................... ... ... ... ... .... ............ 36
8.3.2 Ratio Select (Bits 3:1) .. ... .... ... ... ... ... .... ................... ... .... ... ... ... ... .................... ... ... ... .... ............ 36
8.3.3 PopguardTM Disable (Bit 0) ........ ... .... ... ... ... .... ... ... ... .... ................... ... ... .... ... ... ... ... .... ... ... ...... 36
8.4 ADC and DAC Control - Address 04h ................. .... ... ... ... .... ......................................... ................ 36
8.4.1 ADC HPF Freeze A (Bit 7)  .................... ... ... .... ... ... ... .... ... ... ... ... .... ................... ... ... .... ... ... ...... 36
8.4.2 ADC HPF Freeze B (Bit 6)  .................... ... ... .... ... ... ... .... ... ... ... ... .... ................... ... ... .... ... ... ...... 37
8.4.3 Digital Loopback (Bit 5) ...... ... ... ... .................... ... ... ... .... ... ... ................... .... ... ... ... ... .... ... ......... 37
8.4.4 DAC Digital Interface Format (Bits 4:3) ................................................................................. 37
8.4.5 ADC Digital Interface Format (Bit 0) ...................................................................................... 37
8.5 Transition Control - Address 05h ................................................................................................... 38
8.5.1 DAC Single Volume (Bit 7) .................................................................................................... 38
8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................................... 38
8.5.3 Invert Signal Polarity (Bits 4:1) .... ... .... ... ... ... .... ... ... ... .... ... ................... ... .... ... ... ... ... .... ... ......... 38
8.5.4 De-Emphasis Control (Bit 0) ..... ... ... .................... ... ... .... ... ... ... ... .... ... ................... ... .... ... ... . ..... 39
8.6 Mute Control - Address 06h  ................ ... ....................................................................................... 39
8.6.1 Auto-Mute (Bit 5) ......... ... .... ... ... ... ... .... ... ... ... .................... ... ... ... .... ... ... ... .... ... ......................... 39
8.6.2 ADC Channel A & B Mute (Bits 4:3) ......................... .... ... ... ... ... .... ... ... ... .... ... ......................... 39
8.6.3 Mute Polarity (Bit 2) ............................................................................................................... 39
8.6.4 DAC Channel A & B Mute (Bits 1:0) ......................... .... ... ... ... ... .... ... ... ... .... ... ......................... 39
8.7 DAC Channel A Volume Control - Address 07h ............................................................................ 40
8.8 DAC Channel B Volume Control - Address 08h ............................................................................ 40
9. FILTER PLOTS      ................................................................................................................................ 41
10. PARAMETER DEFINITIONS .............................................................................................................. 45
11. PACKAGE DIMENSIONS  .................................................................................................................. 46
12. ORDERING INFORMATION  .............................................................................................................. 47
13. REVISION HISTORY .......................................................................................................................... 47
LIST OF FIGURES
Figure 1. CS4270 Typical Connection Diagram .......................................................................................... 8
Figure 2. Output Test Load ....................................................................................................................... 11
Figure 3. Maximum Loading ...................................................................................................................... 11
Figure 4. Master Mode, Left-Justified SAI ................................................................................................. 18
Figure 5. Slave Mode, Left-Justified SAI ......... .................... ... ... ... .... ... ... ... ... .... ... ... ... ................................ 18
Figure 6. Master Mode, I²S SAI ................................................................................................................. 18
Figure 7. Slave Mode, I²S SAI ................................................................................................................... 18
Figure 8. Master and Slave Mode SDIN vrs. SCLK .................................................................................. 18
Figure 9. Format 0, Left-Justified up to 24-Bit Data .................................................................................. 19
Figure 10. Format 1, I²S up to 24-Bit Data ............. ... ... ... .... ... ... ... .... ................... ... ... .... ... ... ... ... ................ 19
Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only)
Format 3, Right-Justified 24-Bit Data. (Available in Control Port Mode only)  ........................................... 19
Figure 12. I²C Mode Control Port Timing .................................................................................................. 20
Figure 13. SPI Control Port Timing ........................................................................................................... 21
Figure 14. De-Emphasis Curve ................................................................................................................. 27
Figure 15. CS4270 Recommended Analog Input Network ....................................................................... 28
Figure 16. A/D THD+N Performance vrs. Input Source Resistance  ......................................................... 28
Figure 17. A/D Dynamic Range vrs. Input Source Resistance ................................................................. 29
Figure 18. CS4270 Example Analog Input Network .................................................................................. 30

DS686PP1 5
CS4270
Figure 19. CS4270 Recommended Analog Output Filter .......................................................................... 30
Figure 20. Suggested Active-Low Mute Circuit ......................................................................................... 31
Figure 21. Control Port Timing, SPI Mode  ................................................................................................ 32
Figure 22. Control Port Timing, I²C Mode ................................................................................................. 33
Figure 23. De-Emphasis Curve ................................................................................................................. 39
Figure 24. DAC Single-Speed Stopband Rejection  .................................................................................. 41
Figure 25. DAC Single-Speed Transition Band ......................................................................................... 41
Figure 26. DAC Single-Speed Transition Band (detail) ............................................................................. 41
Figure 27. DAC Single-Speed Passband Ripple ....................................................................................... 41
Figure 28. DAC Double-Speed Stopband Rejection .................................................................................41
Figure 29. DAC Double-Speed Transition Band ....................................................................................... 41
Figure 30. DAC Double-Speed Transition Band (detail) ..... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................42
Figure 31. DAC Double-Speed Passband Ripple ..................................................................................... 42
Figure 32. DAC Quad-Speed Stopband Rejection ....... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42
Figure 33. DAC Quad-Speed Transition Band .......................................................................................... 42
Figure 34. DAC Quad-Speed Transition Band (detail) ..................................................... ......................... 42
Figure 35. DAC Quad-Speed Passband Ripple ........................................................................................ 42
Figure 36. ADC Single-Speed Stopband Rejection  .................................................................................. 43
Figure 37. ADC Single-Speed Stopband (detail)  ...................................................................................... 43
Figure 38. ADC Single-Speed Transition Band (detail) ............................................................................. 43
Figure 39. ADC Single-Speed Passband Ripple ....................................................................................... 43
Figure 40. ADC Double-Speed Stopband Rejection .................................................................................43
Figure 41. ADC Double-Speed Stopband (detail) ..................................................................................... 43
Figure 42. ADC Double-Speed Transition Band (detail) ..... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................44
Figure 43. ADC Double-Speed Passband Ripple ..................................................................................... 44
Figure 44. ADC Quad-Speed Stopband Rejection ....... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 44
Figure 45. ADC Quad-Speed Stopband (detail) ..... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...................... 44
Figure 46. ADC Quad-Speed Transition Band (detail) .............. ... ........................................................... .. 44
Figure 47. ADC Quad-Speed Passband Ripple ........................................................................................ 44
LIST OF TABLES
Table 1. Speed Modes.. ... ... ... .... ... ................... ... .... ... ... ... .... ... ... ................... .... ... ... ... .... ... ... .......... ... ........  22
Table 2. Clock Ratios - Stand-Alone Mode...............................................................................................  23
Table 3. CS4270 Stand-Alone Mode Control.......................................................................................... ..  24
Table 4. Speed Modes.. ... ... ... .... ... ................... ... .... ... ... ... .... ... ... ................... .... ... ... ... .... ... ... .......... ... ........  25
Table 5. Clock Ratios - Control Port Mode................................................................................................  25
Table 6. Analog Input Design Parameters................................................................................................  29
Table 7. Memory Address Pointer . ... ... .... ... ... ... ... .................... ... ... .... ... ... ... ... .... ... ... ... .... ...................... ... ..  33
Table 8. Functional Mode Selection........... ... ... ... .................... ... ... .... ... ... ... ... .... ... ... ... .... ...........................  36
Table 9. MCLK Divider Configuration...................................................................................................... ..  36
Table 10. DAC Digital Interface Formats ...... ... ... ....................... .......................................... .....................  37
Table 11. ADC Digital Interface Formats ...... ... ... ....................... .......................................... .....................  37
Table 12. Soft Cross or Zero Cross Mode Selection................................................................................. 38
Table 13. Digital Volume Control ............ ... ... ............................................................................................  40

6DS686PP1

CS4270

1. PIN DESCRIPTIONS - SOFTWARE MODE

Pin Name # Pin Description

SDIN 1 Serial Audio Data Inp ut (Input) - Input for two’s complement serial audio data.

LRCK 2Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCLK 4Serial Clock (Input/Output) - Serial clock for the serial audio interface.

VD 5Digital Power (Input) - Positi ve power supply for the digital section.

DGND 6Digital Ground (Input) - Ground reference for the internal digital section.

SDOUT 7Serial Audio Da ta Output (Output) - Output for two’s complement serial audio data.

VLC 8Control Port Power (Input) - Determines the signal level for the Control Port.

SDA/CDOUT 9Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for

the Control Port interface in SPI® Mode.

SCL/CCLK 10 Serial Control Port Clock (Input) - Serial clock for the serial Control Port.

AD0/CS 11 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode.

CS is the chip select signal for SPI format.

AD1/CDIN 12 Address Bit 1 (I²C) / Serial Control Data (Input) - AD1 is a chip address pin in I²C Mode. CDIN is the

input data line for the Control Port interface in SPI Mode.

AD2 13 Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C Mode.

RST 14 Reset (Input) - The device enters a low power mode when low.

AINA

AINB 15

16 Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics

specification table.

VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 18 Positive Voltage Referen ce (Output) - Positive reference voltage for the internal sampling circuits.

VA 19 Ana log Power (Input) - Positive power for the analog sections.

AGND 20 Analog Ground (Input) - Ground reference. Must be connected to analog ground.

MUTEA

MUTEB 21

24 Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master

clock to left/right clock frequency ratio is incorrect, or power-down.

AOUTA

AOUTB 22

23 Analog Audio Outp ut (Output) - The full-scale output level is specified in the DAC Analog Character-

istics specification table.

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

SDA/CDOUT

SCL/CCLK

AD0/CS

AD1/CDIN

MUTEB

AOUTB

AOUTA

MUTEA

AGND

FILT+

AINB

AINA

RST

AD2

DS686PP1 7

CS4270

2. PIN DESCRIPTIONS - STAND-ALONE MODE

Pin Name # Pin Description

SDIN 1 Serial Au dio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCLK 4Serial Clock (Input/Output) - Serial clock for the serial audio interface.

VD 5Digital Power (Input) - Positive power supply for the digital secti on.

DGND 6Digital Ground (Input) - Ground reference for the internal digital section.

SDOUT

(M/S) 7Serial Audio Data Outp ut (Output) - Output for two’s complement serial audio data. This pin must be

pulled-up or pulled-down to sel ect Master or Slav e Mode.

VLC 8Control Port Power (Input) - Determines the signal level for the Control Port.

M0 9

10 Mode Selection (Input) - Determines the operational mode of the devi c e.

I²S/LJ 11 Serial Audio Interface Select (Input) - Selects either the Left-Justified or I²S format for the Serial Audio

Interface.

MDIV1

MDIV2 12

13 MCLK Divide (Input) - Configures MCLK divider to divide by 1, 1.5, 2, or 4.

RST 14 Reset (Input) - The device enters a low power mode when low.

AINA

AINB 15

16 Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics

specification table.

VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA 19 Analog Power (Input) - Positiv e po w e r for the an a l og s ect io n s.

AGND 20 Analog Ground (Input) - Ground reference. Must be connected to analog ground.

MUTEA

MUTEB 21

24 Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master

clock to left/right clock frequency ratio is incorrect, or power-down.

AOUTA

AOUTB 22

23 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-

tics specificati on table.

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

I²S/LJ

MDIV1

MUTEB

AOUTB

AOUTA

MUTEA

AGND

FILT+

AINB

AINA

RST

MDIV2

8DS686PP1

CS4270

3. TYPICAL CONNECTION DIAGRAM

Figure 1. CS4270 Typical Connection Diagram

)LJ(I2S/CS /AD0

SDA / CDIN (M1)

SCL / CCLK (M0)

AINA

AINB

RST

Power

Down

and Mode

Settings

(Control Port)

AOUTA

MUTEA

AOUTB

MUTEB

Analog Conditioning

Mute

LRCK

SCLK

MCLK Timing Logic

Clock

SDIN

)S(M/SDOUT Audio Data

Processor

DGND

FILT+

AGND

+3.3 V to 5 V

CS4270

GND or VD

47 kΩ

5.1Ω

Analog Input

Network

47 µF 0.1 µF

10 µF 0.1 µF

1 µF0.1 µF

If using separate supplies for

VA and VD, 5.1 Ω resistor not

needed. See "Grounding and

Power Supply Decoupling."

VLC

+1.8 V to 5 V

3. Use pull-up resistors in Software

Mode. In Hardware Mode, use

pull-up or pull-down. See "Mode

Selection & De-Emphasis."

2 kΩ

(see Figures 12 & 13)

(see Figures 14 & 15)

Use a 47 kΩ pull-down to select

Slave Mode or 47 kΩ pull-up to

VD to select Master Mode. See

"Master/Slave Mode Selection."

AD1 (MDIV2)

AD2 (MDIV1)

DS686PP1 9

CS4270

4. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measurements taken at nominal supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(AGND = 0 V; all voltages with respect to ground.)

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V, All voltages with respect to ground.) (Note 1)

Notes:

1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SRC latch-up.

THERMAL CHARACTERISTICS

3. θJA is specified according to JEDEC specifications for multi-layer PCBs.

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Control Port Interface

VLC

3.1

1.7

5.0

3.3

5.25

Ambient Operating Temperature (Powe r Applied) Commercial

Automotive TA-10

-40 -

-+70

+85 °C

°C

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Control Port Interface

VLC

-0.3

+6.0

Input Current (Note 2) Iin -10 - +10 mA

Analog Input Voltage VIN AGND-0.7 - VA+0.7 V

Digital Input Voltage Control Port Interface

Digital Interface VIND-C

VIND-D -0.3

-0.3 -VLC+0.3

VD+0.3 V

Ambient Operating Temperature (Powe r Applied) TAC -50 - +95 °C

Storage Tempera ture Tstg -65 - +150 °C

Parameters Symbol Min Typ Max Units

Allowable Junction Temperature --135°C

Junction to Ambient Thermal Impedance (Note 3)

(Multi-layer PCB) TSSOP

(Single-layer PCB) TSSOP θJA-M

θJA-S

-70

105 -

-°C/W

°C/W

10 DS686PP1

CS4270

DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE

(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF

(see Figure 2). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE

(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF

(see Figure 2). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

4. One-half LSB of triangular PDF dither added to data.

Parameter

VA = 5 V VA = 3.3 V

Min Typ Max Min Typ Max Unit

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

105

102

103

100

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-89

-76

-36

-87

-67

-27

-83

-70

-30

-81

-61

-21

-89

-76

-36

-87

-67

-27

-83

-70

-30

-81

-61

-21

Parameter

VA = 5 V VA = 3.3 V

Min Typ Max Min Typ Max Unit

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

105

102

103

100

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-89

-76

-36

-87

-67

-27

-79

-66

-26

-77

-57

-17

-89

-76

-36

-87

-67

-27

-79

-66

-26

-77

-57

-17

DS686PP1 11

CS4270

DAC ANALOG CHARACTERISTICS - ALL MODES

Parameter Symbol Min Typ Max Unit

Interchannel Isolation (1 kHz) -100-dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB

Gain Drift -100 +100 ppm/°C

Analog Output

Full Scale Output Voltage 0.6•VA 0.65•VA 0.7•VA Vpp

Max DC Current draw from AOUTA or AOUTB IOUTmax -10-µA

Max AC-Load Resistance (see Figure 3) RL-3-kΩ

Max Load Capacitance (see Figure 3) CL-100-pF

Output Impedance of AOUTA and AOUTB ZOUT -100-Ω

AOUTx

AGND

3.3 µF

Vout

RLCL

100

2.5

51015

Safe Operating

Region

C a p a c itiv e Lo a d - - C ( p F )

Resisti ve Load -- R (k

Ω

)

125

320

Figure 2. Output Test Load Figure 3. Maximum Loading

12 DS686PP1
CS4270
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs.) (See Note 5) 
5. Amplitude vs. Frequency plots of this data are available in Section 9. “Filter Plots” on page 41. See
Figures 24 through 47.
6. Response is clock dependent and will scale with Fs. 
7. For Single-Speed Mo de, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
8. De-emphasis is available only in Single-Speed Mode.
Parameter Symbol Min Typ Max Unit
Single-Speed Mode 
Passband  (Note 6) to -0.1 dB corner
 to -3 dB corner 0
0-
-.35
.4992 Fs
Fs
Frequency Response 10 Hz to 20 kHz  -.175 - +.01 dB
StopBand  .5465 - - Fs
StopBand Attenuation   (Note 7) 50 - - dB
Group Delay  tgd - 10/Fs - s
De-emphasis Error (Note 8)   Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+.05/-.25
-.2/-.4
dB
dB
dB
Double-Speed Mode 
Passband  (Note 6) to -0.1 dB corner
to -3 dB corner 0
0-
-.22
.501 Fs
Fs
Frequency Response 10 Hz to 20 kHz  -.15 - +.15 dB
StopBand  .5770 - - Fs
StopBand Attenuation   (Note 7) 55 - - dB
Group Delay  tgd - 5/Fs - s
Quad-Speed Mode
Passband  (Note 6) to -0.1 dB corner
to -3 dB corner 0
0-
-0.110
0.469 Fs
Fs
Frequency Response 10 Hz to 20 kHz  -.12 - +0 dB
StopBand  0.7 - - Fs
StopBand Attenuation   (Note 7) 51 - - dB
Group Delay  tgd - 2.5/Fs - s

DS686PP1 13

CS4270

ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE

Measurement bandwid th is 10 Hz to 20 kHz unless othe rwise specified . Figure 18 input circuit, 1 kHz sine wave in.

9. Referred to the typical full-scale input voltage.

Dynamic Performance for Commercial Grade VA = 5 V VA = 3.3 V

Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit

Dynamic Range A-weighted

unweighted 99

96 105

102 -

-96

93 102

99 -

-dB

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

THD+N -

-95

-82

-42

-90

-92

-79

-39

-87

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-95

-82

-42

-95

-90

-92

-79

-39

-87

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-95

-82

-42

-95

-90

-92

-79

-39

-87

Dynamic Performance for Commercial Grade - All Modes

Parameter Min Typ Max Unit

Interchannel Isolation - 90 - dB

DC Accuracy

Interchanne l Gain Mismatch - 0.1 - dB

Gain Error -3 - +3 %

Gain Drift -±100 -ppm/°C

Analog Input Characte ristics

Full-Scale Input Voltage 0.53*VA 0.56*VA 0.58*VA Vpp

Input Impedance - 300 - kΩ

14 DS686PP1

CS4270

ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Figure 18 input circuit, 1 kHz sine wave in.

10. Referred to the typical full-scale input voltage.

Dynamic Performance for Automotive Grade VA = 5 V VA = 3.3 V

Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit

Dynamic Range A-weighted

unweighted 97

94 105

102 -

-94

91 102

99 -

-dB

Total Harmonic Distortion + Noise (Note 10)

-1 dB

-20 dB

-60 dB

THD+N -

-95

-82

-42

-90

-92

-79

-39

-87

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 10)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-95

-82

-42

-95

-90

-92

-79

-39

-87

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 10)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-95

-82

-42

-95

-90

-92

-79

-39

-87

Dynamic Performance for Automotive Grade - All Modes

Parameter Min Typ Max Unit

Interchannel Isolation - 90 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -3 - +3 %

Gain Drift -±100 -ppm/°C

Analog Input Characteristics

Full-Scale Input Voltage 0.53*VA 0.56*VA 0.58*VA Vpp

Input Impedance - 300 - kΩ

DS686PP1 15
CS4270
ADC DIGITAL FILTER CHARACTERISTICS
(Measurement Bandwidth is 10 Hz to 20 kHz unle ss oth erwise specified)  (Note 11)
11. Plots of this data are co nt ain ed  in Section 9. “Filter Plots” on page 41. See Figures 24 through 47.
12. The filter frequency response scales precisely with Fs.
13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
Parameter Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB)   (Note 12) 0 - 0.49 Fs
Passband Ripple  - - 0.035 dB
Stopband   (Note 12) 0.57 - - Fs
Stopband Attenuation  70 - - dB
Group Delay  tgd - 12/Fs - s
Double-Speed Mode
Passband (-0.1 dB)   (Note 12) 0 - 0.49 Fs
Passband Ripple  - - 0.05 dB
Stopband   (Note 12) 0.56 - - Fs
Stopband Attenuation  69 - - dB
Group Delay  tgd -9/Fs- s
Quad-Speed Mode
Passband (-0.1 dB)   (Note 12) 0 - 0.26 Fs
Passband Ripple  - - 0.05 dB
Stopband   (Note 12) 0.50 - - Fs
Stopband Attenuation  60 - - dB
Group Delay  tgd -5/Fs- s
High-Pass Filter Characteristics
Frequency Response -3.0 dB 
-0.13 dB   (Note 13) -1
20 -
-Hz
Hz
Phase Devia ti o n @ 20 Hz   (Note 13) -10-deg
Passband Ripple  --0dB

16 DS686PP1

CS4270

DC ELECTRICAL CHARACTERISTICS

(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode)

14. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

15. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

16. Serial Port signals include: SCLK, LRCK, SDOUT, SDIN

Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS, RST

Parameter Symbol Min Typ Max Unit

Power Supply

Power Supply Current VA = 5 V

(Normal Operation) VA = 3.3 V

VD, VLC = 5 V

VD, VLC = 3.3 V

Power Supply Current VA = 5 V

(Power-Down Mode) (Note 14) VD, VLC = 5 V IA

-1.51

0.45 -

-mA

Power Consumption

VA = 5 V, VD = VLC= 3.3 V Normal Operation

VA = 5 V, VD = VLC = 5 V Normal Operation

Power-Down Mode (Note 14)

221

255

9.8

296

323

Power Supply Rejection Ratio (1 kHz) (Note 15) PSRR - 55 - dB

Common Mode Voltage

Nominal Common Mode Voltage VQ - VA/2 - VDC

Maximum DC Current Source/Sink from VQ -1-µA

VQ Output Impedance -25-kΩ

Positive Voltage Reference

FILT+ Nominal Voltage FILT+ - VA - VDC

Maximum DC Current Source/Sink from FILT+ -10-µA

FILT+ Output Impedance -18-kΩ

Mute Control

MUTEA, MUTEB Low-Level Output Voltage -0-V

MUTEA, MUTEB High-Level Output Voltage -VA-V

Maximum MUTEA & MUTEB Drive Current -3-mA

Parameter (Note 16) Symbol Min Typ Max Units

High-Level Input Voltage Serial Port

Control Port VIH 0.7xVD

0.7xVLC -

-V

Low-Level Input Voltage Serial Port

Control Port VIL -

-0.2xVD

0.2xVLC V

High-Level Output Voltage at Io = 2 mA Serial Port

Control Port

MUTEA, MUTEB

VOH VD - 1.0

VLC - 1.0

VA - 1.0

Low-Level Output Voltage at Io = 2 mA VOL --0.4V

Input Leakage Current Iin -10 - 10 µA

DS686PP1 17
CS4270
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF) 
17. In Control Port Mode, MCLK Fr equency and Functional Mode Select bits must be configured according
to Table 5, Table 8, and Table 12.
18. tsclkw = tsclkh + tsclkl in Figures 5 and 7.
Parameter Symbol Min Typ Max Unit
Sample Rate  Single-Speed Mode
 Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
54
108
216
kHz
kHz
kHz
MCLK Specifications
MCLK Frequency   tand-Alone Mode
 (Note 17) Control Port Mode fmclk
fmclk 1.024
1.024 -
-55.296
55.296 MHz
MHz
MCLK Duty Cycle  40 50 60 ns
Master Mode
LRCK Duty Cycle  -50-%
SCLK Period  (Note 18) tsclkw --s
SCLK Duty Cycle  -50-%
SCLK falling to LRCK edge  tmslr -20 - 20 ns
SCLK falling to SDOUT valid  tsdo - - 32 ns
SDIN valid to SCLK rising setup time  tsdis 16 - - ns
SCLK rising to SDIN hold time  tsdih 20 - - ns
Slave Mode
LRCK Duty Cycle  40 50 60 %
SCLK Period 
 (Note 17) Single-Speed Mode
 
 Double-Speed Mode
 
 Quad-Speed Mode
tsclkw
tsclkw
tsclkw
-
-
-
-
-
-
s
s
s
SCLK Duty Cycle  45 50 55 ns
SCLK falling to LRCK edge  tslrd -20 - 20 ns
SDOUT valid before SCLK rising  tstp 10 - - ns
SDOUT valid after SCLK rising  thld 5--ns
SDIN valid to SCLK rising setup time  tsdis 16 - - ns
SCLK rising to SDIN hold time  tsdih 20 - - ns
1
64()Fs
------------------
1
128()Fs
---------------------
1
64()Fs
------------------
1
64()Fs
------------------

18 DS686PP1

CS4270

SCLK output

SDOUT

LRCK output

MSB MSB-1 MSB-2 MSB-3

tmslr

tsdo

LRCK input

SCLK input

SDOUT MSB

tstp thld

tsclkl

tsclkh

MSB-1

tslrd

Figure 4. Master Mode, Left-Justified SAI Figure 5. Slave Mode, Left-Justified SAI

SC LK output

SDOUT

LRCK output

MSB MSB-1 MSB-2 MSB-3

tsdo

tmslr

LRCK input

SCLK input

SDOUT

tstp thld

tsclkl

tsclkh

MSB

tslrd

Figure 6. Master Mode, I²S SAI Figure 7. Slave Mode, I²S SAI

sdis

SCLK

SDIN

sdih

sclkw

Figure 8. Master and Slave Mode SDIN vrs. SCLK

DS686PP1 19

CS4270

Figure 9. Format 0, Left-Justified up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Figure 10. Format 1, I²S up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx +3 +2 +1+5 +4

-1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB MSB

LSB LSB

LRCK

SCLK

Left Channel

SDATA +5 +4 +3 +2 +1

MSB -1 -2 -3 -4 -5

32 clocks

Right Channel

LSB +5 +4 +3 +2 +1

-1 -2 -3 -4 -5

-6 +6

-6

Channel A - Left Channel B - Right

LSB MSB LSB

Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only)

Format 3, Right-Justified 24-Bit Data. (Available in Control Port Mode only)

20 DS686PP1

CS4270

SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT

(Inputs: logic 0 = DGND, logic 1 = VLC)

19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Parameter Symbol Min Max Unit

I²C Mode

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 19) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of Both SDA and SCL Lines tr-1µs

Fall Time of Both SDA and SCL Lines tf-300ns

Setup Time for Stop Condition tsusp 4.7 - µs

buf thdst

hdst

low

hdd

thigh

sud

sust

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 12. I²C Mode Control Port Timing

DS686PP1 21

CS4270

SWITCHING CHARACTERISTICS - SPITM CONTROL PORT

(Inputs: logic 0 = DGND, logic 1 = VLC)

20. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

21. Data must be held for sufficient time to bridge the transition time of CCLK.

22. For FSCK < 1 MHz

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 20) tspi 500 - ns

CS High Time Between Transmissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl 82 - ns

CCLK High Time tsch 82 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 21) tdh 15 - ns

Rise T ime of CCLK and CDIN (Note 22) tr2 -100ns

Fall Time of CCLK and CDIN (Note 22) tf2 -100ns

tr2 tf2

dsu

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 13. SPI Control Port Timing

22 DS686PP1

CS4270

5. APPLICATIONS

5.1 Stand-Alone Mode

5.1.1 Recommended Power-Up Sequence

Reliable power- up can be accomplished by keeping th e device in reset until the power supplies, clocks

and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital

supplies drop below the minimum specified operating voltages to prevent power glitch related issues.

5.1.2 Master/Slave Mode

The CS4270 supports operation in either Master Mode or Slave Mode.

In Master Mode, LRCK and SCLK are outputs and are synchronously generated on- chip. LRCK is equal

to Fs and SCLK is equal to 64x Fs.

In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.

It is recommended that SCLK be 48x or 64x Fs to maximize system performance.

In Stand-Alone Mode, the CS4270 will enter Slave Mode when SDOUT (M/S) is pulled low through a

47 kΩ resistor. Master Mode may be accessed by placing a 47 kΩ pull-u p to VD on the SDOUT (M/S) pin.

Configuration of clock ratios in each of these modes is outlined in Table 2.

5.1.3 System Clocking

The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three

speed modes as shown in Table 1

Mode Sampling Frequency

Single-Speed 4-54 kHz

Double-Speed 50-108 kHz

Quad-Speed 100-216 kHz

Table 1. Speed Modes

DS686PP1 23

CS4270

5.1.4 Clock Ratio Selection

Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK

ratios may be used. These ratios are shown in the Table 2.

5.1.5 Interpolation Filter

In Stand-Alone Mode, the fast ro ll-off interpol ation filter is used. Filter specificatio ns can be found in Sec-

tion 4. Plots of the data are contained in Section 9. “Filter Plots” on page 41.

5.1.6 High-Pass Filter

The opera tional amplifiers in the input circ uitry driving the CS4270 may generate a small DC offset into

the ADC. The CS4270 includes a hig h-pass filter after the decimator to remove any DC offset which could

result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel

system. In Stand-Alone Mode, the high-pass filter continuously subtracts a measu re of the DC offset from

the output of the decimation filter This function cannot be disabled in Stand-Alone Mode.

Master Mode

MCLK/LRCK SCLK/LRCK LRCK MDIV2 MDIV1

Single-Speed

256 64 Fs 0 0

384 64 Fs 0 1

512 64 Fs 1 0

1024 64 Fs 1 1

Double-Speed

128 64 Fs 0 0

192 64 Fs 0 1

256 64 Fs 1 0

512 64 Fs 1 1

Quad-Speed

64 64 Fs 0 0

96 64 Fs 0 1

128 64 Fs 1 0

256 64 Fs 1 1

Slave Mode

MCLK/LRCK SCLK/LRCK LRCK MDIV2 MDIV1

Single-Speed

256 32, 48, 64, 128 Fs 0 0

384 32, 48, 64, 96 Fs 0 1

512 32, 48, 64, 128 Fs 1 0

1024 32, 48, 64 , 96 Fs 1 1

Double-Speed

128 32, 48, 64 Fs 0 0

192 32, 48, 64 Fs 0 1

256 32, 48, 64 Fs 1 0

512 32, 48, 64 Fs 1 1

Quad-Speed

64 32, 48, 64 Fs 0 0

96 32, 48, 64 Fs 0 1

128 32, 48, 64 Fs 1 0

256 32, 48, 64 Fs 1 1

Table 2. Cloc k Rati os - Stand-Alone Mode

24 DS686PP1

CS4270

5.1.7 Mode Selection & De-Emphasis

The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz,

is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper

mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0

pin becomes De-emph asis select. Stand-alone definitions of the mode pins are shown in Table 3.

5.1.8 Serial Audio Interface Format Selection

Either I²S or Left-Justified serial audio data format may be selected in Stand-Alone Mode. The selection

will affect both the input and output format. Placing a 10 kΩ pull-up to VD on the I²S/LJ pin will select the

I²S format, while placing a 10 kΩ pull-down to DGND on the I²S/LJ pin will select the Left-Justified format.

5.2 Control Port Mode

5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode

1. Pull RST low until the power supply, MCLK, and LRCK are stable.

2. Release RST. The Control Port will be accessible.

3. Set the power down bit (register 0x02h, bit 0) to “1” for 1 ms minimum within 10 ms after releasing

RST and then set to “0” prior to reading or writing to other registers.

4. Initiate a SPI or I²C transaction as described in Section 6.1 or Section 6.2, respectively.

5.2.2 Master / Slave Mode Selection

The CS4270 suppor ts operation in either Master Mode or Slave Mode.

In Master Mode, LRCK and SCLK are outputs and are synchronously generated on- chip. LRCK is equal

to Fs and SCLK is equal to 64x Fs.

In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.

It is recommended that SCLK be 48x or 64x Fs to maximize system performance.

Configuration of clock ratios in each of these modes will be outlined in the Table 10 and Table 9.

In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by

changing the status of the M/S bits in the Functional Control Register (03h).

Mode 1 Mode 0 Mode Sample Rate (Fs) De-Emphasis

0 0 Single-Speed Mode 4 kHz - 54 kHz Off

0 1 Single-Speed Mode 4 kHz - 54 kHz 44.1 kHz

1 0 Double-Speed Mode 50 kHz - 108 kHz Of f

1 1 Quad-Speed Mode 100 kHz - 216 kHz Off

Table 3. CS4270 Stand-Alone Mode Control

DS686PP1 25

CS4270

5.2.3 System Clocking

The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three

speed modes as sh own in Table 4.

5.2.4 Clock Ratio Selection

In Control Port Master Mode, the user must configure the mode bits (MCLK Freq<2:0>) to set the speed

mode and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave

Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control

Port Register Bits are shown in Table 5, Table 9 and Section 8.3 on page 36.

Mode Sampling Frequency

Single-Speed 4-54 kHz

Double-Speed 50-108 kHz

Quad-Speed 100-216 kHz

Table 4. Speed Modes

Master Mode

MCLK/LRCK SCLK/LRCK LRCK MCLK

Freq<2> MCLK

Freq<1> MCLK

Freq<0>

Single-Speed

256 64 Fs 0 0 0

384 64 Fs 0 0 1

512 64 Fs 0 1 0

768 64 Fs 0 1 1

1024 64 Fs 1 0 0

Double-Speed

128 64 Fs 0 0 0

192 64 Fs 0 0 1

256 64 Fs 0 1 0

384 64 Fs 0 1 1

512 64 Fs 1 0 0

Quad-Speed

64 64 Fs 0 0 0

96 64 Fs 0 0 1

128 64 Fs 0 1 0

192 64 Fs 0 1 1

256 64 Fs 1 0 0

Slave Mode

MCLK/LRCK SCLK/LRCK LRCK MCLK

Freq<2> MCLK

Freq<1> MCLK

Freq<0>

Single-Speed

256 32, 64, 128 Fs 0 0 0

384 32, 48, 64, 96, 128 Fs 0 0 1

512 32, 64, 128 Fs 0 1 0

768 32, 48, 64, 96, 128 Fs 0 1 1

1024 32, 64, 128 Fs 1 0 0

Table 5. Clock Ratios - Control Port Mode

26 DS686PP1

CS4270

5.2.5 Internal Digital Loopback

In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output of the

ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in

the ADC & DAC Ctrl register (04h).

When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270.

Any changes made to the DAC_DIF(4:3) bits while the Digital Loopbac k bit is set will have no impact on

operation until the Dig ital Loopback bit is released, at which time the Digital Interface Format of the DAC

will operate according to the format selected in the DAC _DIF(4:3) bits. While the Digital Loopback bit is

set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.

5.2.6 Auto-Mute

The Auto-Mute function is contro lled by the status of the Au to Mute bi t in the Mute r egister. When set, the

DAC output will mute following the reception of 8192 consecutive audi o sample s of static 0 or -1 . A single

sample of non-static data will release the mute. Detection and muting are done independently for each

channel. The common mode on the output will be retained and the Mute Control pin for that channel will

become active during the mute period. The m uting function is affected, similar to volume control changes,

by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default.

5.2.7 High-Pass Filter and DC Offset Calibration

The input circuitry driving the CS4270 may generate a small DC offset into the A/D converter. The CS4270

includes a high-pass filter after the decimator to remove any DC offset which could result in rec ording a

DC level, possibly yielding "clicks" when switching between devices in a multichannel system.

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. The high-pass filter can be enabled if the hpf_freeze bit is set during normal operation, the current

value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be sub-

tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration

by:

1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

2. Disabling the high-pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the

calibration point an d th e CS4 27 0.

Double-Speed

128 32, 48, 64 Fs 0 0 0

192 32, 48, 64 Fs 0 0 1

256 32, 48, 64 Fs 0 1 0

384 32, 48, 64 Fs 0 1 1

512 32, 64 Fs 1 0 0

Quad-Speed

64 32 Fs 0 0 0

96 48, 64 Fs 0 0 1

128 32, 64 Fs 0 1 0

192 48, 64 Fs 0 1 1

256 32, 64 Fs 1 0 0

Table 5. Clock Ratios - Control Port Mode (Continued)

DS686PP1 27

CS4270

5.2.8 De-Emphasis

One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate.

5.2.9 Oversampling Modes

The CS4270 operates in one of three oversampling modes based on the input samp le rate. Mode selec-

tion is determined by the FM_&_M/S_Mode[1:0] bits in the Functional Mode register (03h). Single-Speed

Mode supports input sample rates up to 54 kHz and uses a 128x oversampling ratio. Double-Speed Mode

supports input sample rates up to 108 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode

supports input sample rate s up to 216 kHz and uses an oversampling ratio of 32x. See Table 10 for Con-

trol Port Mode settings.

5.3 De-Emphasis Filter

The CS4270 includes on-chip digital de-emphasis. Figure 14 shows the de - em p ha sis cu rve for Fs equal

to 44.1 kHz. The frequency response of the de-emphasis curv e will scale proportionally with changes in

sample rate, Fs. Plea se see Section 5.1.7 for the desired de-e mphasis control for Stand-Alo ne Mode and

Section 5.2.8 for Control Port Mod e.

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis

equalization as a means of noise reduction.

De-emphasis is only available in Single-Speed Mode.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kH z 10. 61 kHz

Figure 14. De-Emphasis Curve

28 DS686PP1

CS4270

5.4 Analog Connections

5.4.1 Input Connections

The analog modulator samples the input at 6.144 MHz.The digital filter will reject signals within the stop-

band of the filter. However, there is no rejection for input signals which are multiples of the input sampling

frequency (n ×6.144 MHz), where n=0,1,2,... Refer to Figure 15 which shows the recommended topology

of the analog input network. The capacitor values chosen not only provide the appropriate filtering of noise

at the mo dulator sampling f requency, but also act as a charge source for the internal sampling circuits.

The use of capacitor s which have a large vo ltage coefficient (such as general purpose ceramics) must be

avoided since these ca n degrade signal linearity.

Three paramete rs determine the values of resistors R1 and R2 as shown in Figure 15 source impedance,

attenuation, and input impedance. Table 6 shows the design equat ion use d to de te rm in e th ese values.

Source Impedance: Source impedance is defined as the impeda nce as seen from the ADC lo oking back

into the signal netwo rk. The ADC achieves optimal THD+N per formance when source imped ance is min-

imized and THD+N degrades for source impedance greater than 1 kΩ. See Figure 16 and 17 below.

Figure 15. CS4270 Recommended Analog Input Network

CS4270

AINx

220 pF

10µFR1

Analog

Input

Figure 16. A/D THD+N Per f ormance vrs. Input Source Resistance

DS686PP1 29

CS4270

Attenuation: The required attenuation factor depends on th e magnitude of the input signal. For

VA = 5 V, the full-scale input voltage equals 1 Vrms. The full-scale input voltage scales with VA as indi-

cated on pages 13 and 14. The user should select values for R1 and R2 such that the magnitude of the

incoming signal multiplied by the attenuation factor is less than or equal to the full-scale input voltage of

the device.

Input Impedance: Input impedance is the impedance from the signal source to the ADC analog input

pins. Table 6 shows the input parameters and the associated design equations.

Figure 18 illustrates an example configuration using two 2 kΩ resistors in place of R1 and R2. This circuit

will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the ADC, 1 Vrms when VA = 5

V and is the maximum source impedance for the ADC specifications listed in this Data Sheet.

Source Impedance

Attenuation Fact or

Input Impedance

Table 6. Analog Input Design Parameters

Figure 17. A/D Dynamic Range vrs. Input Source Resistance

R1R2

×()

R1R2+

-------------------------

()

R1R2+()

-------------------------

R1R2+

()

30 DS686PP1

CS4270

5.4.2 Output Connections

The analog output filter presen t in the CS4270 is a switched-capacitor filter fo llowed by a continuous time

low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 24 - 47. The

recommended external analog circuitry is shown in Figure 19.

5.5 Mute Control

The Mute Control pins become active during power-up initialization, reset, muting, when the MCLK to

LRCK ratio is incorrect, and during power-down. The MUTE pins are intended to be used as control for

an external mute circuit in order to add off-chip mute capability.

The CS4270 also features Auto-Mute, which is enabled by default. The Auto-Mute function causes the

MUTE pin correspondin g to an individua l ch annel to activate following the recep tion of 8192 conse cutive

static-level audio samples on the respective channel. A single transition of data on the channel will cause

the corresponding MUTE pin to deactivate.

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute

minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system

designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute

circuit. The MUTE pins are active-low. Se e Figure 20 for a suggested active-low mute circuit.

Figure 18. CS4270 Example Analog Input Network

CS4270

AINx

220 pF

2 k Ω

10 µF

Analog

Input

2 k Ω

Figure 19. CS4270 Recommended Analog Output Filter

Analog Output

R+470

C= 4πFs(R470)

3.3µF

10kΩC

470Ω

Rext

ext

ext For best 20 kH z response

AOUTx

CS4270

DS686PP1 31

CS4270

5.6 Synchronization of Multiple Devices

In systems where multip le ADCs are requ ired, care must be taken to achi eve simultaneou s sampling. To

ensure synchronous sam pling, the MCLK and LRCK mu st be the same for a ll of the CS427 0’s in the sys-

tem. If only one MCLK source is needed , one solution is to place one CS4270 in M aster Mode, a nd slave

all of the other CS4270’s to the one master. If multiple MCLK sources are needed, a possible solution

would be to supply all clocks from the same external source and time the CS4270 reset with the inactive

edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.

5.7 Grounding and Power Supply Decoupling

As with any high resolution co nverter, the CS4270 requires careful attention to power sup ply and ground-

ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power

arrangements, with VA and VD connected to clean supplies. VD, which powers the digital filter, may be

run from the system digital supply (VD) o r may b e po were d fro m the an alo g supply ( VA) via a r esistor. In

this case, no additional devices sho uld be powered fr om VD. Power supply decouplin g capacitors should

be as near to the CS4270 as possible, with the low value ceramic capacitor being the nearest. All signals,

especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted cou-

pling into the modulators. The VREF and VCOM decoupling capacitors, particularly the 0.1 µF, must be

positioned to minimize the electrical path from VREF and AGND. The CDB4270 evaluation board dem-

onstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the

CS4270 digital outputs only to CMOS inputs.

LPF

+VEE

-VEE

560 ΩAudio

Out

2 kΩ

10 kΩ

-VEE

+VA

MMUN2111LT1

AOUTx

MUTEx

CS4270

Couple

47 kΩ

Figure 20. Suggested Active-Low Mute Circuit

32 DS686PP1

CS4270

6. CONTROL PORT INTERFACE

The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Port may be

completely asynchronou s to the a udio sa mple rate. However, to avoid potential interference problems, the Control

Port pins should remain static if no operation is required.

The Control Port has 2 modes: SPI and I²C, with the CS4270 operating as a slave to control messages in both

modes. If I²C operation is desired, AD0/CS should be tied to VLC or DGND. If the CS4270 ever detects a high to

low transition on AD0/CS after power-up, SPI Mode will be selected.

Upon release of the RST pin, the CS4270 will wait approximately 10 ms before it begins its start-up sequence. The

part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in Section 5.1 on

page 22. If the user initiates communication to the p art through the SPI o r I²C interface, the part enters Control- Port

Mode and all operational modes are controlled by the Control Port regist ers. If syst em requirements do not allow

writing to the Control Port immediately following the release of RST, the SDIN line should be held at logic “0” until

the proper serial mode can be selected.

6.1 SPI™ Mode

In SPI Mode, CS is the CS4270 chip select signal, CCLK is the Control Port bit clock, CDIN is the input data

line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is

clocked in on the rising edge of CCLK.

Figure 21 shows the operatio n of the Control Port in SPI Mo de. To write to a register , bring CS low. The first

7 bits on CDIN form the chip address, a nd mu st be 100 111 1. The ei ghth b it is a read/write indicator (R/W ),

which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the

address of the register that is to be updated. The next 8 bits are the data which will be placed into the register

designated by the MAP. See Table 9 on page 36.

The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the

MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte

is written, allowing block writes to successive registers.

MAP

MSB LSB

DATA

byte 1 byte n

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

CDIN

CCLK

1001111

Figure 21. Control Port Timing, SPI Mode

DS686PP1 33

CS4270

6.2 I²C® Mode

In I²C Mode, SDA is a bi-directiona l data line. Data is cl ocked into and out of the p art by the clock, SCL, with

the clock to data relationsh ip as shown in Figure 22. There is no CS pin. Pins AD0, AD1, and AD2 form the

partial chip address and should be tied to VLC or DGN D a s re q uir ed . T h e up pe r 4 b i ts of th e 7 -b i t ad dr es s

field must be 1001. To communicate with the CS4270, the three lower bits of the chip address field should

match the setting on the AD0, AD1, and AD2 pins. The e ighth bit of the addre ss byte is the R/W bit (high for

a read, low for a write) . The next byte is the Memory Address Pointer, MAP, which selects the register to be

read or written. If the operation is a write, the MAP is then followed by the data to be writte n. If the operation

is a read, then the contents of the register pointed to by the MAP will be output after the chip address.

The CS4270 has MAP auto increment capability, ena bled by the INCR bit in the MAP. If INCR is 0, then the

MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte

is written, allowing block reads or writes of successive registers.

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

INCR - Auto MAP Increment Enable

Default = ‘0’.

0 - Disabled

1 - Enabled

MAP(3:0) - Memory Address Pointer

Default = ‘0000’.

Table 7. Memory Address Pointer

SDA

SCL

1001 ADDR

AD2 R/W

Start

ACK DATA

1-8 ACK DATA

1-8 ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

AD0

Figure 22. Control Port Timing, I²C Mode

34 DS686PP1

CS4270

7. REGISTER QUICK REFERENCE

This table shows the register names and their associated default values.

Addr Function 7 6 5 4 3 2 1 0

01h ID id<3> id<2> id<1> id<0> rev<3> rev<2> rev<1> rev<0>

110 0 0 0 0 1

02h Power

Control Freeze Reserved PDN_ADC Reserved Reserved Reserved PDN_DAC PDN

000 0 0 0 0 0

03h Funct Mode Reserved Reserved FM_&_M/S

_Mode1 FM_&_M/S_

Mode0 MCLK

freq<2> MCLK

freq<1> MCLK

freq<0> PopGuard

Disable

001 1 0 0 0 0

04h Serial Format ADC HPF

Freeze A ADC HPF

Freeze B Digital

Loopback DAC_DIF1 DAC_DIF0 Reserved Reserved ADC_DIF0

000 0 0 0 0 0

05h Transition

Control DAC

Single Vol soft_dac zc_dac Invert ADC

ch B Invert ADC

ch A Invert DAC

ch B Invert DAC

ch A De-Emph

011 0 0 0 0 0

06h Mute Reserved Reserved Auto Mute Mute ADC

SP ch B Mute ADC

SP ch A Mute

Polarity Mute DAC

ch B Mute DAC

ch A

001 0 0 0 0 0

07h Vol Ctrl

AOUTA dacA

vol<7> dacA

vol<6> dacA

vol<5> dacA

vol<4> dacA

vol<3> dacA

vol<2> dacA

vol<1> dacA

vol<0>

000 0 0 0 0 0

08h Vol Ctrl

AOUTB dacB

vol<7> dacB

vol<6> dacB

vol<5> dacB

vol<4> dacB

vol<3> dacB

vol<2> dacB

vol<1> dacB

vol<0>

000 0 0 0 0 0

DS686PP1 35

CS4270

8. REGISTER DESCRIPTION

** All registers are read /write in I²C Mode and SPI Mode, unless otherwise noted**

8.1 Chip ID - Address 01h

Function:

This register is Read-Only. Bits 7 thr ough 4 are the part number ID which is 1100b (01h) and the rema ining

bits (b3:b0) are for the chip revision.

8.2 Power Control - Address 02h

8.2.1 Freeze (Bit 7)

Function:

This function allows modifications to be made to certain Control Port bits without the changes taking effect

until the Freeze bit is disabled. To make multip le changes to these bits take effect simultaneously, set the

Freeze bit, make all changes, then clear the Freeze bit. T he bits affected by the F reeze function are liste d

below:

– Register 05h (Bits 7:0)

– Register 06h (Bits 7:0)

– Register 07h (Bits 7:0)

– Register 08h (Bits 7:0)

8.2.2 PDN_ADC (Bit 5)

Function:

The ADC portion of the device will enter a low-power state whenever this bit is set.

8.2.3 PDN_DAC (Bit 1)

Function:

The DAC portion of the device will enter a low-power state whenever this bit is set.

8.2.4 Power Down (Bit 0)

Function:

The device will enter a low-power state whenever this bit is set. The c ontents of the control registers are

retained when the device is in power-down.

76543210

id<3> id<2> id<1> id<0> rev<3> rev<2> rev<1> rev<0>

76543210

Freeze Reserved PDN_ADC Reserved Reserved Reserved PDN_DAC PDN

36 DS686PP1

CS4270

8.3 Mode Control - Address 03h

8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4)

Function:

In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control

Port Slave Mode, the CS4270 auto-detects speed mode.

8.3.2 Ratio Select (Bits 3:1)

Function:

These bits are used to select the clocking ratios.

8.3.3 Popguard Disable (Bit 0)

Function:

Disables Popguard when set. Popguard is enabled by default.

8.4 ADC and DAC Control - Address 04h

8.4.1 ADC HPF Freeze A (Bit 7)

Function:

When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC

offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “High-

Pass Filter and DC Offset Calibration” on page 26.

76543210

Reserved Reserved FM_&_M/S_

Mode1 FM_&_M/S_

Mode0 MCLK freq<2> MCLK freq<1> MCLK freq<0> Popguard

Disable

FM_&_M/S_

Mode1 FM_&_M/S_

Mode0 Mode

Single-Speed Mode: 4 to 54 kHz sample rates

Double-Speed Mode: 50 to 108 kHz sample rates

Quad-Speed Mode: 100 to 216 kHz sample rates

Slave Mode (default)

Table 8. Functional Mode Selectio n

MCLK freq<2> MCLK freq<1> MCLK freq<0> Mode

00 0

Divide by 1 (default)

00 1

Divide by 1.5

01 0

Divide by 2

01 1

Divide by 3

10 0

Divide by 4

Table 9. MCLK Divider Configuration

76543210

ADC HPF

Freeze A ADC HPF

Freeze B Digital

Loopback DAC_DIF1 DAC_DIF0 Reserved Reserved ADC_DIF0

DS686PP1 37
CS4270
8.4.2 ADC HPF Freeze B (Bit 6)
Function:
When this bit is set, the internal high-pass filter  for the selected channel will  be disabled.The current D C
offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “High-
Pass Filter and DC Offset Calibration” on page 26.
8.4.3 Digital Loopback (Bit 5)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
Section 5.2.5 “Internal Digital Loopback” on page 26.
8.4.4 DAC Digital Interface Format (Bits 4:3)
Function:
The DAC Digital Interface Format and the options are detailed in Table 10 and Figures 9 through 11.
8.4.5 ADC Digital Interface Format (Bit 0)
Function:
The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital
Interface Fo r ma t. The options are detailed in Table 11 and may be seen in Figures 9 and 10.
DAC_DIF1 DAC_DIF0 Description Format Figure
0 0 Left-Justified, up to 24-bit data (default) 0 9
0 1 I²S, up to 24-bit data 1 10
1 1 Right-Justified, 16-bit Data 2 11
1 0 Right-Justified, 24-bit Data 3 11
Table 10. DAC Digital Interface Formats
ADC_DIF Description Format Figure
0 Left-Justified, up to 24-bit data (default) 0 9
1 I²S, up to 24-bit data 1 10
Table 11. ADC Digital Interface Formats

38 DS686PP1

CS4270

8.5 Transition Control - Address 05h

8.5.1 DAC Single Volume (Bit 7)

Function:

The AOUTA and AOUTB vo lume levels are independ ently controlled by the A and the B Channel Volume

Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by

the A Channel Volume Control Byte (07h) and the B Channel Byte (08h) is ignored w hen this func tion is

enabled. Volume and muting functions are affected by the Soft Ramp and ZeroCross func tion s be lo w.

8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, both muting and attenuation, to be imp lemented by incrementa lly ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

See Table 12 on page 38.

Zero Cross Enable

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-

out period between 512 an d 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel. See Table 9 on page 36.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out per iod betwe en 512 an d 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-

ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-

itored and implemented for each channel. See Table 9 on page 36.

8.5.3 Invert Signal Polarity (Bits 4:1)

Function:

When set, this bit activates an inversion of the signal polar ity for the ap propr iate ch annel. This is useful if

a board layout error has occurred or in other situations where a 180 degr ee phase shift is desirable.

76543210

DAC Single

Volume soft_dac zc_dac invert

ADC ch B invert

ADC ch A invert

DAC ch B invert

DAC ch A De-emph

Soft ZeroCross Mode

0 0 Changes to affect immediately

0 1 Zero Cross enabled

1 0 Soft Ramp enabled

1 1 Soft Ramp and Zero Cross enabled

(default)

Table 12. Soft Cross or Zero Cross Mode Selection

DS686PP1 39

CS4270

8.5.4 De-Emphasis Control (Bit 0)

Function:

Implementation of the sta ndard 50/15 µs digital de-emphasis filter on the DAC output requires reconfigu-

ration of the digital filter to maintain the proper filter response for 44.1 kHz sample rate. Figure 23 shows

the filter response. NOTE: De-emphasis is available only in Single-Speed Mode.

8.6 Mute Control - Address 06h

8.6.1 Auto-Mute (Bit 5)

Function:

When set, enables the Auto-Mute function. Section 5.2.6 “Auto-Mute” on page 26.

8.6.2 ADC Channel A & B Mute (Bits 4:3)

Function:

When this bit is set, the output of the ADC for the selected channel will be muted.

8.6.3 Mute Polarity (Bit 2)

Function:

The MUTEA and MUTEB pins (pins 24 and 21) are active low by default. When this bit is set, these pins

are active high.

8.6.4 DAC Channel A & B Mute (Bits 1:0)

Function:

When this bit is set, the output of the DAC for the selected channel will be muted.

76543210

Reserved Reserved Auto Mute Mute ADC SP

ch B Mute ADC SP

ch A mute polarity Mute DAC SP

ch B Mute DAC SP

ch B

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 23. De-Emphasis Curve

40 DS686PP1

CS4270

8.7 DAC Channel A Volume Control - Address 07h

Function:

See Section 8.8 DAC Channel B Volume Control - Address 08h.

8.8 DAC Channel B Volume Control - Address 08h

Function:

The digital volume control allows the user to attenua te the signal in 0.5 dB increments from 0 to -127 dB.

The vol<0> bit activates a 0.5 dB attenuation when set, and no atte nuation when cleared. The Vol[7:1]

bits activate attenuation equal to their decimal value (in dB). Example volume settings are decoded as

shown in Table 13. The volume changes are implemented as dictated by the DACSoft and DACZero-

Cross bits in the Transition Control register (see Section 8.5.2).

76543210

dacA

vol<7> dacA

vol<6> dacA

vol<5> dacA

vol<4> dacA

vol<3> dacA

vol<2> dacA

vol<1> dacA

vol<0>

76543210

dacB

vol<7> dacB

vol<6> dacB

vol<5> dacB

vol<4> dacB

vol<3> dacB

vol<2> dacB

vol<1> dacB

vol<0>

Binary Code Volume Setting

00000000 0 dB

00000001 -0.5 dB

00101000 -20 dB

00101001 -20.5 dB

11111110 -127 dB

11111111 -127.5 dB

Table 13. Digital Volume Control

DS686PP1 41

CS4270

9. FILTER PLOTS

Figure 24. DAC Single-Speed Stopband Rejection Figure 25. DAC Single-Speed Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

Frequency (normalized to Fs)

Amplitude dB

00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-0.25

-0. 2

-0.15

-0. 1

-0.05

0.05

Frequency (normalized to Fs)

Amplitude dB

Figure 26. DAC Single-Speed Transition Band (detail) Figure 27. DAC Single-Speed Passband Ripple

Figure 28. DAC Double-Speed Stopband Rejection Figure 29. DAC Double-Speed Transition Band

42 DS686PP1

CS4270

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

- 10

- 9

- 8

- 7

- 6

- 5

- 4

- 3

- 2

- 1

Frequency (normalized to Fs)

Amplitude dB

00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-0. 2

-0. 1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Frequency (normalized to Fs)

Amplitude dB

Figure 30. DAC Double-Speed Transition Band (detail) Figure 31. DAC Double-Speed Passband Ripple

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Amplitude (dB)

Frequency(normalized to Fs)

0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75

-60

-50

-40

-30

-20

-10

Amplitude (dB)

Frequency(normalized to Fs)

Figure 32. DAC Quad-Speed Stopband Rejection Figure 33. DAC Quad-Speed Transition Band

0.4 0.45 0.5 0.55 0.6 0.65 0.7

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

Amplitude (dB)

Frequency(normalized to Fs)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-1. 5

-1

-0. 5

Frequency (normalized to Fs)

Amplitude dB

Figure 34. DAC Quad-Speed T ransition Band (detail) Figure 35. DAC Quad-Speed Passband Ripple

DS686PP1 43

CS4270

Figure 36. ADC Single-Speed Stopband Rejection Figure 37. ADC Single-Speed Stopband (detail)

-140

-130

-120

- 110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (norma lized to Fs)

Amplitude (dB)

-140

-130

-120

- 110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 38. ADC Single-Speed Tr ansition Band (detail) Figure 39. ADC Single-Speed Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0 0.050.10.150.20.250.30.350.40.450.5

Frequency (normali zed to Fs)

Amplitude (dB)

Figure 40. ADC Double-Speed Stopband Rejection Figure 41. ADC Double-Speed Stopband (detail)

-140

-130

-120

- 110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (norma lized to Fs)

Amplitude (dB)

-140

-130

-120

- 110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

44 DS686PP1

CS4270

Figure 42. ADC Double-Speed Transition Band (detail) Figure 43. ADC Double-Speed Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.46 0.47 0.48 0.49 0.50 0.51 0.52

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 44. ADC Quad-Speed Stopband Rejection Figure 45. ADC Quad-Speed Stopband (detail)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normali zed to Fs)

Amplitude (dB)

-140

-130

-120

- 110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85

Frequency (norma lized to Fs)

Amplitude (dB)

Figure 46. ADC Qu ad-Speed Transition Band (detail) Figure 47. ADC Quad-Speed Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28

Frequency (normalized to Fs)

Amplitude (dB)

DS686PP1 45

CS4270

10.PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.

Dynamic Range is a signal -to-noise r atio measurem ent over the spe cified ba ndwidth made with a -60 dBFS signal.

60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the

distortion components are below the noise level and do not affect the measurement. This measurement technique

has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Ja-

pan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the sig nal to the rms sum of all other spectral comp onents over the specified bandwidth

(typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS

as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz.

Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output

with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

46 DS686PP1

CS4270

11.PACKAGE DIMENSIONS

Notes:

1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not ex ceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Da mbar intrusion shall not re-

duce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A----0.47----1.20

A1 0.00197 0.00394 0.00591 0.05 0.10 0.15

A2 0.03150 0.0394 0.04137 0.80 1.00 1.05

b 0.00748 0.00965 0.01182 0.19 0.245 0.30 2,3

D 0.30338 BSC 0.30732 BSC 0.31126 BSC 7.70 BSC 7.80 BSC 7.90 BSC 1

E 0.24822 0.25216 0.25610 6.30 6.40 6.50

E1 0.16942 0.17336 0.17730 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.01970 0.02364 0.02955 0.50 0.60 0.75

µ0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

DS686PP1 47

CS4270

12.ORDERING INFORMATION

13.REVISION HISTORY

Product Description Package Pb-Free Grade Tem p Range Container Order #

CS4270 24-Bit 192 kHz Stereo

Audio CODEC 24-TSSOP YES Commercial -10° to +70° C Rail CS4270-CZZ

Tape & Reel CS4270-CZZR

CS4270 24-Bit 192 kHz Stereo

Audio CODEC 24-TSSOP YES Automotive -40° to +85° C Rail CS4270-DZZ

Tape & Reel CS4270-DZZR

CDB4270 CS4270 Evaluation Board -- - - -CDB4270

Release Changes

A1 Initial Release

48 DS686PP1
CS4270
PP1
– U pdate Release after B0 chip validation
– Changed value of A/D shunt capacitor from 2200 pF to 220 pF in Figure 18
– Added “single ended input” to “A/D Features” on page 1 and “single ended output” to “D/A 
Features” on pa ge 1
– Added “3.3 V or 5 V core supply” to “System Features” on page 1
– Added package/grade & ordering info to “General Description” on page 2
– Changed note 2. in Figure 1
– Moved ordering info to Section 12
– Moved Typical Connection Diagram to Section 3
– Removed SOIC data from Thermal Characteristics Table  on page 9
– Changed DAC THD+N specs in “DAC Analog Characteristics - Commercial Grade” on 
page 10 and “DAC Analog Characteristics - Automotive Gr ade” on page 10
– Changed DAC Full Scale Output Voltage specs in “DAC Analog Characteristics - all Modes” 
on page 11
– Revised specifications in “DAC Combined Interpolatio n & on-Chip Analog FIlter Response” 
on page 12
– Changed A/D THD+N and  Full Scale  Input Voltage  specs in “ADC Analog Characteristics - 
Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on 
page 14
– Specified A/D input circuit for performance specs in “ADC Analog Characteristics - 
Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on 
page 14
– Revised specifications in “ADC Digital Filter CharacteristicS” on page 15
– C hanged PSRR spec in “DC Electrical Characteristics” on page 16
– Revised Serial Audio Port specifications and acronyms in “Switching Characteristics - Serial 
Audio Port” on page 17
– Replaced serial port timing diagrams with Figure 4, Figure 5, Figure 6, Figure 7 and 
Figure 8, revised Note 17 and Note 18.
– Revised power up sequen ce text in “Recommended Power-Up Sequence - Access to 
Control Port Mode” on page 24
– Changed  text in “Input Connections” on page 28 to specify maximum source impedance for 
A/D performance specifications in the A/D Specification Tables
– Added “A/D THD+N Performance vrs. Input Source Resistance” on page 28 and “A/D 
Dynamic Range vrs. Input Source Resistance” on page 29
– Revised text in “Input Connections” on page 28 that describes A/D input attenuator (resistor 
divider) circuit
–Replaced Figure 18 on page 30
– Moved Parameter Definitions to Section 10
– M oved “Filter Plots” to Section 9 and updated all plots
– Moved “Package Dimensions” to Section 11 and updated dimensions data
Release Changes

DS686PP1 49

CS4270

Contacting Cirrus Logic Support

For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.

To find the one nearest to you, go to www.cirrus.com.

IMPORTANT NOTICE

"Prelimina ry" product inform ation de scribes prod ucts that are in prod uction, but for w hich full character ization data is not yet availa ble. Cirrus Log ic, Inc. and its sub-

sidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without no tice an d

is provi ded "AS IS" withou t warranty of any k ind (express or implied). Customer s are advised t o obtain the lates t version of r elevant information to verify, before

placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order

acknowledg me nt, includ in g those pertai ning to warra nty, inde mn ific ation, a nd lim itation o f lia bility . N o res pon sibi lity is a ss um ed by C irrus for the use of this info rma -

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made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to

other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

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THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in t his document may be

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