AP138
300mA Low-Noise CMOS LDO
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Oct 29, 2004
1/7
Features
- Very low dropout voltage
- Low current consumption: Typ.30µA, Max. 35µA
- Output voltage: 1.8V, 2.5V, 2.8V, 3.0V and 3.3V
- High accuracy output voltage: ±1.5%
- Guaranteed 300mA output
- Input range up to 7.0V
- Thermal shutdown
- Current limiting
- Stability with low ESR capacitors
- Factory pre-set output voltages
- Low temperature coefficient
- Pb-free package: SOT23-5L
Applications
- Battery-powered devices
- Personal communication devices
- Home electric/electronic appliances
- PC peripherals
General Descriptions
The AP138 is a positive voltage linear regulator
utilizing CMOS technology. The features that
include low quiescent current (30µA typ.), low
dropout voltage, and high output voltage accuracy,
make it ideal for battery applications. EN input
connected to CMOS has low bias current. The
space-saving SOT23-5L package is attractive for
“Pocket” and “Hand Held” applications.
This rugged device has both thermal shutdown, and
current limit protections to prevent device failure
under the “Worst” operating conditions.
In a low noise, regulated supply application, a
1000pF capacitor is necessary to be placed in
between Bypass and Ground.
The AP138 is stable with a low ESR output
capacitor of 1.0µF or greater.
Pin Assignments
1 32
5 4
BYP
V
IN
EN
GND
V
OUT
AP138
SOT23-5
(Top View)
Pin Descriptions
Pin
Name
Pin
No. Function
VIN 1 Power Supply
GND 2 Ground
EN 3 Enable Pin
BYP 4 Bypass Signal Pin
VOUT 5 Output
Ordering Information
AP138 XX X X
W : SOT23-5L
Output voltage Package
18: 1.8V
25: 2.5V
28: 2.8V
30: 3.0V
33: 3.3V
Blank: Tube
A: Taping
Packing
AP138
300mA Low-Noise CMOS LDO
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Oct 29, 2004
2/7
Block Diagram
Current
Limit
Thermal
Shutdown
AMP
+
-
Vref
BYP
EN
1uA
V
OUT
GND
V
IN
R1
R2
Absolute Maximum Ratings
Symbol Parameter Rating Unit
VCC Input Voltage +7 V
IOUT Output Current PD/ (VIN-VO) mA
VOUT Output Voltage GND - 0.3 to VIN+ 0.3 V
ESD Classification B
TA Ambient Temperature Range -40 to +85 ºC
TJ Junction Temperature Range -40 to +125 ºC
Thermal Information
Symbol Parameter Maximum Unit
θjc Thermal Resistance SOT23-5L 160 ºC/W
PD Internal Power Dissipation (∆T=100 ºC) SOT23-5L 250 mW
TJ Maximum Junction Temperature 150 ºC
TLead Maximum Lead Temperature (10 sec) 300 ºC
AP138
300mA Low-Noise CMOS LDO
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Oct 29, 2004
3/7
Electrical Characteristics
(TA=+25ºC, unless otherwise noted.)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIN Input Voltage Note 1 - 7 V
VOUT Output Voltage Accuracy IO=1mA to 300mA -1.5 - 1.5 %
1.2V<VO(NOM)
≤ 2.0V - - 1300
2.0V<VO(NOM)
≤ 2.5V - - 800
VDROPOUT Dropout Voltage IO=1mA to 300mA,
VOUT=VO(NOM)-1.5%
2.5V<VO(NOM) - - 300
mV
IOUT Output Current VOUT > 1.2V 300 - - mA
ILIMIT Current Limit VOUT > 1.2V 300 450 - mA
IQ Quiescent Current IO=0mA - 30 35 µA
IGND Ground Pin Current IO=1mA to 300mA - 30 50 µA
REGLINE Line Regulation IOUT=5mA, VIN=VOUT+1 to VOUT+2 -0.1 0.02 0.1 %
REGLOAD Load Regulation IO=1mA to 300mA - 0.2 1 %
OTS Over Temperature
Shutdown - 150 - oC
OTH Over Temperature
Hysteresis - 30 -
oC
TC VOUT Temperature
Coefficient - 40 - ppm/ oC
f=1KHz - 60 -
f=10KHz - 50 -
PSRR Power Supply Rejection IO=100mA,
CO=2.2µF ceramic f=100KHz - 40 -
dB
f=1KHz - 75 -
f=10KHz - 55 -
PSRR Power Supply Rejection
IO=100mA,
CO=2.2µF ceramic,
CBYP=0.01µF f=100KHz - 30 -
dB
CO=2.2uF - 30 -
eN Output Voltage Noise f=10Hz to 100kHz,
IO=10mA, CBYP=0µF CO=100uF - 20 -
µVrms
CO=2.2uF - 30 -
eN Output Voltage Noise f=10Hz to 100kHz,
IO=10mA, CBYP=0.01µF CO=100uF - 20 -
µVrms
ISD Shutdown Supply
Current VIN=5.0V, VOUT=0V, VEN < VEL - 2.0 3.0 µA
IEH V
EN=VIN, VIN=2.6V to 7V - - 0.1 µA
IEL EN Input Bias Current VEN=0V, VIN=2.6V to 7V - 2.0 3.0 µA
VEH V
IN=2.6V to 7V 2 - VIN V
VEL EN Input Threshold VIN=2.6V to 7V 0 - 0.4 V
Note 1. : VIN(MIN)=VOUT+VDROPOUT
Typical Application
AP138
BYP EN
V
OUT
GND
V
IN
C1
1uF
C2
1nF
C3
1uF
IN OUT
AP138
300mA Low-Noise CMOS LDO
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Oct 29, 2004
4/7
Typical Performance Characteristics
AP138
300mA Low-Noise CMOS LDO
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Oct 29, 2004
5/7
Typical Performance Characteristics (Continued)
AP138
300mA Low-Noise CMOS LDO
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Oct 29, 2004
6/7
Function Description
The AP138 of CMOS regulators contain a PMOS
pass transistor, voltage reference, error amplifier,
over-current protection, thermal shutdown.
The P-channel pass transistor receives data from
the error amplifier, over-current protection, and
thermal protection circuits. During normal operation,
the error amplifier compares the output voltage to a
precision reference. Over-current and thermal
shutdown circuits become active when the junction
temperature exceeds 150oC, or the current exceeds
300mA. During thermal shutdown, the output
voltage remains low. Normal operation is restored
when the junction temperature drops below 120oC.
The AP138 switches from voltage mode to current
mode when the load exceeds the rated output
current. This prevents over-stress.
Enable
The enable pin normally floats high. When actively,
pulled low, the PMOS pass transistor shut off, and
all internal circuits are powered down. In this state,
the quiescent current is less than 2µA. This pin
behaves much like an electronic switch.
External Capacitor
The AP138 is stable with a low ESR output
capacitor to ground of 1.0µF or greater. It can keep
stable even with higher ESR capacitors. A second
capacitor is recommended between the input and
ground to stabilize VIN. The input capacitor should
be larger than 0.1µF to have a beneficial effect. All
capacitors should be placed in close proximity to
the pins. A “quiet” ground termination is desirable.
Marking Information
X : Identification code
(See Appendix)
Y : Year: 0-9
W : Week: A~Z: 01~26
a~z : 27~52
. : 53
SOT23-5L
3 8 X Y W
7
12
3
45
Appendix
Identification
Code Output version
D AP138-1.8V
K AP138-2.5V
N AP138-2.8V
P AP138-3.0V
S AP138-3.3V
AP138
300mA Low-Noise CMOS LDO
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Oct 29, 2004
7/7
Package Information
Package Type: SOT23-5L
θ
Gauge Plane
0.25 mm
L
L1
E1 E
e1
D
123
4
5
b
e
b1
b
CC1
Base
Metal
With
Plating
A2
A1
A
Seating Plane
0.10 C
5x
2(4x)
θ
1(4x)
θ
Dimensions In Millimeters Dimensions In Inches
Symbol Min. Nom. Max. Min. Nom. Max.
A 1.05 1.20 1.35 0.041 0.047 0.053
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 1.00 1.10 1.20 0.039 0.043 0.047
b 0.25 - 0.55 0.010 - 0.022
b1 0.25 0.40 0.45 0.010 0.016 0.018
c 0.08 - 0.20 0.003 - 0.008
c1 0.08 0.11 0.15 0.003 0.004 0.006
D 2.70 2.85 3.00 0.106 0.112 0.118
E 2.60 2.80 3.00 0.102 0.110 0.118
E1 1.50 1.60 1.70 0.059 0.063 0.067
L 0.35 0.45 0.55 0.014 0.018 0.022
L1 0.60 Ref. 0.024 Ref.
e 0.95 Bsc. 0.037 Bsc.
e1 1.90 Bsc. 0.075 Bsc.
θ 0
o 5
o 10o 0
o 5
o 10o
θ1 3o 5
o 7
o 3
o 5
o 7
o
θ2 6o 8
o 10o 6
o 8
o 10o
