CY62137VSL-70ZI - Cypress Semiconductor Corp.

2-Mbit (128K x 16) Static RAM

CY62137V MoBL®

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05051 Rev. *D Revised May 18, 2005

Features

• Temperature Range s

— Commercial: 0°C to 70°C

— Industrial: –40 °C to 85°C

— Automotive: –40°C to 125°C

• High Speed: 55 ns and 70 ns

• Wide voltage range: 2.7V–3.6V

• Ultra-low active, standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/po we r

• Package Available in a standard 44-pin TSOP Type II

(forward pinout) package

Functional Description[1]

The CY62137V is a high-performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular te lephones. Th e device

also has an automatic power-down feature that reduces power

consumption by 99% when addresses are not toggling. The

device can also be put into standby mode when deselected

(CE HIGH) or when CE is LOW and both BLE and BHE are

HIGH. The input/output pins (I/O0 through I/O15) are placed in

a high-impedance state when: deselected (CE HIGH), outputs

are disabled (OE HIGH), BHE and BLE are disabled (BHE,

BLE HIGH), or during a write operation (CE LOW, and WE

LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is

written into the location specified on the address pins (A0

through A16). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8 through I/O15) is written into the location

specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified b y the address

pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) i s

LOW , then data from memory will appear on I/O8 to I/O15. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

128K x 16

RAM Array I/O0–I/O7

ROW DECODER

COLUMN DECODER

A11

A12

A13

A14

A15

2048 x 1024

SENSE AMPS

DATA IN DRIVERS

A3I/O8–I/O15

BLE

BHE

A16

Power-down

Circuit BHE

BLE

A10

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 2 of 11

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating, ICC

(mA) Standby, ISB2

(µA)

Min. Typ.[3] Max. Typ.[3] Max. Typ.[3] Max.

CY62137VLL Industrial 2.7 3.0 3.6 55 7 20 1 15

CY62137VSL 55 7 20 1 5

CY62137VLL 70 7 15 1 15

CY62137VSL 70 7 15 1 5

CY62137VLL Automotive 70 7 15 1 20

Pin Configurations

14 31

Top View

TSOP II (Forward)

15 29

VCC

A16

A15

A14

A13

VSS

I/O15

I/O2

I/O0

I/O1

BHE

I/O3

21 23

24 NC

VSS

I/O6

I/O4

I/O5

I/O7

BLE

VCC

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

A10

A11

A12

Pin Definitions

Pin Number Type Description

1–5, 18–22, 24–27, 42–45 Input A0–A16. Address Inputs

7–10, 13–16, 29–32, 35–38 Input/Output I/O0–I/O15. Data lines. Used as input or output lines depending on operation

23 No Connect NC. This pin is not connected to the die

17 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ

is conducted

6 Input/Control CE. When LOW, selects the chip. When HIGH, deselect s the chip

39, 40 Input/Control BHE, BLE. BHE = LOW selects higher order byte WRITEs or READs on the

SRAM.BLE = LOW selects lower order byte WRITEs or READs on the SRAM

41 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW , the I/O pins

behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as

input data pins

12, 34 Ground VSS. Ground for the device

11, 33 Power Supply VCC. Power supply for the devic e

Notes:

2. NC pins are not connected on the die.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP)., TA = 25°C.

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 3 of 11

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +4.6V

DC Voltage Applied to Outputs

in High-Z S tate[4]....................................–0.5V to VCC + 0.5V

DC Input V oltage[4].................................–0.5V to VCC + 0.5V

Output Current into Outp uts (LOW).............................20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient

Temperature VCC

Industrial –40°C to +85°C 2.7V to 3.6V

Automotive –40°C to +125°C 2.7V to 3.6V

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions CY62137V-55 CY62137V-70 UnitMin. Typ.[3] Max. Min. Typ.[3] Max.

VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.5V 2.2 VCC +

0.5V V

VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 V

IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA

IOZ Output Leakage

Current GND < VO < VCC,

Output Disabled –1 +1 –1 +1 µA

ICC VCC Operating Suppl y

Current IOUT = 0 mA,

f = fMAX = 1/tRC,

CMOS Levels

VCC = 3.6V 7 20 7 15 mA

IOUT = 0 mA, f = 1

MHz, CMOS Levels 12 12mA

ISB1 Automatic CE

Power-down

Current—CMOS

Inputs

CE > VCC – 0.3V,

VIN > VCC – 0.3V or

VIN < 0.3V, f = fMAX

VCC = 3.6V 100 100 µA

ISB2 Automatic CE

Power-down

Current—CMOS

Inputs

CE > VCC – 0.3V

VIN > VCC – 0.3V

or VIN < 0.3V, f = 0

VCC =

3.6V LL 1 15 1 15

Automotive 1 20

SL 1 5 1 5

Capacitance[5]

Parameter Description Tes t Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = VCC(typ) 6pF

COUT Output Capacitance 8 pF

Thermal Resistance

Parameter Description Test Conditions TSOPII Unit

ΘJA Thermal Resistance

(Junction to Ambient)[5] Still Air, soldered on a 4.25 x 1.125 inch, 4-layer

printed circuit board 60 °C/W

ΘJC Thermal Resistance

(Junction to Case)[5] 22 °C/W

Notes:

4. VIL(min.) = –2.0V for pulse durations less than 20 ns.

5. Tested initially and afte r any design or process changes that may affect th ese parameters.

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 4 of 11

AC Test Loads and Waveforms

VCC Typ

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

OUTPUT V

Equivalent to: THÉ VENINEQUIVALENT

ALL INPUT PULSES

RTH

R1 VCC

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE (b)

(a)

Rise Time:

1 V/ns Fall Time:

1 V/ns

(c)

Parameters 3.0V Unit

R1 1105 Ohms

R2 1550 Ohms

RTH 645 Ohms

VTH 1.75 Volts

Data Retention Characteristics (Over the Operating Range )

Parameter Description Conditions Min. Typ.[3] Max. Unit

VDR VCC for Data Retention 1.0 V

ICCDR Data Retention Current VCC = 1.0V, CE > VCC – 0.3V , VIN > VCC – 0.3V

or VIN < 0.3V ; No input may exceed; VCC+0.3V LL 0.5 7.5 µA

Automotive 10

SL 0.5 5

tCDR[5] Chip Deselect to Data

Retention Time 0ns

tROperation Recovery Time 70 ns

Data Retention Waveform

VCC(min.)VCC(min.)

tCDR

VDR >1.0 V

DATA RETENTION MODE

VCC

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 5 of 11

Switching Characteristics Over the Operating Range [6]

Parameter Description

55 ns 70 ns

UnitMin. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 55 70 ns

tAA Address to Data Valid 55 70 ns

tOHA Data Hold from Address Change 10 10 ns

tACE CE LOW to Data Val i d 55 70 ns

tDOE OE LOW to Data Valid 25 35 ns

tLZOE OE LOW to Low-Z[7] 55ns

tHZOE OE HIGH to High-Z[7, 8] 25 25 ns

tLZCE CE LOW to Low-Z[7] 10 10 ns

tHZCE CE HIGH to High-Z[7, 8] 25 25 ns

tPU CE LOW to Power-up 0 0 ns

tPD CE HIGH to Power-down 55 70 ns

tDBE BHE / BLE LOW to Data Valid 55 70 ns

tLZBE (9) BHE / BLE LOW to Low-Z 5 5 ns

tHZBE BHE / BLE HIGH to High-Z 25 25 ns

Write Cycle[10, 11]

tWC Write Cycle Time 55 70 ns

tSCE CE LOW to Write End 45 60 ns

tAW Address Set-up to Write End 45 60 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-up to Write Start 0 0 ns

tPWE WE Pulse Wid th 40 50 ns

tSD Data Set-up to Write End 25 30 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High-Z[7, 8] 20 25 ns

tLZWE WE HIGH to Low-Z[7] 510ns

tBW BHE / BLE LOW to End of Write 50 60 ns

Notes:

6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to VCC typ., and output loading of the specified

IOL/IOH and 30 pF load capacitan c e .

7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

9. If both byte enables are toggled together this value is 10 ns.

10.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal ca n

terminate a writ e by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

11.The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 6 of 11

Switching Waveforms

Read Cycle No. 1[12, 13]

Read Cycle No. 2[13, 14]

Notes:

12.Device is continuously selected. OE, CE = VIL.

13.WE is HIGH for read cycle.

14.Address valid prior to or coincident with CE transition LOW.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

tRC

tACE

tDBE

tLZBE

tLZCE

tPU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE

tHZCE

tPD

HIGH

VCC

SUPPLY

CURRENT

tHZBE

BHE/BLE

tDOE

tLZOE

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 7 of 11

Write Cycle No. 1 (WE Controlled)[10, 15, 16]

Write Cycle No. 2 (CE Controlled)[10, 15, 16]

Notes:

15.Data I/O is high-impedance if OE = VIH.

16.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

17.During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN VALID

NOTE17

BHE/BLE tBW

tWC

tAW

tSA tHA

tHD

tSD

tSCE

DATA I/O

ADDRESS

DATAIN VALID

BHE/BLE tBW

tPWE

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 8 of 11

Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]

Switching Waveforms (continued)

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATAIN VALID

NOTE 17

BHE/BLE tBW

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATAIN VALID

tBW

BHE/BLE

NOTE 17

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 9 of 11

Typical DC and AC Characteristics

1.0 1.9 2.8 3.7

ISB (µA)

1.2

1.4

1.0

0.6

0.4

0.2

1.7 2.2 2.7 3.2 3.7

0.0

0.8

ICC

1.0 1.9 2.8 3.7

SUPPLY VOLTAGE (V)

Access Time vs. Supply Voltage

TAA (ns)

Normalized Operating Current

Standby Current vs. Supply Voltage

SUPPLY VOLTAGE (V)

MoBL

vs. Supply Voltage

2.7

Truth Table

CE WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X High-Z Deselect/Power-down Standby (ISB)

L X X H H High-Z Deselect/Power-down Standby (ISB)

L H L L L Data Out (I/OO–I/O15) R ead Active (ICC)

LHLHLData Out (I/O

O–I/O7);

I/O8–I/O15 in High-Z Read Active (ICC)

L H L L H Data Out (I/O8–I/O15);

I/O0–I/O7 in High-Z Read Active (ICC)

L H H L L High-Z Deselect/Output Disabled Active (ICC)

L H H H L High-Z Deselect/Output Disabled Active (ICC)

L H H L H High-Z Deselect/Output Disable d Active (ICC)

L L X L L Data In (I/OO–I/O15) Write Active (ICC)

L L X H L Data In (I/OO–I/O7);

I/O8–I/O15 in High-Z Write Active (ICC)

L L X L H Data In (I/O8–I/O15);

I/O0 –I/O7 in High-Z Write Active (ICC)

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 10 of 11

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agree ment with Cypr ess. Furthermore , Cypress does no t authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

MoBL is a registered trademark, and More Battery Li fe is a tra demark, of Cypress Semicond uctor C orporation. All product a nd

company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

55 CY62137VLL-55ZI ZS44 44-pin TSOP II Industrial

CY62137VLL-55ZXI 44-pin TSOP II (Pb-free)

CY62137VSL-55ZI 44-pin TSOP II

70 CY62137VLL-70ZI 44-pin TSOP II

CY62137VLL-70ZXI 44-pin TSOP II (Pb-free)

CY62137VSL-70ZI 44-pin TSOP II

CY62137VLL-70ZE 44-pin TSOP II Automotive

CY62137VLL-70ZSXE 44-pin TSOP II (Pb-free)

Package Diagrams

MAX

MIN.

DIMENSION IN MM (INCH)

11.938 (0.470)

PLANE

SEATING

PIN 1 I.D.

18.517 (0.729)

0.800 BSC

0°-5°

0.400(0.016)

0.300 (0.012)

EJECTOR PIN

11.735 (0.462)

10.058 (0.396)

10.262 (0.404)

1.194 (0.047)

0.991 (0.039)

0.150 (0.0059)

0.050 (0.0020)

(0.0315)

18.313 (0.721)

10.058 (0.396)

10.262 (0.404)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

BASE PLANE

0.10 (.004)

TOP VIEW BOTTOM VIEW

44-Pin TSOP II ZS44

51-85087-*A

CY62137V MoBL®

Document #: 38-05051 Rev. *D Page 11 of 11

Document History Page

Document Title: CY62137V MoBL® 2M (128K x 16) Static RAM

Document Number: 38-05051

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 109960 10/03/01 SZV Changed from Spec number: 38-00738 to 38-05051

*A 116788 09/04/02 GBI Added footnote number one.

Added SL power bin.

Deleted fBGA package; replacement fBGA package is available in

CY62137CV30.

*B 237428 See ECN AJU Added Automotive prod uct information

*C 329640 See ECN AJU Change d TSOPII package name from Z44 to ZS44

Added Pb-free ordering information

*D 372074 See ECN SYT Added Pb-free ordering information for Automotive