1
Data sheet acquired from Harris Semiconductor
SCHS212D
CD54HC4316, CD74HC4316,
CD74HCT4316
High-Speed CMOS Logic
Quad Analog Switch with Level Translation
Features
Wide Analog-Input-Voltage Range
VCC - VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 10V
Low “ON” Resistance
-45 (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . .VCC = 4.5V
-35 (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC = 6V
-30 (Typ). . . . . . . . . . . . . . . . . . . . . . . VCC - VEE = 9V
Fast Switching and Propagation Delay Times
Low “OFF” Leakage Current
Built-In “Break-Before-Make” Switching
Logic-Level Translation to Enable 5V Logic to
Accommodate ±5V Analog Signals
Wide Operating T emperature Range . . . -55oC to 125oC
HC Types
- 2V to 10V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
HCT Types
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il1µA at VOL, VOH
Description
The ’HC4316 and CD74HCT4316 contain four independent
digitally controlled analog switches that use silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL with the low power consumption of standard CMOS
integrated circuits.
In addition these devices contain logic-level translation
circuits that provide for analog signal switching of voltages
between ±5V via 5V logic. Each switch is turned on by a
high-level voltage on its select input (S) when the common
Enable (E) is Low. A High E disables all switches. The digital
inputs can swing between VCC and GND; the analog
inputs/outputs can swing between VCC as a positive limit
and VEE as a negative limit. Voltage ranges are shown in
Figures 2 and 3.
Pinout CD54HC4316 (CERDIP)
CD74HC4316 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4316 (PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC4316F3A -55 to 125 16 Ld CERDIP
CD74HC4316E -55 to 125 16 Ld PDIP
CD74HC4316M -55 to 125 16 Ld SOIC
CD74HC4316MT -55 to 125 16 Ld SOIC
CD74HC4316M96 -55 to 125 16 Ld SOIC
CD74HC4316NSR -55 to 125 16 Ld SOP
CD74HC4316PW -55 to 125 16 Ld TSSOP
CD74HC4316PWR -55 to 125 16 Ld TSSOP
CD74HC4316PWT -55 to 125 16 Ld TSSOP
CD74HCT4316E -55 to 125 16 Ld PDIP
CD74HCT4316M -55 to 125 16 Ld SOIC
CD74HCT4316MT -55 to 125 16 Ld SOIC
CD74HCT4316M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1Z
1Y
2Y
2Z
2S
3S
GND
E
VCC
4S
4Z
4Y
3Y
3Z
VEE
1S
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
[
/Title
(
CD74
H
C431
6
,
C
D74
H
CT43
1
6)
/
Sub-
j
ect
(
High-
S
peed
C
MOS
2
Functional Diagram
TRUTH TABLE
INPUTS
SWITCHES
L L OFF
LHON
H X OFF
H= High Level Voltage
L= Low Level Voltage
X= Don’t Care
15
5
14
6
4S
3S
2S
1S 1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
7
E
16
VCC
89
VEE
GND
2
1
3
4
11
10
12
13
LOGIC
LEVEL
CONV.
AND
CONTROL
Logic Diagram
FIGURE 1. ONE SWITCH
VCC
VEE
nZ
nY
ELOGIC
LEVEL
CONV.
VCC
VEE
TO 3 OTHER
SWITCHES
nS
CD54HC4316, CD74HC4316, CD74HCT4316CD54HC4316, CD74HC4316, CD74HCT4316
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Supply Voltage, VCC - VEE. . . . . . . . . . . . . . . . . . -0.5V to 10.5V
DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC 0.5V. . . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Switch Diode Current, IOK
For VI < VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA
DC Switch Diode Current
For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
Supply Voltage Range, VCC - VEE
HC, HCT Types (Figure 2) . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
Supply Voltage Range, VEE
HC, HCT Types (Figure 3) . . . . . . . . . . . . . . . . . . . . . . . 0V to -6V
DC Input or Output Voltage, VI. . . . . . . . . . . . . . . . . . . GND to VCC
Analog Switch I/O Voltage, VIS. . . . . . . . . . . . . . . . . . . . . VEE (Min)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC (Max)
Input Rise and Fall Time, tr, tf
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .108oC/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150o
Maximum Storage Temperature Range . . . . . . . . . . . -65oC to 150o
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . . 300o
SOIC - Lead Tips Only
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Area as a Function of Supply Voltage
FIGURE 2. FIGURE 3.
8
6
4
2
0
VCC - GND
(V) HC HCT
024681012
VCC - VEE (V)
8
6
4
2
0
VCC - GND
(V) HC
HCT
0-2-4-6-8
VEE - GND (V)
CD54HC4316, CD74HC4316, CD74HCT4316CD54HC4316, CD74HC4316, CD74HCT4316
4
DC Electrical Specifications
PARAMETER SYMBOL
TEST CONDITIONS 25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) VIS (V) VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
“ON” Resistance
IO = 1mA
(Figures 4, 5)
RON VIH or
VIL VCC or
VEE 0 4.5 - 45 180 - 225 - 270
0 6 - 35 160 - 200 - 240
-4.5 4.5 - 30 135 - 170 - 205
VCC to
VEE 0 4.5 - 85 320 - 400 - 480
0 6 - 55 240 - 300 - 360
-4.5 4.5 - 35 170 - 215 - 255
Maximum “ON”
Resistance Between
Any Two Channels
RON - - 0 4.5-10-----
0 6 -8.5-----
-4.5 4.5 - 5 -----
Switch Off Leakage
Current IIZ VIH or
VIL VCC -
VEE 06--±0.1 - ±1-±1µA
-5 5 - - ±0.1 - ±1-±1µA
Control Input Leakage
Current IIL VCC or
GND -06--±0.1 - ±1-±1µA
Quiescent Device
Current
IO = 0
ICC VCC or
GND When
VIS = VEE,
VOS=VCC
When
VIS=VCC,
VOS =VEE
0 6 - - 8 - 80 - 160 µA
-5 5 - - 16 - 160 - 320 µA
HCT TYPES
High Level Input
Voltage VIH - - - 4.5 to
5.5 2--2-2-V
Low Level Input
Voltage VIL - - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
“ON” Resistance
IO = 1mA
(Figures 4, 5)
RON VIH or
VIL VCC or
VEE 0 4.5 - 45 180 - 225 - 270
-4.5 4.5 - 30 135 - 170 - 205
VCC to
VEE 0 4.5 - 85 320 - 400 - 480
-4.5 4.5 - 35 170 - 215 - 255
Maximum “ON”
Resistance Between
Any Two Channels
RON - - 0 4.5-10-----
-4.5 4.5 - 5 -----
Switch Off Leakage
Current IIZ VIH or
VIL VCC -
VEE 06--±0.1 - ±1-±1µA
-5 5 - - ±0.1 - ±1-±1µA
CD54HC4316, CD74HC4316, CD74HCT4316CD54HC4316, CD74HC4316, CD74HCT4316
5
Control Input Leakage
Current IIVCC or
GND - 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current
IO = 0
ICC Any
Voltage
Be-
tween
VCCand
GND
When
VIS =VEE,
VOS =
VCC,
When
VIS=VCC,
VOS =V
EE
0 5.5 - - 8 - 80 - 160 µA
-4.5 5.5 - - 16 - 160 - 320 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
ICC
(Note 2) VCC
-2.1 - - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT UNIT LOADS
All 0.5
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST CONDITIONS 25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) VIS (V) VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VEE
(V) VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,
Switch In to Out tPLH, tPHL CL= 50pF 0 2 - - 60 - 75 - 90 ns
0 4.5 - - 12 - 15 - 18 ns
0 6 - - 10 - 13 - 15 ns
-4.5 4.5 - - 8 - 10 - 12 ns
Turn “ON” Time E to Out tPZH, tPZL CL= 50pF 0 2 - - 205 - 255 - 310 ns
0 4.5 - - 41 - 51 - 62 ns
0 6 - - 35 - 43 - 53 ns
-4.5 4.5 - - 37 - 47 - 56 ns
CL= 15pF - 5 - 17 -----ns
Turn “ON” Time nS to Out tPZH, tPZL CL= 50pF 0 2 - - 175 - 220 - 265 ns
0 4.5 - - 35 - 44 - 53 ns
0 6 - - 30 - 37 - 45 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL= 15pF - 5 - 14 -----ns
Turn “OFF” Time E to Out tPLZ, tPHZ CL= 50pF 0 2 - - 205 - 255 - 310 ns
0 4.5 - - 41 - 51 - 62 ns
0 6 - - 35 - 43 - 53 ns
-4.5 4.5 - - 37 - 47 - 56 ns
CL= 15pF - 5 - 17 -----ns
CD54HC4316, CD74HC4316, CD74HCT4316CD54HC4316, CD74HC4316, CD74HCT4316
6
Turn “OFF” Time nS to Out tPLZ, tPHZ CL= 50pF 0 2 - - 175 - 220 - 265 ns
0 4.5 - - 35 - 44 - 53 ns
0 6 - - 30 - 37 - 45 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL= 15pF - 5 - 14 -----ns
Input (Control) Capacitance CI- ----10-10-10pF
Power Dissipation Capacitance
(Notes 3, 4) CPD - -5-42-----pF
HCT TYPES
Propagation Delay,
Switch In to Switch Out tPLH, tPHL CL= 50pF 0 4.5 - - 12 - 15 - 18 ns
-4.5 4.5 - - 8 - 10 - 12 ns
Turn “ON” Time E to Out tPZH CL= 50pF 0 4.5 - - 44 - 55 - 66 ns
-4.5 4.5 - - 42 - 53 - 63 ns
CL= 15pF - 5 - 18 -----ns
tPZL CL= 50pF 0 4.5 - - 56 - 70 - 85 ns
-4.5 4.5 - - 42 - 53 - 63 ns
CL= 15pF - 5 - 24 -----ns
Turn “ON” Time nS to Out tPZH CL= 50pF 0 4.5 - - 40 - 53 - 60 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL= 15pF - 5 - 17 -----ns
tPZL CL= 50pF 0 4.5 - - 50 - 63 - 75 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL= 15pF - 5 - 18 -----ns
Turn “OFF” Time E to Out tPLZ CL= 50pF 0 4.5 - - 50 - 63 - 75 ns
-4.5 4.5 - - 46 - 58 - 69 ns
tPLZ, tPHZ CL= 15pF - 5 - 21 -----ns
Turn “OFF” Time nS to Out tPHZ CL= 50pF 0 4.5 - - 44 - 55 - 66 ns
-4.5 4.5 - - 40 - 50 - 60 ns
tPLZ, tPHZ CL= 15pF - 5 - 18 -----ns
Input (Control) Capacitance CI- ----10-10-10pF
Power Dissipation Capacitance
(Notes 3, 4) CPD - -5-47-----pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD=C
PD VCC2fi+Σ(CL+C
S)V
CC2fowhere fi= input frequency, fo= output frequency, CL= output load capacitance, CS= switch
capacitance, VCC = supply voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VEE
(V) VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Analog Channel Specifications TA = 25oC
PARAMETER TEST
CONDITIONS VCC (V) HC4316 CD74HCT4316 UNITS
Switch Frequency Response Bandwidth at -3dB
(Figure 6) Figure 9 (Notes 5, 6) 4.5 >200 >200 MHz
Crosstalk Between Any Two Switches (Figure 7) Figure 8 (Notes 6, 7) 4.5 TBE TBE dB
CD54HC4316, CD74HC4316, CD74HCT4316CD54HC4316, CD74HC4316, CD74HCT4316
7
Total Harmonic Distortion 1kHz, VIS = 4VP-P
(Figure 10) 4.5 0.078 0.078 %
1kHz, VIS = 8VP-P
(Figure 10) 9 0.018 0.018 %
Control to Switch Feedthrough Noise Figure 11 4.5 TBE TBE mV
9 TBE TBE mV
Switch “OFF” Signal Feedthrough (Figure 7) Figure 12 (Notes 6, 7) 4.5 -62 -62 dB
Switch Input Capacitance, CS--5 5pF
NOTES:
5. Adjust input level for 0dBm at output, f = 1MHz.
6. VIS is centered at VCC/2.
7. Adjust input for 0dBm at VIS.
Analog Channel Specifications TA = 25oC (Continued)
PARAMETER TEST
CONDITIONS VCC (V) HC4316 CD74HCT4316 UNITS
Typical Performance Curves
FIGURE 4. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE FIGURE 5. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE
FIGURE 6. SWITCH FREQUENCY RESPONSE FIGURE 7. SWITCH-OFF SIGNAL FEEDTHROUGH AND
CROSSTALK vs FREQUENCY
110
100
90
80
70
60
50
40
30
20
10
01 23454.5
INPUT SIGNAL VOLTAGE, VIS (V)
“ON” RESISTANCE, RON ()
6
VCC = 6V, VEE = 0V
VCC = 4.5V, VEE = 0V
50
45
40
35
30
25
20
15
10
-4.5 -3.5 -2.5 -1.5 -0.5 1.50.5
INPUT SIGNAL VOLTAGE, VIS (V)
“ON” RESISTANCE, RON ()
2.5
VCC = 4.5V, VEE = 4.5V
3.5 4.5
5
0
60
0
-1
-2
-3
-4
10K 100K 1M 10M 100M
FREQUENCY (f), Hz
CHANNEL ON BANDWIDTH, dB
CL = 10pF
VCC = 4.5V
RL = 50
TA = 25oC
PIN 4 TO 3
CL = 10pF
VCC = 9V
RL = 50
TA = 25oC
PIN 4 TO 3
0
-20
-40
-60
-80
10K 100K 1M 10M 100M
FREQUENCY (f), Hz
CROSSTALK, dB
CL = 10pF
VCC = 4.5V
RL = 50
TA = 25oC
PIN 4 TO 3
CL = 10pF
VCC = 9V
RL = 50
TA = 25oC
PIN 4 TO 3
SWITCH OFF SIGNAL FEEDTHROUGH, dB
-100
CD54HC4316, CD74HC4316, CD74HCT4316CD54HC4316, CD74HC4316, CD74HCT4316
8
Analog Test Circuits
FIGURE 8. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT
FIGURE 9. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 10. TOTAL HARMONIC DISTORTION TEST CIRCUIT
FIGURE 11. CONTROL-TO-SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT FIGURE 12. SWITCH OFF SIGNAL FEEDTHROUGH
VCC
VIS
0.1µF
RC
VCC/2
VOS1
SWITCH
ON
VCC
VCC/2
R
RC
VCC/2
VOS2
SWITCH
ON
dB
METER
VIS
fIS = 1MHz SINEWAVE
R = 50
C = 10pF
R
VCC
VIS
0.1µF
5010pF
VCC/2
VOS
SWITCH
ON
dB
METER
VCC
VIS
10µF
10k50pF
VCC/2
VOS
SWITCH
ON
DISTORTION
METER
VI = VIH
fIS = 1kHz TO 10kHz
VIS
SINE
WAVE
SWITCH
ALTERNATING
ON AND OFF
tr, tf 6ns
fCONT = 1MHz
50% DUTY
CYCLE SCOPE
VP-P
VOS
E
VOS
50pF
600
VCC/2
600
VCC/2
VCC VCC
VIS
0.1µF
RC
VCC/2
VOS
SWITCH
ON
dB
METER
R
VCC/2
VC = VIL
fIS 1MHz SINEWAVE
R = 50
C = 10pF
CD54HC4316, CD74HC4316, CD74HCT4316
9
Test Circuits and Waveforms
FIGURE 13. SWITCH PROPAGATION DELAY TIMES FIGURE 14. SWITCH TURN-ON AND TURN-OFF
PROPAGATION DELAY TIMES WAVEFORMS
tf= 6ns
SWITCH INPUT
tPLH
SWITCH OUTPUT
tr= 6ns
90%
50%
10%
VCC
VEE
tPHL
50%
50% 10%
90%
GN
D
VCC (HC)
10%
90% 50%
50%
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH
ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
E
3V (HCT)
OUTPUTS
DISABLED
SWITCH OFF
OUTPUTS
ENABLED
SWITCH O
N
CD54HC4316, CD74HC4316, CD74HCT4316
10
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54HC4316F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC4316E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC4316EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC4316M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWT ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4316PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD74HCT4316EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT4316M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT4316MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC4316M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4316NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4316PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4316PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4316M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4316M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4316NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC4316PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4316PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HCT4316M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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