ISD15100 SERIES
Publication Release Date: May 6, 2011
- 1 - Revision 1.3
ISD15100 Series
Multi-Message Record/Playback Devices
with Digital Audio Interface
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 2 - Revision 1.3
TABLE OF CONTENTS
1 GENERAL DESCRIPTION .............................................................................................................. 3
2 FEATURES ...................................................................................................................................... 3
3 BLOCK DIAGRAM ........................................................................................................................... 5
4 PINOUT CONFIGURATION ............................................................................................................ 7
5 PIN DESCRIPTION .......................................................................................................................... 8
6 ELECTRICAL CHARACTERISTICS .............................................................................................. 11
6.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 11
6.2 OPERATING CONDITIONS ........................................................................................................................ 11
6.3 DC PARAMETERS ................................................................................................................................... 11
6.4 AC PARAMETERS ................................................................................................................................... 13
6.4.1 Internal Oscillator ......................................................................................................................... 13
6.4.2 Inputs ............................................................................................................................................. 13
6.4.3 Outputs ........................................................................................................................................... 14
6.4.4 SPI Timing ..................................................................................................................................... 15
6.4.5 I2S Timing ...................................................................................................................................... 17
7 APPLICATION DIAGRAM .............................................................................................................. 18
8 PACKAGE SPECIFICATION ......................................................................................................... 19
8.1 48 LEAD LQFP(7X7X1.4MM FOOTPRINT 2.0MM) .................................................................................... 19
9 ORDERING INFORMATION .......................................................................................................... 20
10 REVISION HISTORY.................................................................................................................. 21
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 3 - Revision 1.3
1 GENERAL DESCRIPTION
The ISD15100 series is a multi-message ChipCorder® featuring digital compression, comprehensive
memory management, flash storage, and integrated analog/digital audio signal paths. The message
management feature is designed to make message recording simple and address-free as well as
make code development easier for playback-only applications. This family utilizes flash memory to
provide non-volatile audio record/playback with durations up to 16 minutes for a single-chip solution.
Unlike other ChipCorder series, the ISD15100 series provides an I2S digital audio interface, faster
digital recording, higher sampling frequency, and a signal path with SNR equivalent to 12bit resolution.
The ISD15100 series can take digital audio data via I2S or SPI interface. When I2S input is selected, it
will replace the analog audio inputs and will support sample rates of 32, 44.1 or 48 kHz depending
upon clock configuration. When SPI interface is chosen, the sample rate of the audio data sent must
be one of the ISD15100 supported sample rates.
The ISD15100 series has built-in analog audio inputs, analog audio line driver, and speaker driver
output. The two analog audio inputs to the device are: (1) AUXIN has a fixed gain configured by SPI
command, and (2) ANAIN/ANAOUT has a fixed gain amplifier with the gain set by two external
resistors. ANAIN/ANAOUT can also be used as a microphone differential input (ANAIN/ANAOUT
becomes MIC+/MIC-) in conjunction with an automatic gain control (AGC) circuit configured by SPI
command. Analog outputs are available in three forms: (1) AUXOUT is a single-ended voltage output;
(2) AUDOUT can be configured as either a single-ended voltage output or a single-ended current
output; (3) BTL (bridge-tied-load) is a differential voltage output.
2 FEATURES
Fast Digital Programming
o Programming rate can go up to 1Mbits/second mainly limited by the flash memory write rate.
Duration
o 2 to 16 minutes based on 8kHz/4bit ADPCM
Message Management
o Perform address-free recording: The ISD15100 allocates memory for new recording requests
and upon completion, returns a start address to the host via SPI interface
o Store pre-recorded audio (Voice Prompts) using high quality digital compression
o Use a simple index based command for playback
o Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration
of the device and play back Voice Prompts sequences and message recordings.
Sample Rate
o Seven record and playback sampling frequencies are available for a given master sample
rate. For example, the record and playback sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16
and 32kHz* are available when the device is clocked at a 32kHz master sample rate.
o For I2S operation, 32, 44.1 and 48kHz master sample rates are available with record and
playback sampling frequencies scaling accordingly.
Compression Algorithms
o For recording
ADPCM: 2, 3, 4 or 5 bits per sample
µ-Law: 6, 7 or 8 bits per sample
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample. Each sampled value is stored as a code, offering no
compression but preserving maximum resolution
o For Pre-Recorded Voice Prompts
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 4 - Revision 1.3
µ-Law: 6, 7 or 8 bits per sample
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample
Enhanced ADPCM: 2, 3, 4 or 5 bits per sample
Variable-bit-rate optimized compression. This allows best possible compression given a
metric of SNR and background noise levels.
Oscillator
o Internal oscillator with internal reference: 2.048 MHz with ±10% deviation
o Internal oscillator with external resistor: 2.048 MHz with ±5% deviation when Rosc is 80k-ohm
o External crystal or clock input
o I2S bit clock input
o Crystals and resonators support standard audio sampling rates of 2.048, 4.096, 8.192, 12.288
and11.2896MHz
Inputs
o AUXIN: Analog input with 2-bit gain control configured by SPI command
o ANAIN/ANAOUT:
Analog input with the gain set by two external resistors from ANAOUT to ANAIN, or
Microphone differential input (ANAIN/ANAOUT becomes MIC+/MIC-)
o Digital AGC:
Automatic gain control of digitized data from the analog input
Outputs
o PWM: Class D speaker driver to direct drive an 8Ω speaker or buzzer
o AUDOUT: configurable as a current or voltage single-ended line driver
o AUXOUT: a single-ended voltage output
o BTL: a differential voltage output
I/Os
o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
o I2S interface: I2S_CLK, I2S_WS, I2S_SDI, I2S_SDO for digital audio data
o 8 GPIO pins (4 of the 8 GPIO pins share with I2S).
Three 8-bit Volume Control set by SPI command for flexible mixing
o VOLA: volume control for the digital audio data from I2S or analog inputs
o VOLB: volume control for the digital audio data from decompression block or SPI
o VOLC: master volume control for PWM, AUDOUT, AUXOUT and I2S outputs
Operating Voltage: 2.7-3.6V
Standby Current: 1uA typical
Package: Green 48L-LQFP
Temperature Options:
o Industrial: -40C to 85C
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 5 - Revision 1.3
3 BLOCK DIAGRAM
AUDOUT
AUXIN
ANAIN
+Digital Signal Path:
Digital Filters
Resampling
Digital Mixing
Volume Control
DAC
ADC +
AUXOUT
PWM
Control
Compression
De-Compression
Flash Memory
Controller Flash Memory
I2S
Interface
SPI
Interface
Memory Management
and Command
Interpreter
SCK
SDI
WS
SCLK
SSB
MISO
MOSI
INTB
RDY/BSYB
AUDOUT
AUXOUT
SPK+
SPK-
SUM1 SUM2
ADC_MUX
SDO
SUM2_MUX
AUD_MUX AUX_MUX
GPIO
Controller
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4/
GPIO5/
GPIO6/
GPIO7/
A
G
C
ANAIN
ANAOUT
Av = 0, 3, 6, 9dB
AUXIN
SPK+_MUX SPK-_MUX
Figure 3-1 ISD15100 Block Diagram, ANAIN Selected
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 6 - Revision 1.3
AUDOUT
AUXIN
MICIN
Digital Signal Path:
Digital Filters
Resampling
Digital Mixing
Volume Control
DAC
ADC +
AUXOUT
PWM
Control
Compression
De-Compression
Flash Memory
Controller Flash Memory
I2S
Interface
SPI
Interface
Memory Management
and Command
Interpreter
SCK
SDI
WS
SCLK
SSB
MISO
MOSI
INTB
RDY/BSYB
AUDOUT
AUXOUT
SPK+
SPK-
SUM2
SDO
SUM2_MUX
AUD_MUX AUX_MUX
GPIO
Controller
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4/
GPIO5/
GPIO6/
GPIO7/
A
G
C
MIC+
MIC-
Av = 0, 3, 6, 9dB
AUXIN
SPK+_MUX SPK-_MUX
Figure 3-2 ISD15100 Block Diagram, MICIN Selected
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 7 - Revision 1.3
4 PINOUT CONFIGURATION
VCCD
2
3
4
5
6
7
8
9
10
1
2
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
33
32
31
30
29
44 43 42 41 40 39 38 37
ISD15100
36
35
34
47 46 4548
VSSD
VSSD
VCCD
VREG
I2S_SDO/GPIO4
I2S_WS/GPIO5
I2S_SCK/GPIO6
I2S_SDI/GPIO7
NC
NC
NC
VCCD_PWM
NC
NC
SPK-
VSSD_PWM
SPK+
VCCD_PWM
MOSI
SSB
SCLK
MISO
NC
INTB
NC
NC
RDY/BSYB
RESET
XTALOUT
XTALIN
GPIO3
VCCD
GPIO2
GPIO1
VCCD
NC
NC
NC
AUDOUT
AUXOUT
VCCA
VSSA
ANAOUT/MIC-
ANAIN/MIC+
AUXIN
NC
GPIO0
Figure 4-1 ISD15100 48-Lead LQFP Pin Configuration.
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 8 - Revision 1.3
5 PIN DESCRIPTION
Pin
Number
Pin Name
I/O
Function
1
NC
This pin should be left unconnected.
2
NC
This pin should be left unconnected.
3
NC
This pin should be left unconnected.
4
I2S_SDI/
GPIO7
I
Serial Data Input of the I2S interface (If I2S is not used, this pin should
be grounded).
Or, can be configured as a GPIO pin.
5
I2S_SCK/
GPIO6
I/O
Clock input in slave mode or clock output in master mode. This pin can
be configured as an external clock buffer if I2S is not used (If I2S is not
used, this pin should be grounded).
Or, can be configured as a GPIO pin.
6
I2S_WS/
GPIO5
I/O
Word Select (WS) input in slave mode or WS output in master mode (If
I2S is not used, this pin should be grounded).
Or, can be configured as a GPIO pin.
7
I2S_SDO/
GPIO4
O
Serial Data Output of the I2S Interface (If I2S is not used, this pin
should be left unconnected).
Or, can be configured as a GPIO pin.
8
VCCD
I
Digital power supply.
9
VSSD
I
Digital Ground.
10
VSSD
I
Digital Ground.
11
VCCD
I
Digital power supply.
12
VREG
O
A 1.8V regulator to supply the internal logic. A 0.1uF capacitor should
be connected to this pin for supply decoupling and stability.
13
MISO
O
Master-In-Slave-Out. Serial output from the ISD15100 to the host. This
pin is in tri-state when SSB=1.
14
SCLK
I
Serial Clock input to the ISD15100 from the host.
15
SSB
I
Slave Select input to the ISD15100 from the host. When SSB is low
device is selected and responds to commands on the SPI interface.
16
MOSI
I
Master-Out-Slave-In. Serial input to the ISD15100 from the host.
17
VCCD_PWM
I
Digital Power for the PWM Driver.
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 9 - Revision 1.3
Pin
Number
Pin Name
I/O
Function
18
SPK+
O
PWM driver positive output. This SPK+ output, together with SPK- pin,
provide a differential output to drive 8Ω speaker or buzzer. During
power down this pin is in tri-state.
Or, can be configured as BTL which, together with SPK- pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
19
VSSD_PWM
I
Digital Ground for the PWM Driver.
20
SPK-
O
PWM driver negative output. This SPK- output, together with SPK+
pin, provides a differential output to drive 8Ω speaker or buzzer.
During power down this pin is tri-state.
Or, can be configured as BTL which, together with SPK+ pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
21
VCCD_PWM
I
Digital Power for the PWM Driver.
22
NC
This pin should be left unconnected.
23
NC
This pin should be left unconnected.
24
NC
This pin should be left unconnected.
25
INTB
O
Active low interrupt request pin. This pin is an open-drain output.
26
RDY/BSYB
O
An output pin to report the status of data transfer on the SPI interface.
“High” indicates that ISD15100 is ready to accept new SPI commands
or data.
27
RESET
I
Applying power to this pin will reset the chip. (A high pulse of 50ms or
more will reset the chip.)
28
NC
This pin should be left unconnected.
29
NC
This pin should be left unconnected.
30
GPIO3
I/O
GPIO
31
GPIO2
I/O
GPIO
32
GPIO1
I/O
GPIO
33
VCCD
I
Digital power supply pin.
34
VCCD
I
Digital power supply pin.
35
XTALOUT
O
Crystal interface output pin.
36
XTALIN
I
The CLK_CFG register determines one of the following three
configurations: (1) A crystal or resonator connected between the
XTALOUT and XTALIN pins. (2) A resistor connected to GND as a
reference current to the internal oscillator and left the XTALOUT
unconnected. (3) An external clock input to the device and left the
XTALOUT unconnected.
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 10 - Revision 1.3
Pin
Number
Pin Name
I/O
Function
37
NC
This pin should be left unconnected.
38
GPIO0
I/O
GPIO
39
NC
This pin should be left unconnected.
40
NC
This pin should be left unconnected.
41
AUDOUT
O
Audio Out. This pin can be either a voltage output or a current output
configured by the internal registers via SPI command.
If AUDOUT is not used, this pin should be left unconnected.
42
AUXOUT
O
Aux Out. This pin is an analog voltage output.
If AUXOUT is not used, this pin should be left unconnected.
43
VCCA
I
Analog power supply pin.
44
VSSA
I
Analog ground pin.
45
ANAOUT/
MIC-
O
Variable gain analog output with the gain set by feedback resistance to
ANAIN.
Or, can be configured as MIC- which, together with MIC+, provides a
microphone differential input.
If ANAIN/ANAOUT is not used, this pin should be left unconnected.
46
ANAIN/
MIC+
I
Variable gain analog input.
Or, can be configured as MIC+ which, together with MIC-, provides a
microphone differential input.
If ANAIN/ANAOUT is not used, this pin should be left unconnected.
47
AUXIN
I
Auxiliary input with the gain set by SPI command
If AUXIN is not used, this pin should be left unconnected.
48
NC
This pin should be left unconnected.
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 11 - Revision 1.3
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) [1]
CONDITIONS
VALUES
Junction temperature
1300C
Storage temperature range
-650C to +1500C
Voltage Applied to any pins
(VSS - 0.3V) to (VCC + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
Power supply voltage to ground potential
-0.3V to +5.0V
[1] Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
6.2 OPERATING CONDITIONS
OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS)
CONDITIONS
VALUES
Operating temperature range (Case temperature)
-40°C to +85°C
Supply voltage (VDD) [1]
+2.7V to +3.6V
Ground voltage (VSS) [2]
0V
Input voltage (VDD) [1]
0V to 3.6V
Voltage applied to any pins
(VSS –0.3V) to (VDD +0.3V)
NOTES: [1] VDD = VCCA = VCCD = VCCPWM
[2] VSS = VSSA = VSSD = VSSPWM
6.3 DC PARAMETERS
PARAMETER
SYMBOL
MIN
TYP [1]
MAX
UNITS
CONDITIONS
Supply Voltage
VDD
2.7
3.6
V
Input Low Voltage
VIL
VSS-0.3
0.3xVDD
V
Input High Voltage
VIH
0.7xVDD
VDD
V
Output Low Voltage
VOL
VSS-0.3
0.3xVDD
V
IOL = 1mA
Output High Voltage
VOH
0.7xVDD
VDD
V
IOH = -1mA
INTB Output Low Voltage
VOH1
0.4
V
Record Current
IDD_Record
40
mA
VDD= 3.6V, No load,
Sampling freq = 16 kHz
Playback Current
IDD_Playback
30
mA
Standby Current
ISB
1
10
µA
VDD= 3.6V
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 12 - Revision 1.3
Input Leakage Current
IIL
1
µA
Force VDD
Notes: [1] Conditions VDD=3V, TA=25°C unless otherwise stated
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 13 - Revision 1.3
6.4 AC PARAMETERS
6.4.1 Internal Oscillator
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Internal Oscillator with internal
reference
FINT
-10%
2.048
MHz
+10
%
MHz
Vdd = 3V.
At room temperature
Internal Oscillator with external
resistor [1]
FExt
-5%
2.048
MHz
+5%
MHz
With 1% precision
resistor, 80k-ohm.
Vdd = 3V.
At room temperature
Notes:
[1] Characterization data shows that frequency deviation is +/- 5% across temperature and voltage
ranges.
6.4.2 Inputs
ANAIN & MICIN
PARAMETER
SYMBOL
MIN
TYP [1]
MAX
UNITS
CONDITIONS
ANAIN Input Voltage
VANAIN
10-1000
mV
Peak-to-Peak[2]
ANAIN Feed Back Resistance
RANA(FB)
40
100
KΩ
MICIN Input Voltage
VMICIN
5-500
mV
Peak-to-Peak[2]
Notes: [1] Conditions VDD=3V, TAB=25°C unless otherwise stated
[2] Depends on Gain Setting
AUXIN
PARAMETER
SYMBOL
MIN
TYP[1]
MAX
UNITS
CONDITIONS
AUXIN Input Voltage
VAUXIN
1000
mV
Peak-to-Peak[2]
Gain from AUXIN to
AUXOUT/ANAOUT
AAUXIN GAIN
0 to 9
dB
4 Gain Steps of 3db
each
AUXIN Gain Accuracy
AAUXIN (GA)
-0.5
+0.5
dB
AUXIN Input Resistance
RAUXIN
20-40
KΩ
Depending on
AUXIN Gain Setting
Notes: [1] Conditions VDD=3V, TA=25°C unless otherwise stated.
[2] With 0db Gain setting.
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 14 - Revision 1.3
6.4.3 Outputs
AUXOUT
PARAMETER
SYMBOL
MIN
TYP[1]
MAX
UNITS
CONDITIONS
SINAD, AUXIN to AUXOUT
SINADAUXIN_AUXOUT
80
dB
Load 5K[2][3]
SINAD, ANAIN to AUXOUT
SINADANAIN_AUXOUT
80
dB
Load 5K[2][3]
PSRR
PSRRAUXOUT
-40
dB
[4]
DC Bias
VBIAS_AUXOUT
1.2
V
Minimum Load Impedance
RL(AUXOUT)
5
KΩ
Maximum Load Capacitance
CL(AUXOUT)
0.1
nF
Notes: [1] Conditions VDD=3V, TA=25°C unless otherwise stated.
[2] 1 Vpp 1KHz signal applied at AUXIN/ANAIN with 0db Gain setting.
[3] All measurements are C-message weighted.
[4] Measured with 1KHz, 100 mVpp sine wave applied to VCCA pins.
AUDOUT
PARAMETER
SYMBOL
MIN
TYP[1]
MAX
UNITS
CONDITIONS
SINAD, AUXIN to AUDOUT[5]
SINADAUXIN_AUDOUT
80
dB
Load 5K[2][3]
SINAD, ANAIN to AUDOUT[5]
SINADANAIN_AUDOUT
80
dB
Load 5K[2][3]
PSRR[5]
PSRRAUDOUT
-40
dB
[4]
DC Bias[5]
VBIAS_AUDOUT
1.2
V
Minimum Load Impedance[5]
RL(AUDOUT)
5
KΩ
Maximum Load Capacitance[5]
CL(AUDOUT)
0.1
nF
Output Current [6]
IAUDOUT
0
3
6
mA
[2][6]
Notes: [1] Conditions Vcc=3V, TA=25°C unless otherwise stated.
[2] 1 Vpp 1KHz signal applied at AUXIN/ANAIN with 0db Gain setting.
[3] All measurements are C-message weighted.
[4] Measured with 1Khz, 100 mVpp sine wave applied to VCCA pins.
[5] Configured as AUDOUT(Voltage Output).
[6] Configured as AUDOUT(Current Output).
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 15 - Revision 1.3
SPEAKER OUTPUTS
PARAMETER
SYMBOL
MIN
TYP[1]
MAX
UNITS
CONDITIONS
SNR, AUXIN to SPK+/SPK-
SNRAUXIN_SPK
60
dB
Load 150Ω [2][3]
SNR, ANAIN to SPK+/SPK-
SNRANAIN_SPK
60
dB
Load 150Ω [2][3]
Output Power
POUT_SPK VCC=3.0
360
mW
Load 8Ω [2]
THD, AUXIN to SPK+/SPK-
THD %
<1%
Load 8Ω [2]
Minimum Load Impedance
RL(SPK)
4
8
Ω
Notes: [1] Conditions Vcc=3V, TA=25°C unless otherwise stated.
[2] 1 Vpp 1KHz signal applied at AUXIN/ANAIN with 0db Gain setting.
[3] All measurements are C-message weighted.
6.4.4 SPI Timing
TRISE
TFALL
SSB
SCLK
MOSI
MISO
TSCK
TSCKH TSCKL
TSSBS TSSBH
TMOS TMOH
TMID
TSSBHI
TZMID
RDY/BSYB TCRBD TRBCD
TMIZD
Figure 0-1 SPI Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
TSCK
SCLK Cycle Time
60
---
---
ns
TSCKH
SCLK High Pulse Width
25
---
---
ns
TSCKL
SCLK Low Pulse Width
25
---
---
ns
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 16 - Revision 1.3
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
TRISE
Rise Time for All Digital Signals
---
---
10
ns
TFALL
Fall Time for All Digital Signals
---
---
10
ns
TSSBS
SSB Falling Edge to 1st SCLK Falling Edge Setup
Time
30
---
---
ns
TSSBH
Last SCLK Rising Edge to SSB Rising Edge Hold
Time
30 ns
---
50us
---
TSSBHI
SSB High Time between SSB Lows
20
---
---
ns
TMOS
MOSI to SCLK Rising Edge Setup Time
15
---
---
ns
TMOH
SCLK Rising Edge to MOSI Hold Time
15
---
---
ns
TZMID
Delay Time from SSB Falling Edge to MISO Active
--
--
12
ns
TMIZD
Delay Time from SSB Rising Edge to MISO Tri-state
--
--
12
ns
TMID
Delay Time from SCLK Falling Edge to MISO
---
---
12
ns
TCRBD
Delay Time from SCLK Rising Edge to RDY/BSYB
Falling Edge
--
--
12
ns
TRBCD
Delay Time from RDY/BSYB Rising Edge to SCLK
Falling Edge
0
--
--
ns
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 17 - Revision 1.3
6.4.5 I2S Timing
TWSH TWSS
MSB
TSDIS
TSDOD
TSCKH TSCKL
TWSH TWSS
MSB
MSB
MSB
LSB
LSB
TSDIH
TSCK TRISE
TFALL
IS_SCK
IS_WS
IS_SDI
IS_SDO
Figure 0-2 I2S Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
TSCK
IS_SCK Cycle Time
60
---
---
ns
TSCKH
IS_SCK High Pulse Width
25
---
---
ns
TSCKL
IS_SCK Low Pulse Width
25
---
---
ns
TRISE
Rise Time for All Digital Signals
---
---
10
ns
TFALL
Fall Time for All Digital Signals
---
---
10
ns
TWSS
WS to IS_SCK Rising Edge Setup Time
20
---
---
ns
TWSH
IS_SCK Rising Edge to IS_WS Hold Time
20
---
---
ns
TSDIS
IS_SDI to IS_SCK Rising Edge Setup Time
15
---
---
ns
TSDIH
IS_SCK Rising Edge to IS_SDI Hold Time
15
---
---
ns
TSDOD
Delay Time from IS_SCLK Falling Edge to IS_SDO
---
---
12
ns
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 18 - Revision 1.3
7 APPLICATION DIAGRAM
The following applications example is for references only. It makes no representation or warranty that such applications shall be suitable for the use
specified. Each design has to be optimized in its own system for the best performance on voice quality, current consumption, functionalities and etc.
I2S_SDI/GPIO7
I2S_SCK/GPIO6
I2S_WS/GPIO5
I2S_SDO/GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
4
5
6
7
30
31
32
38
MISO
SCLK
SSB
MOSI
INTB
RDY/BSYB
RESET
13
14
15
16
25
26
27
MIC+
MIC-
AUXIN
8
11
9
10
VSSD
VSSD
VCCD
VCCD
VCCD
0.1
uF
47
uF
VCCD
17
21
19
VSSD_PWM
VCCD_PWM
VCCD_PWM
VCCD
VCCD 34
33
high pulse of 50ms
VREG
12
46
45
: Digital ground; : Analog ground;
0.1
uF
47
VCCD
10K
VCCA
220uF
1.5 K
0.1uF
1.5 K
0.1uF
1.5 K
0.01
uF 0.001
uF
47
uF
MIC
ISD15100
data flow control
SPI Type-III
SPK+
SPK-
18
20
100
4.7K
0.1uF
200
pF
AUXOUT 42
AUDOUT 41
4300.1uF
VCCA
8050C
43
VSSA
VCCA 0.1
uF
47
uF
VCCA
44
5.6 K
5.6 K220pF
0.1uF
XTALOUT
XTALIN 36
35
27pF 27pF
270
1M
Figure 7-1 ISD15100 Application Diagram
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 19 - Revision 1.3
8 PACKAGE SPECIFICATION
8.1 48 LEAD LQFP(7X7X1.4MM FOOTPRINT 2.0MM)
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 20 - Revision 1.3
9 ORDERING INFORMATION
I151xx FYI
Lead-Free Package Type
F: 48L-LQFP
Y: Green (RoHS Compliant)
I: Industrial -40 C to 85C
Duration
02: 2 minute*
04: 4 minute*
08: 8 minute*
16: 16 minute*
* Based on 8kHz/4bit ADPCM
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 21 - Revision 1.3
10 REVISION HISTORY
Version
Date
Description
0.71
May 28, 2008
Initial release.
Reset pulse: 50ms.
Add a 270-ohm resistor between XTALOUT and
crystal.
Update spec of internal oscillator.
Industrial temp.
0.75
Sep 10, 2008
Update:
SPI timing: TSSBH maximum 50us.
MICIN input signal: 500mV
Revise Block Diagram; add BTL block.
Revise Application Diagram.
0.80
Feb 10, 2009
Update:
Remove the Preliminary watermark.
Output low/high voltage.
0.82
Nov 20, 2009
Update Block Diagram.
1.0
July 1, 2010
Update crystal configuration.
1.3
May 6, 2011
Add Absolute Maximum Ratings.
ISD15100 SERIES
Publication Release Date: May 6, 2011
- 22 - Revision 1.3
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