19-3931; Rev 4; 2/11 KIT ATION EVALU E L B A AVAIL 25V Span, 800mA Device Power Supply (DPS) Features The MAX9959 provides all the key features of a device power supply (DPS) common to automatic test equipment (ATE) and other instrumentation. Its small size, high level of integration, and superb flexibility make the MAX9959 ideal and economical for multisite systems requiring many device power supplies. The MAX9959 has multiple input control voltages that allow independent setting of both the output voltage, and the maximum and minimum (smallest positive or most negative) voltage or current. The MAX9959 is a voltage source when the load current is between the two programmed limits, and transitions gracefully into a precision current source/sink if a programmed current limit is reached. The output features two independently adjustable voltage clamps that limit both the negative and positive output voltage values between levels externally provided. The MAX9959 can source voltages spanning 25V and can source currents as high as 800mA. The DPS can support an external buffer for sourcing and sinking higher currents. Multiple MAX9959s can be configured in parallel to load-share, allowing higher output currents with greater flexibility. o 25V Span Output Voltage The MAX9959 features operation over a wide range of loading conditions. Programmability allows optimizing of settling time, over-/undershoot, and stability. Built-in, configurable, range-change glitch-control circuits minimize output glitches during range transitions. o Compact (14mm x 14mm) Package o Programmable Current and Voltage Compliance o Programmable Current Ranges 200A 2mA 20mA 800mA o Load Regulation of 1mV at 800mA o External Buffer Support for Higher Currents o Parallel Multiple Devices for Higher Currents o Programmable Gain Allows a Wide Range of DACs o Device-Under-Test (DUT) Ground Sense o Programmable Compensation for Wide Range of Loads o Integrated Go/No-Go Comparators o IDDQ Test Mode o Range-Change Glitch Control o 3-Wire Compatible Serial Interface o Thermal Warning Flag and Thermal Shutdown The MAX9959 offers load regulation of 1mV at 800mA load. The MAX9959D features an internal 300k sense resistor (R FS ), between RCOMF and SENSE. The MAX9959F does not include this sense resistor. Both devices are available in the 100-pin TQFP package with an exposed pad on the top for heat removal. Applications Memory Testers VLSI Testers Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9959DCCQ 0C to +70C 100 TQFP-EPR-IDP* MAX9959DCCQ+ 0C to +70C 100 TQFP-EPR-IDP* MAX9959FCCQ+ 0C to +70C 100 TQFP-EPR-IDP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EPR = Exposed pad. Inverted die pad. System-On-a-Chip Testers Industrial Systems Structural Testers Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9959 General Description MAX9959 25V Span, 800mA Device Power Supply (DPS) ABSOLUTE MAXIMUM RATINGS VCC to VEE ......................................................................... +31V VCC to AGND ...................................................................... +20V VEE to AGND....................... .................................................-15V VL to DGND .......................................................................... +6V AGND to DGND.....................................................-0.5V to +0.5V Digital Inputs ................................................-0.3V to (VL + 0.3V) All Other Pins ...................................(VEE - 0.3V) to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 100-Pin TQFP-EPR-IDP (derated at 166.7mW/C above +70C)........................................................13.33W Junction Temperature ..................................................... +150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................ +300C Soldering Temperature (reflow) Lead(Pb)-Free Packages.............................................+260C Packages Containing Lead(Pb)...................................+240C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +12V, VEE = -12V, VL = +3.3V, TJ = +30C to +100C. Typical values are at TJ = +30C, unless otherwise specified.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VOLTAGE OUTPUT Output Voltage Range Output Offset Output-Voltage Temperature Coefficient Voltage Gain Error Voltage-Gain Temperature Coefficient Linearity Error Off-State Leakage Current Force-to-Sense Resistor VDUT VOS DUT current below 10% of FSR current VEE + 2.5 VCC - 2.5 DUT current = +800mA, range A (Note 2) 0 +7 DUT current = -800mA, range A (Note 2) -7 0 DUT current at full scale (IDUT = 200A, 2mA, 20mA, or 200mA) VEE + 5 VCC - 5 VIN = 0V, IOUT = 0A (no load), gain = +1 25 50 VOSTC VGE VLER 1.25 Gain = +2 1.25 Gain = +6 1.25 Gain = -1 1.25 Gain = -2 1.25 Gain = -6 1.25 HIZFLK RFS 5 Gain and offset errors calibrated out; IOUT = 0 for ranges A, C, and D; 20mA for range B; gain = +1 (Notes 3, 4, 5) RCOMF = (VCC - 2.5V) to (VEE + 2.5V) -10 "D" option only mV V/C Gain = +1 VGETC V % ppm/C 0.02 %FSR +10 nA 300 k 700 mV DUT GROUND SENSE Voltage Range VDUTGND VDUTGSNS - VAGND 500 LOAD REGULATION (Note 6) Voltage 2 VDUT Range A, gain = +1, VIN = (VCC - 5V) to (VEE + 5V), 800mA current load step (Note 5) 1 _______________________________________________________________________________________ 7 mV 25V Span, 800mA Device Power Supply (DPS) (VCC = +12V, VEE = -12V, VL = +3.3V, TJ = +30C to +100C. Typical values are at TJ = +30C, unless otherwise specified.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 200 A CURRENT OUTPUT Range D, RD = 5000 Output Current Range Input Voltage Range Corresponding to the Full-Scale Force Current Current-Sense-Amp Offset Voltage Input Output Current Offset Force-Current Offset Temperature Coefficient Gain Error IDUT Output Over Current-Limit Range (Note 4) Linearity Error VIOSI IOS 20 Range A, RA = 1.25 800 -4 +4 VIOSI = VAGND + 4V 0 +8 -0.2 +4.4 V 0.5 %FSR V Relative to AGND VRCOMF = 0V (Note 4) 0.1 20 VRCOMF = 0V, IOUT = FSR CMROER ppm/C 1.0 IGETC IOCL mA IOSI = AGND IOSTC ILER Rejection of Output Error Due to Common-Mode Load Voltage 2 Range B, RB = 50 VINI IGE Forced-Current Gain Temperature Coefficient Range C, RC = 500 20 ppm/C Range D, IOUT = 200A 135 147 158 Range C, IOUT = 2mA 135 147 158 Range B, IOUT = 20mA 135 147 158 Range A, IOUT = 800mA 125 138 150 Gain, offset, and CMR errors calibrated out; VIOSI = -0.2V and +4.4V; ranges B, C, and D (Notes 4, 5, 7) Range D, IOUT = 0, VRCOMF = (VEE + 2.5V) and (VCC - 2.5V), measured across RD 0.001 Range D 200 Range C 2 Range B 20 % %FSR 0.02 %FSR 0.005 %FSR/V CURRENT MONITOR Measured Current Range IDUTM Range A Current-Sense-Amp Voltage Range VISENSE +4 VIOSI = VAGND + 4V 0 +8 -0.2 +4.4 V 0.5 %FSR Relative to AGND Current-Sense-Amp Offset IMOS VRCOMF = 0V (Note 4) IMOSTC IMGE 800 -4 VIOSI Gain Error mA IOSI = AGND Current-Sense-Amp Offset Voltage Input Measured-Current Offset Temperature Coefficient A 0.1 20 VRCOMF = 0V, IOUT = FSR V ppm/C 1 % _______________________________________________________________________________________ 3 MAX9959 DC ELECTRICAL CHARACTERISTICS (continued) MAX9959 25V Span, 800mA Device Power Supply (DPS) DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +12V, VEE = -12V, VL = +3.3V, TJ = +30C to +100C. Typical values are at TJ = +30C, unless otherwise specified.) (Notes 1, 2) PARAMETER Measured-Current Gain Temperature Coefficient Linearity Error Rejection of Output Error Due to Common-Mode Load Voltage SYMBOL CONDITIONS MIN IMGETC IMLER CMRMOER TYP MAX 20 Gain, offset, and CMR errors calibrated out; VIOSI = -0.2V and +4.4V, range B (Notes 4, 5) UNITS ppm/C 0.02 %FSR 0.005 %FSR/ V VEE + 2.5 VCC - 2.5 V -0.2 +4.4 V 25 mV Range D, IOUT = 0A, VRCOMF = (VEE + 2.5V) and (VCC - 2.5V) 0.001 VOLTAGE MONITOR Measured Output Voltage Range VDUTM Gain = +1, IOSV = AGND Voltage-Sense-Amp Offset Voltage Input VIOSV Relative to AGND Voltage-Sense-Amp Offset VDUTMOS Measured Voltage Offset Temperature Coefficient VDUTMOSTC Voltage-Sense-Amp Gain Error Measured-Voltage Gain Temperature Coefficient Linearity Error VDUTGE Gain = +1 10 Gain = +1 1 Gain = +1/2 1 Gain = +1/6 1 VDUTGETC VDUTLER V/C 10 Gain and offset errors calibrated out, VIOSV = -0.2V and +4.4V, IOUT = 0A, gain = +1, range B (Note 4) % ppm/C 0.02 %FSR VEE + 2.3 VCC - 2.3 V VEE + 2.5 VCC - 2.5 VEE + 5 VCC - 5 VOLTAGE/CURRENT CLAMPS (Note 8) Input Control Voltage VCLLO, VCLHI Voltage Clamp Range (Note 9) VCRNG Voltage Clamp Gain VCGAIN Voltage Clamp Accuracy (Notes 2, 9) VCERR Current Clamp Range ICRNG Current Clamp Gain ICGAIN Current Clamp Accuracy ICERR DPS output current 10% of FSR DPS output current at FSR +1 V/V Range A to D, IOUT 10% of FSR 200 Range A to D, IOUT = FSR 200 (Note 10) V mV VIOSI 1.5 x FSR V 4 V/FSR Range A, VOUT = FSR, IOUT = FSR (Notes 2, 10) 0.15 Range B to D, VOUT = FSR, gain and offset errors calibrated out (Note 10) 0.05 %FSR COMPARATOR INPUTS Input Voltage Range CMPIRG Input Offset Voltage CMPIOS 4 VEE + 3.5 VITHHI = VITHLO = 0V _______________________________________________________________________________________ VCC - 3.5 V 30 mV 25V Span, 800mA Device Power Supply (DPS) (VCC = +12V, VEE = -12V, VL = +3.3V, TJ = +30C to +100C. Typical values are at TJ = +30C, unless otherwise specified.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS COMPARATOR OUTPUTS Output High Voltage CMPOH VL = 2.375V to 3.3V, RPULLUP = 1k Output Low Voltage CMPOL VL = 2.375V to 3.3V, RPULLUP = 1k High-Impedance State Leakage Current High-Impedance Output Capacitance ANALOG INPUTS Input Current Input Capacitance DIGITAL INPUTS VL - 0.2 V 0.4 V CMPOLK 5 nA CMPOC 1 pF IIN CIN 5 4 nA pF Input High Voltage VIH Input Low Voltage VIL VTHR Input Range VTHR VTHR + 0.15 V 0.5 VTHR 0.15 V VL - 0.5 V Input Current IIN 25 A Input Capacitance CIN 4 pF DIGITAL OUTPUTS Output High Voltage VOH VL = 2.375V to 3.3V, relative to DGND, IOUT = +1.0mA Output Low Voltage VOL VL = 2.375V to 3.3V, relative to DGND, IOUT = -1.0mA VL - 0.25 V 0.2 V TEMPERATURE SENSOR Analog Output Offset VTSNSO Analog Output Gain VTSNSG Digital Output Temperature Threshold TTSNSR Thermal-Shutdown Temperature TJ = +28C (Note 11) TSDN 3.01 V 10 mV/C +130 C +140 C POWER SUPPLY Positive Supply VCC (Note 12) 12 18 V Negative Supply VEE (Note 12) -15 -12 V +30 V +2.375 +3.300 V mA Total Supply Voltage VCC - VEE Logic Supply VL Positive Supply Current ICC No load 20 22 Negative Supply Current IEE No load 19 21 mA Analog Ground Current IAGND No load 0.8 1.0 mA Logic Supply Current IL No load, all digital inputs at DGND 7.0 9.0 mA Digital Ground Current IDGND No load, all digital inputs at DGND 7.0 9.0 mA Power-Supply Rejection Ratio PSRR Each supply varied individually from min to max, VDUT = 5.0V 80 dB _______________________________________________________________________________________ 5 MAX9959 DC ELECTRICAL CHARACTERISTICS (continued) MAX9959 25V Span, 800mA Device Power Supply (DPS) AC ELECTRICAL CHARACTERISTICS (VCC = +12V, VEE = -12V, VL = +3.3V, CC1 = 350pF, CL = 100pF, CMEAS = 100pF, CIMEAS = 100pF, TJ = +30C to +100C. Typical values are at TJ = +35C, unless otherwise specified.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FORCE VOLTAGE (Notes 13, 14) Settling Time FVST Range D = 200A, RL = 35k to AGND 30 Range C = 2mA, RL = 3.5k to AGND 20 Range B = 20mA, RL = 350 to AGND 30 Range A = 800mA, RL = 8.75 to AGND 25 50 s LOAD REGULATION SETTLING TIME (Note 14) Settling Time LRST Range A, VIN = 7V, RL = 8.75 switched between open circuit to AGND, CL = 10F 100 s FORCE VOLTAGE/MEASURE CURRENT (Notes 13, 14, 15) Settling Time FVMIST Range D = 200A, RL = 35k to AGND 50 Range C = 2mA, RL = 3.5k to AGND 20 Range B = 20mA, RL = 350 to AGND 25 Range A = 800mA, RL = 8.75 to AGND 35 Range D = 200A, RL = 35k to AGND 100 Range C = 2mA, RL = 3.5k to AGND 35 Range B = 20mA, RL = 350 to AGND 25 Range A = 800mA, RL = 8.75 to AGND 20 50 s FORCE CURRENT (Notes 13, 14) Settling Time FIST 50 s FORCE CURRENT/MEASURE VOLTAGE (Notes 13, 14, 15) Settling Time FIMVST Range D = 200A, RL = 35k to AGND 100 Range C = 2mA, RL = 3.5k to AGND 35 Range B = 20mA, RL = 350 to AGND 25 Range A = 800mA, RL = 8.75 to AGND 40 50 s FORCE OUTPUT Output Slew Rate Stable Load Capacitance Range Output Overshoot FOSLEW FOSLC CL = 0F (Note 16) 0.7 (Notes 17, 18) FOOSHT CL < 20F, CB1 = 3nF MOSLC (Note 17) 2.1 V/s 1000 F 0 % MEASURE OUTPUT Stable Load Capacitance Range 1000 pF COMPARATORS (CILIMHI/ILIMLO = 20pF, RPULLUP = 1k) (Note 19) Propagation Delay CMPPD 100mV overdrive, 1VP-P, measured from input threshold zero crossing to 50% of output voltage 100 ns Rise Time CMPTR 20% to 80% 80 ns Fall Time CMPTF 20% to 80% Disable True to High Impedance Disable False to Active 6 5 ns CMPHIZT Measured from 50% of digital input voltage to 10% of output voltage 100 ns CMPHIZF Measured from 50% of digital input voltage to 90% of output voltage 100 ns _______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) (VCC = +12V, VEE = -12V, VL = +3.3V, CC1 = 350pF, CL = 100pF, CMEAS = 100pF, CIMEAS = 100pF, TJ = +30C to +100C. Typical values are at TJ = +35C, unless otherwise specified.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS SERIAL PORT TIMING CHARACTERISTICS (VL = 3.0V, CDOUT = 10pF) (Figure 4) MIN Serial Clock Frequency fSCLK SCLK Pulse-Width High tCH 12 SCLK Pulse-Width Low tCL 12 SCLK Fall to DOUT Valid tDO TYP MAX UNITS 20 MHz ns ns 25 ns CS Low to SCLK High Setup tCSS0 10 SCLK High to CS High Hold tCSH1 22 ns SCLK High to CS Low Hold tCSH0 0 ns CS High to SCLK High Setup tCSS1 5 ns tDS 10 ns DIN to SCLK High Setup DIN to SCLK High Hold (Note 17) ns tDH 0 ns CS Pulse-Width High tCSWH 10 ns CS Pulse-Width Low tCSWL 10 ns LOAD Pulse-Width Low tCLL 20 Power-On Reset POR Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: Note 19: ns 50 s All minimum and maximum test limits are 100% production tested at TJ = +35C 15C at nominal supplies. Specifications over the full operating temperature range are guaranteed by design and characterization. Exercise care not to exceed the maximum power dissipation specifications listed in the Absolute Maximum Ratings section. With drive current of 800mA limit DPS operation to two quadrants (i.e., when sourcing current limit VDUT to below +7V, when sinking current limit VDUT to above -7V). With drive current below 800mA and four-quadrant operation, limit DPS power dissipation to below the allowed maximum. VIN swept to achieve an output voltage of (VEE + 2.5V) to (VCC - 2.5V), with IOUT = 0. Parameters expressed in terms of %FSR (percent of full-scale range) are as a percent of the end-point-to-end-point range. Case must be maintained to within 5C for linearity specifications to apply. Load regulation is defined at a single programmed output voltage (force voltage mode), independent of linearity specification, with a 0 to 100% current step. To maintain linearity, keep the clamps at least 700mV away from VRCOMF. In the force-current and force-voltage modes, the reference-clamping voltage CLH must be greater than 0V, and CLL must be less than 0V. For high clamping accuracy, CLH-CLL is > 1V. To maintain 0.02% force-voltage linearity when the programmable current clamps are enabled, two conditions must be met: 1) CLH and CLL must be set 12.5% FSR higher than the forced current and 2) CLH and CLL must be set such that CLH is 1.6V + IOSI and CLL is -1.6V + IOSI (e.g., if driving 1mA in the 2mA range, the current clamps must be set to a minimum of 1.5mA, or CLH = 3V, CLL = -3V, and IOSI = 0V). DPS in force current mode. DPS in force voltage mode. The temperature threshold may vary up to 10C from the specified threshold. The device operates properly within absolute specifications, for varying supply voltages with equally varying output voltage settings. Settling times are for a full-scale voltage or current step. FVST measured from VIN to VDUT, FVMIST from VIN to IMEAS, FIST from VIN to VDUT, and FIMVST from VIN to VMEAS. Settling times are to 0.1% of FSR. The actual settling time of the measure path (sense input to measure output) is less than 1s. However, the RC time constant of the sense resistor and the load capacitance causes a longer overall settling time of VDUT. This settling time is a function of the current range resistor. Slew rate is measured from the 20% to 80% points. Guaranteed by design and characterization. Range A. The propagation delay time is measured by holding the current constant, and transitioning ITHHI or ITHLO. _______________________________________________________________________________________ 7 MAX9959 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (TA = +25C, unless otherwise noted.) 0 VIMEAS VIMEAS VDUT t = 10s/div t = 10s/div TRANSIENT RESPONSE FVMI MODE, RANGE D TRANSIENT RESPONSE FVMV MODE, RANGE C TRANSIENT RESPONSE FIMV MODE, RANGE A MAX9959 toc05 MAX9959 toc06 t = 10s/div MAX9959 toc04 VIMEAS 2V/div VIN 2V/div 0 VDUT 0 VIN VVMEAS VVMEAS VDUT VDUT TRANSIENT RESPONSE FIMV MODE, RANGE B TRANSIENT RESPONSE FIMV MODE, RANGE C TRANSIENT RESPONSE FIMV MODE, RANGE D 2V/div VIN 0 VIN VVMEAS VVMEAS VDUT VDUT MAX9959 toc09 t = 10s/div MAX9959 toc08 t = 5s/div MAX9959 toc07 t = 15s/div 2V/div 2V/div 0 VDUT VIN 0 2V/div VIMEAS VDUT 0 MAX9959 toc03 MAX9959 toc02 VIN VIN 2V/div 2V/div VIN 0 TRANSIENT RESPONSE FVMI MODE, RANGE C TRANSIENT RESPONSE FVMI MODE, RANGE B MAX9959 toc01 TRANSIENT RESPONSE FVMI MODE, RANGE A 2V/div MAX9959 25V Span, 800mA Device Power Supply (DPS) 0 VIN VVMEAS VDUT t = 10s/div 8 t = 10s/div t = 25s/div _______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) MAX9959 toc12 MAX9959 toc11 VDUT = 300mV/div 7V VIMEAS 7V VDUT = 7V LOAD = 0 TO 800mA TO 0 CLOAD = 10F VDUT = 7V LOAD = 0 TO 800mA TO 0 CLOAD = 47F t = 10s/div t = 50s/div RESPONSE TO CAPACITIVE LOAD FALLING EDGE RESPONSE TO CAPACITIVE LOAD POSITIVE SIGNAL MAX9959 toc13 RESPONSE TO CAPACITIVE LOAD RISING EDGE t = 100s/div CLOAD = 1000F VIN NO COMPENSATION 0 1V/div 0 2V/div 2V/div VIN NO COMPENSATION 100pF LEAD 100pF LEAD CB1 = 3000pF CB1 = 3000pF CB3 = 0.025F 0 CLOAD = 0.47F t = 1ms/div RESPONSE TO CAPACITIVE LOAD NEGATIVE SIGNAL RANGE-CHANGE GLITCH RANGE-CHANGE GLITCH 0 VIN IDDQSEL = LOW TO HIGH FV RANGE A TO D MAX9959 toc17 t = 10s/div MAX9959 toc16 t = 10s/div IDDQSEL = HIGH TO LOW FV RANGE D TO A MAX9959 toc18 VIN CLOAD = 0.47F MAX9959 toc14 VDUT MAX9959 toc15 VDUT = 50mV/div MAX9959 toc10 2V/div VIN 0 LOAD REGULATION TRANSIENT RECOVERY LOAD REGULATION TRANSIENT RECOVERY TRANSIENT RESPONSE FIMI MODE, RANGE C CT = 250pF 50mV/div 1V/div 25mV/div CB3 = 0.025F 0 0 CT = 0 CT = 0 CT = 250pF CLOAD = 1000F t = 1ms/div t = 10s/div t = 5s/div _______________________________________________________________________________________ 9 MAX9959 Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) 25V Span, 800mA Device Power Supply (DPS) MAX9959 Pin Description PIN NAME 1-8 RA 9 BIFRCA 10 RB 11 BIFRCB 12 RC Range C Output. Connect to a range-setting resistor. 13 RD Range D Output. Connect to a range-setting resistor. 14 RCOMF Sense Resistors Kelvin Connection. The Kelvin connection for the sense resistors that connect to the DUT. RCOMF provides a feedback point for current sensing. 15 SENSE Sense Input. Kelvin connection to the DUT. Provides the feedback signal for FVMI and the measured signal for FIMV. 16 FUNCTION Range A Outputs. Connect together and to a range-setting resistor. Positive Current-Sense-Amplifier Input. Used in range A to provide a Kelvin connection to rangesetting resistor. Range B Output. Connect to a range-setting resistor. Positive Current-Sense-Amplifier Input. Used in range B to provide a Kelvin connection to rangesetting resistor. DUT Ground Sense. In force voltage mode, senses the error between AGND and DUTGND and DUTGSNS adjusts the output voltage to achieve the desired voltage drop across the DUT with respect to DUTGND. 17, 18, 25, 49, 77-84, 93, 99 VCC Positive Analog Supply 19, 20, 26, 50, 76, 85-92, 95, 100 VEE Negative Analog Supply 21 VRXP Positive Current-Sense-Amplifier Input. Used in the external range to provide a Kelvin connection to the range-setting resistor. 22 VRXM Negative Current-Sense-Amplifier Input. Used in the external range to provide a Kelvin connection to the range-setting resistor. 23 CT1 Range-Change Glitch-Control Capacitor Connection. Connect optional capacitor from CT1 to DGND. 24 CT2 Range-Change Glitch-Control Capacitor Connection. Connect optional capacitor from CT2 to DGND. 27, 28, 45-48, 96, 97, 98 N.C. No Connection. Make no connection to these pins. 29, 38, 44 DGND Digital Ground 30 HIZMP High-Impedance Control Input. Places current and voltage measure outputs into a highimpedance state. 31 IDDQSEL 32 DIN 33 LOAD Load Data Input. A falling edge at LOAD transfers data from the input registers to the DPS registers. 34 SCLK Serial Clock Input. Serial interface clock. 35 CS 36 VTHR 37 VL 10 IDDQ Test Select. In FV mode, switches between the programmed current range and range D, the lowest current range. Data Input. Serial interface data input. Chip-Select Input Threshold Voltage Input. Sets the input logic threshold level of all digital inputs. Defaults to 1/2 VL if unconnected. Logic Power Supply ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) Pin Description (continued) MAX9959 PIN NAME 39 DOUT 40 EXTSEL External Select Output. Selects the external range. 41 HITEMP High Temperature Indicator Output. Open-collector output goes low when the temperature of the die is above the specified safe operating temperature. 42 ILIMLO Low Current-Limit Output. A sensed current below the ITHLO level forces the ILIMLO output low. ILIMLO is an open-drain output. 43 ILIMHI High Current-Limit Output. A sensed current above the ITHHI level forces the ILIMHI output low. ILIMHI is an open-drain output. 51 ITHLO Low Current-Limit Input. Voltage input that sets the lower threshold for the sense current comparator. 52 ITHHI High Current-Limit Input. Voltage input that sets the upper threshold for the sense current comparator. 53 IOSI Current-Sense Offset Voltage Input. Voltage input that sets an offset voltage for the current-sense amplifier in either FI or MI mode. 54 IOSV Measure Offset Voltage Input. Voltage input that sets an offset voltage for the measure voltage amplifier. 55 VINS 56 VIN 57 AGND FUNCTION Data Output. Serial interface data output. Forced-Current Input. Voltage input that sets the forced current in FI slave mode. Forced-Current/Voltage Input. Voltage input that sets the forced current in FI mode or forced voltage in FV mode. Analog Ground 58 CLL Compliance Low Input. Voltage input that sets the low-side voltage/current compliance. 59 CLH Compliance High Input. Voltage input that sets the high-side voltage/current compliance. 60 IPAR Current-Controlled Proportional Voltage Output. IPAR outputs a voltage that is proportional to the DUT current. Used to slave additional parallel DPSs to provide increased output current. 61 IMEAS Current-Controlled Proportional Voltage Output. IMEAS outputs a voltage that is proportional to the DUT current. High impedance when HIZMP is forced low. 62 VMEAS Voltage-Controlled Proportional Voltage Output. VMEAS outputs a voltage equal to 1x, 1/2x, or 1/6x the voltage present at SENSE. High impedance when HIZMP is forced low. 63 TEMP Temperature Monitor Output. TEMP outputs a voltage proportional to die temperature of 10mV/K. 64 CBC CB Common. Common point for bypass capacitor connections CB1, CB2, and CB3. 65 CB1 Bypass Capacitor 1. Compensation capacitor 1 connection. 66 CB2 Bypass Capacitor 2. Compensation capacitor 2 connection. 67 CB3 Bypass Capacitor 3. Compensation capacitor 3 connection. 68 CC1 Main Compensation Capacitor. Compensation capacitor connection 1. 69 CC2 Main Compensation Capacitor. Compensation capacitor connection 2. 70 CCHL 71 CCH High Clamp Compensation Capacitor. High-side voltage clamp compensation capacitor connection. 72 CCL Low Clamp Compensation Capacitor. Low-side voltage clamp compensation capacitor connection. SAMPO Lead Compensation Capacitor Common. Common connection for CCOMP1 and CCOMP2. 73 Clamp Compensation Capacitor Common. Common connection for CCL and CCH. 74 CCOMP1 Compensation Capacitor 1. Lead compensation capacitor 1 connection. 75 CCOMP2 Compensation Capacitor 2. Lead compensation capacitor 2 connection. 94 AMPOUT Main Amplifier Output. Drives the external buffer when in external range mode. -- EP Exposed pad. Internally connected to VEE. Connect to a large VEE power plane or heatsink to maximize thermal performance. Not intended as an electrical connection point. ______________________________________________________________________________________ 11 MAX9959 25V Span, 800mA Device Power Supply (DPS) CCOMP2 HIZM LEAD COMPENSATION SELECT MAX9959 VMEAS CCOMP1 SAMPO IOSV SENSE GAIN SELECT HIZF CLH RFS ("D" VERSION ONLY) CLL VIN VCLMP GAIN SELECT 1k A1 AMPOUT RA (8x) RB VINS CC CC1 CC2 DUT DUTGSNS FVMODE FISLAVE MODE ICLMP AGND DUT NODE RC HIZF RD CLEN CB1 CB2 BIFRCB CB3 CBC CCH COMPENSATION SELECT BIFRCA VRXP FIMODE CCL CCHL 4x IMEAS RCOMF IPAR HIZM VRXM IOSI ILIMHI ITHLO CS SCLK LOAD DIN DOUT HIZCMP EXTSEL HIZMP VEE VL VL ILIMLO SERIAL INTERFACE CONTROL AND CONFIGURATION REGISTERS IDDQSEL VTHR VCC VL AGND ITHHI HIZM VL TEMP WATCHDOG POWER-ON RESET HITEMP TEMPERATURE SUPERVISOR DGND AGND CT1 SWITCH CONTROL CT2 DGND Figure 1. Functional Diagram Detailed Description The MAX9959 device power supply (DPS) is a voltage source when the load current is between the two programmed limits and transitions gracefully into a precision current source/sink if a programmed current limit is reached. It provides voltage-control inputs that allow independent setting of the output voltage, the maximum voltage (current), and the minimum (smallest positive or most negative) voltage (current), and it can source voltages over a span of 25V at up to 800mA of current. For currents less than 200mA, the MAX9959 provides full four-quadrant operation. It supports the addition of an external buffer for sourcing and sinking higher currents, and multiple MAX9959s can be paralleled to load-share, thus realizing higher total current capability 12 with greater flexibility. Additionally, the output features two independently adjustable clamps that limit both the negative and positive output voltages or currents to externally provided limits. It offers voltage and current measurement outputs, a window comparator for go/nogo testing, a temperature monitor, a high-temperature warning flag, and a high-temperature shutdown. The MAX9959D features an internal 300k sense resistor, RFS, between RCOMF and SENSE. The MAX9959F version does not include this sense resistor. Analog Signal Polarities In force-voltage mode the output voltage (SENSE/ RCOMF in Figure 1, the Functional Diagram) is proportional to the input control voltage and determined by the choice ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) In force-current mode, the output current is proportional to the input control voltage and behaves according to the formula: IOUT = VIN 4R SENSE Positive current is defined as flowing out of the MAX9959 DPS. In high-impedance mode, outputs RA, RB, RC, and RD are high impedance. Current-Sense-Amplifier Offset Voltage Input The current-sense amplifier monitors the voltage across the output resistors connected to RA, RB, RC, and RD in Figure 1. The current-sense offset voltage input, IOSI, introduces an offset to the current-sense amplifier. When IOSI is zero relative to AGND, the nominal output voltage range of the current-sense amplifier, corresponding to a +/- full-scale output current, is -4V to +4V. Voltage applied to IOSI adds directly to this output voltage. For example, if +4V is applied to IOSI, the voltage range corresponding to +/- full-scale current becomes 0 to +8V, within the range allowed by the power-supply rails. Measure Voltage-Sense-Amplifier Offset Voltage Input The measure voltage-sense amplifier monitors the output voltage of the MAX9959. The measure offset voltage input, IOSV, introduces an offset to the measure voltage amplifier. Voltage applied to IOSV adds directly to this output voltage. External Mode Support The MAX9959 includes resources to drive an external amplifier to provide a current range beyond the highest range (or below the lowest current range) included within the device. A voltage output, AMPOUT, is provided for the input of the external amplifier, and a digital output, EXTSEL, goes high to activate the external amplifier. Feedback inputs VRXP and VRXM connect across the external amplifier's current-sense resistor. The external amplifier must have a high-impedance output when not selected (EXTSEL = low), if connected as shown in Figure 1. Parallel DPS Operation The MAX9959 allows multiple devices to be configured in parallel to increase the available DUT drive current. One DPS must be configured as the master (in FV mode), and the parallel devices must be configured as slaves (in FI slave mode). The connection between the master and slaves is made using the IPAR output and VINS input. IPAR outputs a voltage that is proportional to the DUT current and VINS provides a proportional force-current/voltage input. Up to 16 MAX9959s can be placed in parallel. Voltage Clamps Internal programmable voltage clamps limit the output voltage to the programmed values when in FI mode. Set the clamp voltage limits with inputs CLH and CLL. The clamps handle the full 800mA and are triggered by the voltage at RCOMF independent of the voltage at SENSE. Clamp enable bit, CLEN, in the serial control word, enables the voltage clamps. Current Limit Programmable and default current limits are available at the output in the FI and FV modes. When programmable current compliance is enabled, the DPS output current limits at the preprogrammed setting for each current range. When the current limit is disabled, the DPS output current limits at the default value, 147% FSR (typ), of the selected current ranges for range B, C, and D. In range A, under FI or FV conditions, the DPS output current limits at 138% FSR (typ). For currents within each selected range, the FV output behaves as a constant voltage source. When the default or programmed current compliance limits are reached, the DPS transitions to constant current mode. Current-Limit Flags The MAX9959 can flag currents within user-specified limits. This allows fast go/no-go testing in production environments. The window comparator continuously monitors the load current and compares it to inputs ITHHI and ITHLO. The comparator outputs are open collector and can be made high impedance with the serial interface. Measure Amplifier High-Impedance Modes Measure outputs VMEAS and IMEAS can be placed in a high-impedance state with logic input HIZMP or serial interface bit HIZMS. This allows busing of the measure outputs with other DPS measure outputs. Ground and DUT Ground Sense Two ground connections, AGND (analog ground) and DGND (digital ground), are both local grounds. Connect these grounds together on the printed circuit board (PCB). DUT ground-sense input, DUTGSNS, allows sensing with respect to the DUT in force voltage mode. ______________________________________________________________________________________ 13 MAX9959 of one of three +/- gain settings controlled through the serial interface. MAX9959 25V Span, 800mA Device Power Supply (DPS) Short-Circuit Protection VDUT RA, RB, RC, RD, AMPOUT, and SENSE withstand a short to any voltage between and including the supply rails. VCC - 2.5V Temperature Sensor and OverTemperature Protection The MAX9959 outputs a voltage proportional to its die temperature, at TEMP, of 10mV/K (or 10mV/C) with the nominal output voltage being 3.43V at 343K (+70C). If the temperature of the die enters the range of +120C to +140C, the open-collector output HITEMP goes low. If the die temperature exceeds +140C, the temperature sensor issues a power-on reset, placing the DPS into its high-impedance state. A reduction in temperature after a temperature-initiated reset does not return the DPS to its original operating state; reprogramming is required. Mode and Range-Change Transients Glitch minimization measures in the MAX9959 employ make-before-break switching and internal clamps to reduce output glitches. To guarantee minimum glitches between range changes, change between adjacent ranges, e.g., RA to RB, RD to RC. Do not switch to another range until the present range-change operation has been completed. In addition to the make-before-break measures, connections CT1 and CT2 are provided for optional capacitors that control the edge rate of the gate drive to the range-change switches. Two capacitors of 150pF each provide a reasonable balance between glitch control and range-change transition time. DUT Voltage Swing vs. DUT Current and Power-Supply Voltages The DUT voltage that the MAX9959 can deliver is limited by two main and two lesser factors: 1) The 2.5V overhead from each supply rail required by the amplifiers and other on-chip circuitry. 2) The voltage drop across the sense resistor and internal circuitry in series with the sense resistor. At full current the combined voltage drop is 2.5V, 1V across the resistor and 1.5V across the switches. This voltage is not all in addition to the overhead requirement. There is some overlap of the two effects; see Figure 2. 3) Variations in the system power-supply voltages. 4) Variations between the ground voltage of the device-under-test and AGND. Neglecting the effects of items 3 and 4, the output capabilities of the DPS are demonstrated by Figure 2. Figure 2 shows that for zero DUT current, the DUT voltage swing is from (VEE + 2.5V) to (VCC - 2.5V). For positive DUT currents, the maximum voltage drops off 14 VCC - 5V IDUT VEE + 5V VEE + 2.5V IMIN IMAX Figure 2. Output Swing linearly until it reaches VCC - 5V at full current. Similarly for negative DUT currents, the magnitude of the negative voltage drops off linearly until it reaches VEE + 5V. When the DPS is driving more than 200mA output current, the power dissipated by the DPS must be limited to below the power limit of the package (see the Absolute Maximum Ratings and Note 2). For example, when the DPS is driving 800mA in range A, the VCC supply must not exceed +12V, and the V EE supply must not exceed -12V. When the DPS is sourcing current, the DUT node must not be driven below zero volts. When the DPS is sinking current, the DUT node must not be driven above zero volts (two-quadrant operation). When operating below 800mA, four-quadrant operation may be possible depending on the power dissipation of the DPS. Power dissipation analysis must consider variations in the power-supply voltage and the voltage difference between the device-under-test ground and the DPS AGND (items 3 and 4 above). Since the maximum output voltage range is relative to the supply voltage, any decrease in a supply voltage from nominal proportionally decreases the range. The maximum output voltage range is also reduced by the difference between the DUT ground and the analog ground potentials (DUTGSNS - AGND). Note that within these limitations, the forced DUT voltage is equal to DUT ground plus the input control voltage. Similarly, when measuring a voltage, the measured voltage is equal to the difference between the DUT voltage and DUT ground. ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) Configuration of the MAX9959 is achieved through the serial interface, and through the dedicated logic-control inputs HIZMP, LOAD, and IDDQSEL. The serial interface has a shift register, an input register, and a DPS register (Figure 3). Serial data do not directly affect the DPS until the data reach the DPS register. Control of data flow to the DPS register is through two control bits (A0 and C0) and logic input LOAD. LOAD asynchronously transfers data from the input register into the DPS register. If LOAD is held low when data are latched into the input register, then the data transfer directly (transparently) into the DPS register. This allows changing the state of the DPS coincident with the end of serial-port data communication, or asynchronously with respect to serial-port communications. Asynchronous update using LOAD facilitates simultaneous updates of multiple daisy-chained DPS devices. When A0 = C0 = 0 (NOP), data move through the shift register to DOUT without change in mode or operation. This is useful when daisy-chaining devices to shift operational data through a number of devices to a specific device without altering some or all the device's operational data. To update multiple daisy-chained devices simultaneously use A0 = 1 and C0 = 0 to load the input register of the devices to be updated and activate LOAD after CS goes high (Figure 5). If LOAD is held low while CS is raised, data latched to the input register are also latched to the DPS register, independent of the state of C0. Table 1. Data Control Bits and Bit Order DATA BIT NAME 17 FMODE FUNCTION Mode Select 16 G2 15 G1 DPS Data Control Bits 14 G0 An 18-bit word programs the MAX9959. Table 1 outlines the 18-bit control word structure. 13 RS2 12 RS1 Serial Interface Data Flow Control Bits 11 RS0 Bits 0 and 1 (C0 and A0) specify if and how data transfers from the shift register to the input and DPS registers. The specified actions shown in Table 2 occur when CS goes high (Figures 5 and 6). 10 9 CLEN RESERV 8 HIZFRC Force High-Impedance Select 7 HIZMS Measure High-Impedance Select 6 HIZCMP 5 LCOMP1 MAX9959 CS DOUT SCLK SHIFT REGISTER DIN 2 CONTROL DECODE 16 INPUT REGISTER 16 DPS REGISTER Range Select 4 LCOMP0 3 BCOMP1 2 BCOMP0 1 A0 0 C0 Clamp Enable Reserved. Set this bit to zero. Comparator High-Impedance Select Compensation Select Serial Interface Data Flow Control Table 2. Serial Interface Data Flow Control Bits DATA BITS A0 (D1) C0 (D0) LOAD Gain and Polarity Select OPERATION 0 0 NOP: Input and DPS registers remain unchanged 0 1 Load DPS register from input register 1 0 Load input register from shift register 1 1 Load input register and DPS register from shift register TO DPS Figure 3. DPS Serial Port Block Diagram ______________________________________________________________________________________ 15 MAX9959 Configuration and Control MAX9959 25V Span, 800mA Device Power Supply (DPS) "Quick Load" Using Chip Select Mode Selection Latching data from the input register to the DPS register under standard operation of the MAX9959 requires an additional command, and/or use of LOAD. An alternative "shortcut" is to take CS low, satisfy the minimum CS low pulse-width specification, and then return it high without any coincident clock activity. Data in the input register are latched to the DPS register on the rising edge of CS. Bits D8 and D17 in the control word (HIZFRC and FMODE) select the mode of operation of the MAX9959, indicated in Table 5. FMODE selects whether the DPS forces a voltage or a current. HIZFRC determines if the driver amplifier is placed in a high-output-impedance state, or if VINS is selected as the input to the amplifier (FI slave mode). Programmable Analog Modes Current Range Selection Bits D11 to D13 of the control word (RS0, RS1, and RS2) control the full-scale current range for either FI (force current) or MI (measure current) mode. Nominal current monitor resistor values and current ranges are listed in Table 3. Table 3. Range Select Bits and Nominal Sense Resistor Values DATA BITS RS2 (D13) RS1 (D12) RS0 (D11) RANGE MAXIMUM CURRENT NOMINAL SENSE RESISTOR VALUE () 0 0 0 D 200A 5000 0 0 1 C 2mA 500 0 1 0 B 20mA 50 0 1 1 A 800mA 1.25 1 X X External -- -- X = Don't care. VIN and Measure Voltage, Variable-Gain Amplifier Selection Bits D14 to D16 of the control word (G0, G1, and G2) control the gain and polarity of the variable-gain amplifiers (VGAs). These bits also control the gain of the measure amplifier, allowing a 1:1 input-to-output voltage transfer function when in the FVMV mode. The settings are detailed in Table 4. Table 4. VGA Gain and Polarity Select Bits DATA BITS* VIN VGA MEASURE VOLTAGE VGA G2 (D16) G1 (D15) G0 (D14) 0 0 0 +1 +1 0 0 1 +2 +1/2 0 1 0 +6 +1/6 1 0 0 -1 +1 1 0 1 -2 +1/2 1 1 0 -6 +1/6 Table 5. DPS Mode Select Bits DATA BITS DPS MODE AMP INPUT OUTPUTS RA, RB, RC, AND RD 0 High Impedance AGND High Impedance 0 1 FI Slave VINS Current 1 0 FV VIN Voltage 1 1 FI VIN Current HIZFRC (D8) FMODE (D17) 0 In FV and FI modes, IMEAS and VMEAS outputs provide measurement of the DUT sense voltage or current, allowing flexible modes of operation beyond the traditional force-voltage/measure-current (FVMI) and forcecurrent/measure-voltage (FIMV) modes. The modes supported are: FVMI: Force-voltage/measure-current FIMV: Force-current/measure-voltage FVMV: FIMI: Force-voltage/measure-voltage Force-current/measure-current FNMV: Force-nothing/measure-voltage In the FV or FI modes, VIN is selected to control the forced voltage or forced current. In the FI slave mode, VINS is selected. This allows connecting a master DPS to its slaves without using external relays. Digital Interface Operation A 3-wire SPITM/QSPITM/MICROWIRETM-compatible serial interface is used for command and control of the MAX9959. The serial interface operates with clock speeds up to 20MHz. Additionally, a few logic inputs control special functions, sometimes working with the serial interface control data, sometimes overriding it. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. *States 011 and 111 are unused. 16 ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) Digital Output (DOUT) When the input data register is full, the data become available at DOUT in a first-in-first-out fashion, allowing multiple devices to be daisy-chained. Data at DOUT follow DIN with a delay of 18 clock cycles per chained unit. The digital output is clocked on the falling edge of the input clock, allowing daisy-chained devices to use the same clock signal. Digital Inputs Serial-Port Timing Digital inputs SCLK, DIN, CS, LOAD, HIZMP, and IDDQSEL incorporate hysteresis to mitigate noise and to provide compatibility with opto-isolators. Voltage threshold levels for digital inputs are determined by VTHR, and default to 1/2 VL if VTHR is left unconnected. Timing of the serial port is detailed in timing Figures 4, 5, and 6, and in the serial port timing characteristics section of the AC Electrical Characteristics table. tCH SCLK tCSSO tCSS1 tCL tCSH1 tCSHO CS tCSWH tDH tDS DIN D17 DOUT D17LAST D16 D16LAST D15 D15LAST D14 D13 D14LAST D13LAST tDO D12 D12LAST D1 D0 D1LAST D0LAST D17 tCLL LOAD Figure 4. Serial Interface Timing ______________________________________________________________________________________ 17 MAX9959 Logic Inputs and Shared Control Functions Control of the measure output high-impedance state is shared between the HIZMS bit (D7) and the logic input HIZMP. Data transfer operations from the input shift register to the two internal control registers, input and DPS, are shared between the control word's A0 and C0 bits, and logic input LOAD (see the Configuration and Control section). MAX9959 25V Span, 800mA Device Power Supply (DPS) CS INPUT REGISTERS UPDATED SCLK DIN D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 D1 D0 DOUT Q1 FIRST BIT FROM PREVIOUS WRITE Q0 D17 LAST BIT FROM PREVIOUS WRITE LOAD DPS REGISTERS UPDATED Figure 5. Serial Interface Timing with Asynchronous Loading of the DPS Register CS INPUT AND DPS REGISTERS UPDATED SCLK DIN D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 D1 D0 DOUT FIRST BIT FROM PREVIOUS WRITE Q1 Q0 LOAD = 0 Figure 6. Serial Interface Timing with Synchronous Loading of the DPS Register 18 D17 LAST BIT FROM PREVIOUS WRITE ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) Exposed Pad Leave EP unconnected or connect to VEE. Do not connect EP to ground. Lead Compensation Capacitor Selection The MAX9959 can drive widely varying load capacitances. As the load capacitance increases, the output of the DPS tends to overshoot. To counter this, lead compensation capacitor network connections are provided, each with dedicated internal switches controllable through the serial interface (Figure 1). The networks can be tailored to specific needs, such as settling time vs. overshoot, with combinations of capacitors. Control bits D5 and D4 (LCOMP1 and LCOMP0) configure compensation capacitor connections as shown in Table 6. Table 6. Lead Compensation Capacitor Selection DATA BITS COMPENSATION CAPACITOR SELECT MINIMUM CAPACITOR VALUE (pF) MAXIMUM CAPACITOR VALUE (pF) LCOMP1 (D5) LCOMP0 (D4) 0 0 None -- -- 0 1 CCOMP1 27 330 1 0 CCOMP2 27 330 1 1 CCOMP1 and CCOMP2 27 each 330 each Bypass Compensation Capacitor Selection In addition to lead compensation, the DPS also implements bypass compensation, which may be required under conditions of heavy capacitive loading. Depending on the mode selected, FV or FI, control bits D3 and D2 (BCOMP1 and BCOMP0) select different capacitors. Table 7. FV Mode Bypass Capacitor Selection DATA BITS BCOMP1 (D3) BCOMP0 (D2) BYPASS CAPACITOR SELECT 0 0 None 0 1 CB1 1 0 CB2 1 1 CB3 In the FV mode, one of three bypass capacitors (CB1, CB2, and CB3), or none is selected, as shown in Table 7. Table 8 presents the recommended CB1, CB2, and CB3 capacitor values for various load conditions. Table 8. CB1, CB2, and CB3 Recommended Values RANGE LOAD 1nF 10nF 100nF 1F 10F 100F 1000F A -- -- CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF CB3 = 22nF B -- -- CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF -- C -- CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF -- -- D CB1 = 2.7nF CB1 = 2.7nF CB2 = 10nF CB3 = 22nF -- -- -- In FI mode, the bypass capacitor combination (CCH/ CCL), or none, is selected (Table 9). Table 10 presents the recommended CCH and CCL capacitor values for various load conditions. These compensation capacitors provide improved stability for the voltage clamp circuit when driving heavy loads. Table 9. FI Mode Voltage Clamp Compensation Capacitor Selection DATA BITS FORCE-CURRENT MODE COMPENSATION CAPACITOR SELECT BCOMP1 (D3) BCOMP0 (D2) 0 0 None X 1 CCL/CCH 1 X CCL/CCH X = Don't care. ______________________________________________________________________________________ 19 MAX9959 Applications Information MAX9959 25V Span, 800mA Device Power Supply (DPS) Table 10. CCH and CCL Recommended Values (CCH = CCL) RANGE LOAD 100pF 1nF 10nF 100nF 1F 10F 100F 1000F A -- B -- -- -- 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF -- 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF C -- -- 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF -- -- D 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF -- -- -- Measure Output High-Impedance Control IDDQ Test Mode Place the measure output into a low-leakage, highimpedance state in either of two ways: with the HIZMS control bit (D7), or the digital input HIZMP. The two controls are logically AND ed, as shown in Table 11. Digital input HIZMP allows multiplexing between several DPS measure outputs without using the serial interface. While in FV mode, asserting digital input IDDQSEL switches the DPS to the minimum current range (range D), engaging the IDDQ test mode as shown in Table 13. Switching to the minimum current range through external control allows low-current IDDQ measurements without reprogramming the DPS through the serial interface. When IDDQSEL is deasserted the current range switches back to its programmed value. Table 11. Measure Output HighImpedance Control DATA BIT HIZMS (D7) DIGITAL INPUT HIZMP MEASURE OUTPUT (VMEAS, IMEAS) MODE 1 1 Measure Output Enabled 1 0 High Impedance 0 1 High Impedance 0 0 High Impedance Table 13. IDDQ Test Select DIGITAL INPUT IDDQSEL MODE 1 IDDQ Test 0 Normal Voltage (Current) Clamp Enable Control word bit CLEN (D10) enables the output clamps when high and disables the clamps when low, as indicated in Table 12. In FV mode, current compliance is active. In FI mode, voltage compliance is active. Table 12. Clamp Enable Control 20 CONTROL BIT CLEN (D10) CLAMP MODE 1 Clamps Enabled 0 Clamps Disabled ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) At power-up all analog outputs except TEMP default to high impedance. Applications Circuits EXTERNAL BUFFER AMPOUT I/O LOGIC CS SCLK LOAD DIN DOUT HIZMP RA RA RB RB MAX9959 DUT RC RC RD RD DAC V1 V2 V3 V4 V5 V6 V7 GREF VIN CLH CLL IOSI IOSV ITHHI ITHLO BIFRCA BIFRCB VRXP VRXM RCOMF SENSE EXTSEL DUTGSNS IMEAS VMEAS AGND ILIMHI ILIMLO DUTGND ADC GREF LOGIC AGND Figure 7. Single DPS Configuration ______________________________________________________________________________________ 21 MAX9959 Power-Up Configuration 25V Span, 800mA Device Power Supply (DPS) MAX9959 Applications Circuits (continued) I/O LOGIC RA RA CS SCLK LOAD DIN DOUT HIZMP RB RB DUT RC RC RD RD DAC V1 V2 V3 V4 V5 V6 V7 VIN CLH CLL IOSI IOSV ITHHI ITHLO MAX9959 BIFRCB BIFRCA DUTGND DPS1 RCOMF SENSE DUTGSNS GREF ILIMHI ILIMLO AGND IMEAS VMEAS IPAR LOGIC ADC GREF AGND VINS CS SCLK LOAD DIN DOUT HIZMP RA RA RB RB RC RC RD RD DAC V1 V2 V3 V4 V5 V6 V7 GREF VIN CLH CLL IOSI IOSV ITHHI ITHLO MAX9959 BIFRCB BIFRCA RCOMF ILIMHI ILIMLO IMEAS VMEAS LOGIC ADC GREF AGND AGND DPS2 DPS3 DPSn Figure 8. Parallel DPS Configuration Achieves Higher Output Current 22 ______________________________________________________________________________________ 25V Span, 800mA Device Power Supply (DPS) VEE VCC VCC VCC VCC VCC VCC VCC VCC VEE VEE VEE VEE VEE VEE VEE VEE VCC AMPOUT VEE N.C. N.C. N.C. VCC VEE TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RA 1 75 CCOMP2 RA 2 74 CCOMP1 RA 3 73 SAMPO RA 4 72 CCL RA 5 71 CCH RA 6 70 CCHL RA 7 69 CC2 RA 8 68 CC1 BIFRCA 9 67 CB3 RB 10 66 CB2 BIFRCB 11 65 CB1 RC 12 64 CBC MAX9959 RD 13 63 TEMP RCOMF 14 62 VMEAS SENSE 15 61 IMEAS DUTGSNS 16 60 IPAR VCC 17 59 CLH VCC 18 58 CLL VEE 19 57 AGND *EP VEE 20 56 VIN VRXP 21 55 VINS VRXM 22 54 IOSV CT1 23 53 IOSI CT2 24 52 ITHHI VCC 25 51 ITHLO VEE VCC N.C. N.C. N.C. N.C. DGND ILIMHI ILIMLO HITEMP EXTSEL DOUT DGND VL VTHR CS SCLK LOAD DIN IDDQSEL HIZMP DGND N.C. VEE N.C. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TQFP-EPR-IDP *EP = EXPOSED PAD Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE 100 TQFP-EPR-IDP C100E-8R OUTLINE LAND NO. PATTERN NO. 21-0148 90-0159 ______________________________________________________________________________________ 23 MAX9959 Pin Configuration MAX9959 25V Span, 800mA Device Power Supply (DPS) Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 2 3/07 --- 1, 6, 23 3 3/09 Added exposed pad information 2/11 Updated Absolute Maximum Ratings and DC Electrical Characteristics, and corrected pins 42 and 43 in Pin Description 4 1, 11, 12, 19, 23 2, 4, 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX9959DCCQ+D