The Kinetis Based on the ARM® Cortex®-M4 core, the K30 MCU family offers
high-precision analog integration, flexible low-power and peripheral options.
Low-power MCUs
with segment LCD
Kinetis® K30 Family
TARGET APPLICATIONS
}Thermostats
}Smart meters
}Heart rate monitors
}Blood gas analyzers
Families are built from innovative 90 nm thin-film storage
(TFS) flash technology with unique FlexMemory (EEPROM)
capability, and offer industry-leading low power and mixed
signal analog integration.
The K30 MCU family is pin, peripheral and software compatible
with the K10 MCU family and adds a flexible low-power
segment LCD controller with support for up to 320 segments.
Devices start from 64 KB of flash in 64 LQFN packages
extending up to 512 KB in a 144 MAPBGA package with a rich
suite of analog, communication, timing and control peripherals.
ONE-STOP ENABLEMENT OFFERING—MCU + IDE + RTOS
}Tower® System development board platform
}Integrated development environments
– Eclipse-based CodeWarrior® V10.x IDE and
Processor Expert®
– IAR Embedded Workbench®
– ARM® Keil® MDK
– Kinetis Design Studio IDE
}Runtime software and RTOS
– Math, DSP and encryption libraries
– Motor control libraries
– Complimentary bootloaders (USB, Ethernet, RF, serial)
– Complimentary embedded GUI
– MQX™ RTOS
– Micrium® µC/OS-III
– Express Logic ThreadX
– SEGGER embOS
– FreeRTOS
}Full ARM® ecosystem
Features Benefits
• ARM® Cortex®-M4 core with DSP
instruction support
• Up to 16-channel DMA; crossbar switch
• Up to 100 MHz core supporting a broad range of processing bandwidth needs
• Peripheral and memory servicing with reduced CPU loading
• Concurrent multi-master bus accesses for increased bus bandwidth
• Flexible, low-power LCD controller with
support for up to 320 segments
(40 x 8 or 44 x 4)
• LCD blink mode enables low average power while remaining in low-power mode
• Segment-fail detect guards against erroneous readouts and reduces LCD test costs
• Frontplane/backplane reassignment provides pin-out flexibility, easing PCB design and allows LCD configuration
changes via firmware with no hardware re-work
• Supports multiple 3 V and 5 V LCD panel sizes with fewer segments (pins) than competitive controllers and no
external components
• Unused LCD pins can be configured as other GPIO functions
• Low-power capacitive touch-sensing
interface
• Provides a modern upgrade from mechanical to touch keypad, rotary and slider user interfaces and operates
in all low-power modes with minimal current added; supports up to 16 inputs
• 10 ultra-low-power modes with flash
programming and analog operation
down to 1.71 V
• Low-power timer, low-power RTC,
low-leakage wake-up unit
• Peripheral activity and wake-up times can be optimized to suit application requirements, enabling extended
battery life (Stop currents of <500 nA, run currents of <200 μA/MHz, 4 µs wake-up from Stop)
• Continual device operation in reduced power states with flexible wake-up options
• Memory protection unit
• Hardware cyclic redundancy check
engine
• Independent-clocked COP; external
watchdog monitor
• Provides memory protection for all cross bar switch masters, increasing software reliability
• Validates memory contents and communication data, increasing system reliability
• Prevents code runaway in fail-safe applications; drives output pin to safe state external components if
watchdog event occurs
• 64–512 KB flash; up to to 128 KB
of SRAM
• 32–256 KB FlexMemory
• High reliability, fast access program memory with four levels of security protection. Independent flash banks allow
concurrent code execution and firmware updating
• FlexMemory provides 32 bytes–4 KB of user-segmentable byte write/erase EEPROM
• FlexNVM 32–256 KB for extra program code, data or EEPROM backup
Optional
Cyclic
Redundancy
Check (CRC) Low-Power
Touch-Sensing
Interface
Segment
LCD Controller
Timers
System Memories
Communication Interfaces HMI
Clocks
Internal and
External
Watchdogs
Memory
Protection Unit
(MPU)
DMA
Low-Leakage
Wake-Up Unit
Phase-Locked
Loop
Frequency-
Locked Loop
Low-/High-
Frequency
Oscillators
Internal
Reference
Clocks
Carrier
Modulator
Transmitter
Periodic
Interrupt
Timers
Independent
Real-Time
Clock (RTC)
Security
and Integrity
Analog
Core
Interrupt
Controller
Debug
Interfaces DSP
ARM® Cortex®-M4 core
72/100 MHz
16-bit
ADC
PGA
Analog
Comparator
6-bit
DAC
12-bit
DAC
Voltage
Reference
FlexTimer
Programmable
Delay Block
Low-Power
Timer
Program Flash
(64 to 512 KB)
FlexMemory
(32 to 256 KB)
(2 to 4 KB EE)
Serial
Programming
Interface (EZPort)
SRAM
(16 to 128 KB)
External
Bus Interface
(FlexBus)
GPIOI2C
UART
(ISO 7816)
SPI
CAN
I2S
Secure
Digital Host
Controller (SDHC)
KINETIS K30 FAMILY BLOCK DIAGRAM
KINETIS K30 FAMILY
Document Number:
KNTSK30FMLYFS REV 9
NXP, the NXP logo, CodeWarrior, the Energy Efficient Solutions logo, Kinetis, Processor Expert and Tower are trademarks of
NXP B.V. All other product or service names are the property of their respective owners. ARM and Cortex are registered
trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2015–2016 NXP B.V.
www.nxp.com/Kinetis
Part
Number
Memory Feature Options
Other
Packages
CPU (MHz)
Flash (KB)
Flex NVM (KB)
SRAM (KB)
Memory
Protection Unit
CAN
Secure Digital Host
Controller
External Bus Interface
12-bit DAC
Prog. Gain Amplifier
5 V Tolerant I/O
LH LK LL MC LQ MD
64 LQFP (10 x 10)
80 LQFP (12 x 12)
100 LQFP (14 x 14)
121 BGA (8 x 8)
144 LQFP (20 x 20)
144 BGA (13 x 13)
MK30DN512Vyy10 100 512 128 √ √ √ * √ √ √ Segment LCD (up to 40 x 8/44 x 4) √ √ √ √ √
MK30DX64Vyy7 72 64 32 16 √ √ √ √ Segment LCD (up to 24 x 8/28 x 4) √ √ √
MK30DX128Vyy7 72 128 32 32 √ √ √ √ Segment LCD (up to 38 x 8/42 x 4) √ √ √ √
MK30DX256Vyy7 72 256 32 64 √ √ √ √ Segment LCD (up to 38 x 8/42 x 4) √ √ √
MK30DX128yy10 100 128 128 32 √ √ √ √ √ √ √ Segment LCD (up to 40 x 8/44 x 4) √ √
MK30DX256yy10 100 256 256 64 √ √ √ √ √ √ √ Segment LCD (up to 40 x 8/44 x 4) √ √
yy = Package designator
*144pin only
KINETIS K30 FAMILY OPTIONS
