ee FAIRCHILD ns SEMICONDUCTOR 74F112 April 1988 Revised July 1999 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip- flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig- gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affect- ing the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on Sp or Cp prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on Sp and Cp force both Q and QHIGH. Asynchronous Inputs: LOW input to Sp sets Q to HIGH level LOW input to Cp sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on Cp and Sp makes both Q and Q HIGH Ordering Code: Order Number | Package Number Package Description 74F1128C M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F1128J M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide 74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols Spt sa 1 O Coy T b S D2 J2 Q%F Ocr, ke %O yg 7 IEEE/IEC Sp; NS yo % cP} pc, Kyqy zoe Si Q H cP, k a Co Connection Diagram a <= Q 3 1 2 Ol iy wa ns oe nN wi og iy Stn to Te te I? |e FF As fe Fe [| Sl To nN Da nN 1999 Fairchild Semiconductor Corporation Dso009472 www. fairchildsemi.com doj3-dij4 poi06bi4,-e6py eaneben yr lend ZLlarZ74F112 Unit Loading/Fan Out ULL. Input Iia/iL Pin Names Description HIGH/LOW | Output Iow/lot J, Jo, Ky, Ko |Data Inputs 1.0/1.0 |20 LA/-0.6 mA CP,, CP. Clock Pulse Inputs (Active Falling Edge) } 1.0/4.0 |20 pA/-2.4mA Cp1. Cpe Direct Clear Inputs (Active LOW) 1.0/5.0 |20pA/-3.0 mA Spi; Spe Direct Set Inputs (Active LOW) 1.0/5.0 |20 pA/-3.0 mA Qj, Qy, Q;, Qp | Outputs 50/33.3. | -1 mA/20 mA Truth Table Inputs Outputs S Cp CP J K Q a L H x x x H L H L x x x L H L L x x x H H H H NN h h Q Q H H ~N | h L H H H ~N h | H L H H NN | | Q Q H (h) = HIGH Voltage Level L (I) = LOW Voltage Level X = Immaterial ~ = HIGH-to-LOW Clock Transition Qy(Qy) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) Cy J cp Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www. fairchildsemi.com 2Absolute Maximum Ratingsvnote 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Voc Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with Voc = OV) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) -65C to +150C 55C to +125C 55C to +150C 0.5V to +7.0V 0.5V to +7.0V -30 mA to +5.0 mA -0.5V to Vee 0.5V to +5.5V Recommended Operating Conditions 0C to +70C +4.5V to +5.5V Free Air Ambient Temperature Supply Voltage Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated Io, (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Units Veco Conditions Vin Input HIGH Voltage 2.0 Vv Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 Vv Recognized as a LOW Signal Vop Input Clamp Diode Voltage 1.2 Vv Min lin =-18 mA Vou Output HIGH 10% Voc 25 Vv Min lou =-1 mA Voltage 5% Voc 27 loy =-1 mA Voi Output LOW 10% Voc 0.5 Vv Min lol = 20 mA Voltage lin Input HIGH 5.0 HA Max Vn=2.7V Current Ibvl Input HIGH Current 7.0 HA Max Vin =7.0V Breakdown Test | Output HIGH CEX P 50 A Max | Vour=Vee Leakage Current Vv Input Leakage lip =1.9pA ID P' 9 475 Vv 00 ID M Test All other pins grounded | Output Leakage Viop = 150 mV OD py we} 3.75 pA 00 lob Circuit Current All other pins grounded lit Input LOW Current 0.6 Vin =0.5V (Jn, Ky) -2.4 mA Max | Vi) =0.5V (CP,) 3.0 Vin =0.5V (Con, Spn) log Output Short-Circuit Current 60 150 mA Max Vout =0V locu Power Supply Current 12 19 mA Max Vo = HIGH loot Power Supply Current 12 19 mA Max Vo =LOW 3 www fairchildsemi.com cllavlAC Electrical Characteristics 74F112 Ta =+25C Ta = 0C to +70C Symbol Parameter Veo= 15.0V Vee = 5.0V Units C,_ = 50 pF C_ = 50 pF Min Typ Max Min Max fMax Maximum Clock Frequency 85 105 80 MHz teLy Propagation Delay 2.0 5.0 6.5 2.0 7.5 tra GP, to Q, or @, 2.0 5.0 65 2.0 75 ns tpLH Propagation Delay 2.0 45 6.5 2.0 7.5 tPHL Cpm Spn to Qn, Qn 2.0 45 6.5 2.0 75 ns AC Operating Requirements Ta =+25C Ta =0C to +70C Symbol Parameter Voc = +5.0V Voc =+5.0V Units Min Max Min Max tg(H) Setup Time, HIGH or LOW 4.0 5.0 tg(L) Jn or K, to CP, 3.0 3.5 ty(H) Hold Time, HIGH or LOW 0 0 ns tu) J, ot K, to CP, 0 0 tw(H) CP Pulse Width 45 5.0 ns tw(L) HIGH or LOW 45 5.0 tw(L) Pulse Width, LOW 45 50 ns Con OF Son tRec Recovery Time Som Son too 4.0 5.0 ns www. fairchildsemi.com 4Physical Dimensions inches (millimeters) unless otherwise noted 0.150 0.157 (3.810 3.988) 0.100.020 pec at ay (0.254 0.508) | B MAX TYP ALL LEADS t 0.008 0.010 (0.203 0.254) TYP ALL LEADS Q|0.006 (0.15) \ <- 0.386 0.304 (9-804 10.00) 615 141312 O18 pAanAAAA n2ze nase 40 (5.791 6.198) TYP LL A POUGUY Ua ty LEAD No.1 7/1 2 3 4 5 6 7 8 f IDENT 0.010 tax (0.254) 0.0530.069 (1.346 -1.753) 0.004 _ 0,010 (0.102 0.254) Y 7} FS Fy Fat SEATING PLANE A t i A | i PLANE 0.014 0 Paaae 0.050 0.0140.020 pyp a ae (0.356) (1.270) | 19.356 0.508) 0.004 TYP ALL LEADS TYP 0.008 (0.102) mI 203) TP W-OA REV HH ALL LEAD TIPS 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M1i6A 16 9 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) 1 8 7 0.5947 0.402 0.71 0.006-0.010 (10.0-10.2) (Tey? (0.15-0.25) YP TIT IT ITI TATA / yen a-8 TYP \G TYP | |. 0.000-0.010 * -| (0-0,25) 0.014-0.020 obs) TYP (0.35-0.50) TYP *| es M16D (REV B) 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M16D www. fairchildsemi.com cllavl74F112 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 0.740 = 0.780 (18.80 - 19.81) >| 0.090 | 2.286) INDEX AREA 0,250 40.010 (6.350 0.254) PIN NO. 1 PIN NO. 1 IDENT IDENT OPTION 01 OPTION 02 0.065 0.130#0.005 01.651) 0:150#0.005- 0.060 4 TYP 0.500 0.520. (1.651) \ (3.302 40.127) =| [- (rs2ay TYP ~\ > OPTIONAL 7 (7.620 = 8.128) f- { 0.145 = 0.200 ! | (3.683-5.080) } A I 95 5 0.008 = 0.016 Oo oO . i! 0.020 jy | 9005 4 TYP (0.203- 0.406) (0.508) 0.2860" 0.125 - 0.150 0.030 0.015 (7.112) (3.175 = 3.810) , | (0.7620.381) MIN 0.014 = 0.023 0.100 #0.010 +0.040 0.014 = 0.023 70.100 0.010 | 0.325 (0.356 - 0.584) soso too! (2.540 0,254) (0.525 -9'015 N16E (REV F) TP (1.270 0.254) P (8.255*1,918) TYP 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. www. fairchildsemi.com 6