DAC8718 DA C 871 8 DA C8 71 8 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8718 FEATURES DESCRIPTION * * * * * * The DAC8718 is a low-power, octal, 16-bit digital-to-analog converter (DAC). With a 5V reference, the output can either be a bipolar 15V voltage when operating from dual 15.5V (or higher) power supplies, or a unipolar 0V to +30V voltage when operating from a +30.5V (or higher) power supply. With a 5.5V reference, the output can either be a bipolar 16.5V voltage when operating from dual 17V (or higher) power supplies, or a unipolar 0V to +33V voltage when operating from a +33.5V (or higher) power supply. This DAC provides low-power operation, good linearity, and low glitch over the specified temperature range of -40C to +105C. This device is trimmed in manufacturing and has very low zero-code and gain error. In addition, system level calibration can be performed to achieve 1 LSB bipolar zero/full-scale error with bipolar supplies, or 1 LSB zero code/full-scale error with a unipolar supply, over the entire signal chain. The output range can be offset by using the DAC offset register. 1 2345 * * * * * * * * * * Bipolar Output: 2V to 16.5V Unipolar Output: 0V to +33V 16-Bit Resolution Low Power: 14.4mW/Ch (Bipolar Supply) Relative Accuracy: 4 LSB Max Low Zero/Full-Scale Error - Before User Calibration: 10 LSB Max - After User Calibration: 1 LSB Flexible System Calibration Low Glitch: 4nV-s Settling Time: 15s Channel Monitor Output Programmable Gain: x4/x6 Programmable Offset SPITM: Up to 50MHz, 1.8V/3V/5V Logic Schmitt Trigger Inputs Daisy-Chain with Sleep Mode Enhancement Packages: QFN-48 (7x7mm), TQFP-64 (10x10mm) APPLICATIONS * * * Automatic Test Equipment PLC and Industrial Process Control Communications IOVDD DGND DVDD AVDD AVSS REF-A DAC8718 Analog Monitor CS SDI SDO RST RSTSEL LDAC CLR USB/BTC GPIO-0 GPIO-1 GPIO-2 Control Logic SCLK Reference Buffer A OFFSET DAC A Command To DAC-0, DAC-1, Registers DAC-2, DAC-3 (When Correction Engine Disabled) Input Data Register 0 Correction Engine VOUT-7 AIN-0 AIN-1 Ref Buffer A Ref Buffer B OFFSET-B VMON The DAC8718 is pin-to-pin and function-compatible with the DAC8218 (14-bit) and the DAC7718 (12-bit). OFFSET-A DAC-0 DAC-0 Data Mux SPI Shift Register VOUT-0 WAKEUP The DAC8718 features a standard, high-speed serial peripheral interface (SPI) that operates at up to 50MHz and is 1.8V, 3V, and 5V logic compatible, to communicate with a DSP or microprocessor. The input data of the device are double-buffered. An asynchronous load input (LDAC) transfers data from the DAC data register to the DAC latch. The asynchronous CLR input sets the output of all eight DACs to AGND. The VMON pin is a monitor output that connects to the individual analog outputs, the offset DAC, the reference buffer outputs, and two external inputs through a multiplexer (mux). VOUT-0 Latch-0 To DAC-0, DAC-1, DAC-2, DAC-3 Internal Trimming Zero/Gain; INL LDAC User Calibration: Zero Register 0 Gain Regsiter 0 AGND-A To DAC-4, DAC-5, DAC-6, DAC-7 OFFSET-B Reference Buffer B (Same Function Blocks for All Channels) AIN-0 OFFSET DAC B AGND-B Power-Up/ Power-Down Control VOUT-7 AIN-1 DGND DVDD AVDD AVSS REF-B 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DSP is a trademark of Texas Instruments. SPI, QSPI are trademarks of Motorola Inc. Microwire is a trademark of National Semiconductor. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT RELATIVE ACCURACY (LSB) DIFFERENTIAL LINEARITY (LSB) 4 4 DAC8718 (1) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING 1 QFN-48 RGZ -40C to +105C DAC8718 1 TQFP-64 PAG -40C to +105C DAC8718 For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). DAC8718 UNIT AVDD to AVSS -0.3 to 38 V AVDD to AGND -0.3 to 38 V AVSS to AGND, DGND -19 to 0.3 V DVDD to DGND -0.3 to 6 V IOVDD to DGND -0.3 to min of (6 or DVDD + 0.3) V -0.3 to 0.3 V Digital input voltage to DGND -0.3 to IOVDD + 0.3 V SDO to DGND -0.3 to IOVDD + 0.3 V VOUT-x, VMON, AIN-x to AVSS -0.3 to AVDD + 0.3 V -0.3 to DVDD V AGND-x to DGND REF-A, REF-B to AGND GPIO-n to DGND -0.3 to IOVDD + 0.3 V GPIO-n input current 5 mA Maximum current from VMON 3 mA Operating temperature range -40 to +105 C Storage temperature range -65 to +150 C Maximum junction temperature (TJ max) +150 C 2.5 kV Charged device model (CDM) 1000 V Machine model (MM) 200 V TQFP 55 C/W QFN 27.5 C/W TQFP 21 C/W QFN 10.8 C/W (TJ max - TA) / JA W Human body model (HBM) ESD ratings Junction-to-ambient, JA Thermal impedance Junction-to-case, JC Power dissipation (1) 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = -16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT 4 LSB STATIC PERFORMANCE (2) Resolution 16 Bits Linearity error Measured by line passing through codes 0000h and FFFFh Differential linearity error Measured by line passing through codes 0000h and FFFFh 1 LSB TA = +25C, before user calibration, gain = 6, code = 8000h 10 LSB TA = +25C, before user calibration, gain = 4, code = 8000h 15 LSB 2 ppm FSR/C TA = +25C, gain = 6, code = 0000h 10 LSB TA = +25C, gain = 4, code = 0000h 15 LSB 3 ppm FSR/C TA = +25C, gain = 6 10 LSB TA = +25C, gain = 4 15 LSB Bipolar zero error TA = +25C, after user calib., gain = 4 or 6, code = 8000h Bipolar zero error TC Zero-code error Zero-code error TC Gain error Gain error TC Full-scale error Gain = 4 or 6, code = 8000h Gain = 4 or 6, code = 0000h Gain = 4 or 6 0.5 1 LSB 3 ppm FSR/C 10 LSB TA = +25C, before user calibration, gain = 4, code = FFFFh 15 LSB 3 ppm FSR/C Full-scale error TC Gain = 4 or 6, code = FFFFh DC crosstalk (3) Measured channel at code = 8000h, full-scale change on any other channel (2) (3) 0.5 TA = +25C, before user calibration, gain = 6, code = FFFFh TA = +25C, after user calib., gain = 4 or 6, code = FFFFh (1) 1 1 0.5 0.2 LSB LSB Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary no more than 10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and must not be connected during dual-supply operation. Gain = 4 and TC specified by design and characterization. The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 3 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = -16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT V ANALOG OUTPUT (VOUT-0 to VOUT-7) (4) Voltage output (5) Output impedance VREF = +5V -15 +15 VREF = +1.5V -4.5 +4.5 V 0.5 Code = 8000h Short-circuit current (6) Load current Output drift vs time 8 3 mA TA = +25C, device operating for 500 hours, full-scale output 3.4 ppm of FSR TA = +25C, device operating for 1000 hours, full-scale output 4.3 Capacitive load stability Settling time Slew rate ppm of FSR 500 pF To 0.03% of FSR, CL = 200pF, RL= 10k, code from 0000h to FFFFh and FFFFh to 0000h 10 s To 1 LSB, CL = 200pF, RL = 10k, code from 0000h to FFFFh and FFFFh to 0000h 15 s To 1 LSB, CL = 200pF, RL = 10k, code from 7F00h to 8100h and 8100h to 7F00h 6 s 6 V/s (7) Power-on delay (8) mA See Figure 37 From IOVDD +1.8V and DVDD +2.7V to CS low Power-down recovery time 200 s 60 s 4 nV-s 5 mV Digital-to-analog glitch (9) Code from 7FFFh to 8000h and 8000h to 7FFFh Glitch impulse peak amplitude Code from 7FFFh to 8000h and 8000h to 7FFFh Channel-to-channel isolation (10) VREF = 4VPP, f = 1kHz 88 dB DACs in the same group 7.5 nV-s DAC-to-DAC crosstalk (11) 1 nV-s Digital crosstalk (12) 1 nV-s Digital feedthrough (13) 1 Output noise DACs among different groups 200 nV/Hz TA = +25C at 10kHz, gain = 4 130 nV/Hz 20 VPP 0.05 LSB 0.1Hz to 10Hz, gain = 6 Power-supply rejection (14) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) 4 nV-s TA = +25C at 10kHz, gain = 6 AVDD = 15.5V to 16.5V Specified by design. The analog output range of VOUT-0 to VOUT-7 is equal to (6 x VREF - 5 x OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of the analog output must not be greater than (AVDD - 0.5V), and the minimum value must not be less than (AVSS + 0.5V). All specifications are for a 16.5V power supply and a 15V output, unless otherwise noted. When the output current is greater than the specification, the current is clamped at the specified maximum value. Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale. Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid digital communication. Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format. Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale. DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s. Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s. Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s. The output must not be greater than (AVDD - 0.5V) and not less than (AVSS + 0.5V). Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = -16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER OFFSET DAC OUTPUT (15) CONDITIONS MIN TYP MAX UNIT (16) Voltage output VREF = +5V Full-scale error TA = +25C 0 4 LSB Zero-code error TA = +25C 2 LSB Linearity error 5 6 Differential linearity error V LSB 1 LSB ANALOG MONITOR PIN (VMON) Output impedance (17) TA = +25C Three-state leakage current 2 k 100 nA AUXILIARY ANALOG INPUT Input range AVSS Input impedance (AIN-x to VMON) Input capacitance TA = +25C AVDD V 2 (15) Input leakage current k 4 pF 30 nA REFERENCE INPUT Reference input voltage range (18) 1.0 5.5 V Reference input dc impedance 10 M Reference input capacitance (15) 10 pF DIGITAL INPUT (15) High-level input voltage, VIH Low-level input voltage, VIL Input current IOVDD = +4.5V to +5.5V 3.8 0.3 + IOVDD V IOVDD = +2.7V to +3.3V 2.3 0.3 + IOVDD V IOVDD = +1.7V to 2.0V 1.5 0.3 + IOVDD V IOVDD = +4.5V to +5.5V -0.3 0.8 V IOVDD = +2.7V to +3.3V -0.3 0.6 V IOVDD = +1.7V to 2.0V -0.3 0.3 V 1 A 5 A CLR, LDAC, RST, CS, and SDI USB/BTC, RSTSEL, and GPIO-n CLR, LDAC, RST, CS, and SDI Input capacitance 5 pF USB/BTC and RSTSEL 12 pF GPIO-n 14 pF DIGITAL OUTPUT (15) High-level output voltage, VOH (SDO) IOVDD = +2.7V to +5.5V, sourcing 1mA IOVDD - 0.4 IOVDD V 1.6 IOVDD V Low-level output voltage, VOL (SDO) IOVDD = +2.7V to +5.5V, sinking 1mA 0 0.4 V IOVDD = +1.8V, sinking 200A 0 0.2 V GPIO-n output voltage low, VOL 1mA sink from IOVDD GPIO-n output voltage high, VOH 10k pull-up resistor to IOVDD High-impedance leakage current SDO and GPIO-n High-impedance output capacitance SDO IOVDD = +1.8V, sourcing 200A GPIO-n 0.15 V 5 A 5 pF 14 pF 0.99 x IOVDD V (15) Specified by design. (16) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary no more than 10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and must not be connected during dual-supply operation. (17) 8k when VMON is connected to Reference Buffer A or B, and 4k when VMON is connected to Offset DAC-A or -B. (18) Reference input voltage DVDD. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 5 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = -16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD +4.5 +18 V AVSS -18 -4.5 V DVDD +2.7 +5.5 V IOVDD (19) +1.8 +5.5 Normal operation, midscale code, output unloaded AIDD 4.3 35 A mA Power down, output unloaded 35 A Normal operation 78 A Power down 36 A Normal operation, VIH = IOVDD, VIL = DGND 5 A Power down, VIH = IOVDD, VIL = DGND 5 Normal operation, midscale code, output unloaded DIDD IOIDD Power dissipation V mA -2.7 Power down, output unloaded AISS 6 -4 Normal operation, 16.5V supplies, midscale code 115 A 165 mW +105 C TEMPERATURE RANGE Specified performance -40 (19) IOVDD DVDD. 6 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT 4 LSB STATIC PERFORMANCE (1) Resolution 16 Bits Linearity error Measured by line passing through codes 0100h and FFFFh Differential linearity error Measured by line passing through codes 0100h and FFFFh 1 LSB TA = +25C, before user calibration, gain = 6, code = 0100h 10 LSB TA = +25C, before user calibration, gain = 4, code = 0100h 15 LSB 3 ppm FSR/C TA = +25C, gain = 6 10 LSB TA = +25C, gain = 4 15 LSB 3 ppm FSR/C TA = +25C, before user calibration, gain = 6, code = FFFFh 10 LSB TA = +25C, before user calibration, gain = 4, code = FFFFh 15 LSB 3 ppm FSR/C Unipolar zero error TA = +25C, after user calib., gain = 4 or 6, code = 0100h Unipolar zero error TC Gain error Gain error TC Full-scale error 1 Gain = 4 or 6, code = 0100h 0.5 Gain = 4 or 6 1 TA = +25C, after user calib., gain = 4 or 6, code = FFFFh Full-scale error TC Gain = 4 or 6, code = FFFFh DC crosstalk (2) Measured channel at code = 8000h, full-scale change on any other channel ANALOG OUTPUT (VOUT-0 to VOUT-7) Voltage output (4) Output impedance Output drift vs time 1 0.5 0.2 0 +30 VREF = +1.5V 0 +9 V 0.5 Code = 8000h 8 mA TA = +25C, device operating for 500 hours, full-scale output 3.4 ppm of FSR TA = +25C, device operating for 1000 hours, full-scale output 4.3 10 s To 1 LSB, CL = 200pF, RL = 10k, code from 0100h to FFFFh and FFFFh to 0100h 15 s To 1 LSB, CL = 200pF, RL = 10k, code from 7F00h to 8100h and 8100h to 7F00h 6 s 6 V/s From IOVDD +1.8V and DVDD +2.7V to CS low Glitch impulse peak amplitude Code from 7FFFh to 8000h and 8000h to 7FFFh Channel-to-channel isolation (9) VREF = 4VPP, f = 1kHz (8) (9) pF To 0.03% of FSR, CL = 200pF, RL= 10k, code from 0100h to FFFFh and FFFFh to 0100h Code from 7FFFh to 8000h and 8000h to 7FFFh (5) (6) (7) ppm of FSR 500 Digital-to-analog glitch (8) (3) (4) mA 3 Power-down recovery time (1) (2) V See Figure 84 and Figure 85 Slew rate (6) Power-on delay (7) LSB VREF = +5V Capacitive load stability Settling time LSB (3) Short-circuit current (5) Load current LSB s 200 90 s 4 nV-s 5 mV 88 dB Gain = 4 and TC specified by design and characterization. The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk. Specified by design. The analog output range of VOUT-0 to VOUT-7 is equal to (6 x VREF) for gain = 6. The maximum value of the analog output must not be greater than (AVDD - 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted. When the output current is greater than the specification, the current is clamped at the specified maximum value. Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale. Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid digital communication. Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format. Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 7 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT 10 nV-s 1 nV-s Digital crosstalk (11) 1 nV-s Digital feedthrough (12) 1 DAC-to-DAC crosstalk (10) Output noise DACs in the same group DACs among different groups 200 nV/Hz TA = +25C at 10kHz, gain = 4 130 nV/Hz 20 VPP 0.05 LSB 0.1Hz to 10Hz, gain = 6 Power-supply rejection (13) nV-s TA = +25C at 10kHz, gain = 6 AVDD = +33V to +36V ANALOG MONITOR PIN (VMON) Output impedance (14) TA = +25C Three-state leakage current 2 k 100 nA AUXILIARY ANALOG INPUT Input range Input impedance (AIN-x to VMON) AVSS TA = +25C AVDD 2 V k Input capacitance (15) 4 pF Input leakage current 30 nA REFERENCE INPUT Reference input voltage range (16) 1.0 5.5 V Reference input dc impedance 10 M Reference input capacitance (15) 10 pF DIGITAL INPUT (15) High-level input voltage, VIH Low-level input voltage, VIL Input current IOVDD = +4.5V to +5.5V 3.8 0.3 + IOVDD V IOVDD = +2.7V to +3.3V 2.3 0.3 + IOVDD V IOVDD = +1.7V to 2.0V 1.5 0.3 + IOVDD V IOVDD = +4.5V to +5.5V -0.3 0.8 V IOVDD = +2.7V to +3.3V -0.3 0.6 V IOVDD = +1.7V to 2.0V -0.3 0.3 V 1 A 5 A CLR, LDAC, RST, CS, and SDI USB/BTC, RSTSEL, and GPIO-n CLR, LDAC, RST, CS, and SDI Input capacitance 5 pF USB/BTC and RSTSEL 12 pF GPIO-n 14 pF (10) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s. (11) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s. (12) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s. (13) The analog output must not be greater than (AVDD - 0.5V). (14) 8k when VMON is connected to Reference Buffer A or B, and 4k when VMON is connected to Offset DAC-A or -B. (15) Specified by design. (16) Reference input voltage DVDD. 8 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT IOVDD - 0.4 IOVDD V 1.6 IOVDD V DIGITAL OUTPUT (17) High-level output voltage, VOH (SDO) IOVDD = +2.7V to +5.5V, sourcing 1mA Low-level output voltage, VOL (SDO) IOVDD = +2.7V to +5.5V, sinking 1mA 0 0.4 V IOVDD = +1.8V, sinking 200A 0 0.2 V GPIO-n output voltage low, VOL 1mA sink from IOVDD IOVDD = +1.8V, sourcing 200A GPIO-n output voltage high, VOH 10k pull-up resistor to IOVDD V 5 A 5 pF 14 pF 0.99 x IOVDD High-impedance leakage current SDO and GPIO-n High-impedance output capacitance 0.15 SDO GPIO-n V POWER SUPPLY AVDD +9 +36 V DVDD +2.7 +5.5 V IOVDD (18) +1.8 +5.5 V AIDD DIDD IOIDD Power dissipation Normal operation, midscale code, output unloaded 4.5 Power down, output unloaded 35 A Normal operation 70 A Power down 36 A Normal operation, VIH = IOVDD, VIL = DGND 5 A Power down, VIH = IOVDD, VIL = DGND 5 Normal operation 140 7 mA A 225 mW +105 C TEMPERATURE RANGE Specified performance -40 (17) Specified by design. (18) IOVDD DVDD. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 9 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com FUNCTIONAL BLOCK DIAGRAM IOVDD DGND DVDD AVDD AVSS REF-A DAC8718 Analog Monitor SCLK CS SDI SDO RST RSTSEL LDAC CLR USB/BTC GPIO-0 GPIO-1 GPIO-2 Control Logic Reference Buffer A OFFSET DAC A Command Registers To DAC-0, DAC-1, DAC-2, DAC-3 (When Correction Engine Disabled) Input Data Register 0 Correction Engine DAC-0 Data VMON OFFSET-A DAC-0 VOUT-0 Latch-0 To DAC-0, DAC-1, DAC-2, DAC-3 LDAC User Calibration: Zero Register 0 Gain Regsiter 0 VOUT-7 AIN-0 AIN-1 Ref Buffer A Ref Buffer B OFFSET-B Mux WAKEUP SPI Shift Register VOUT-0 Internal Trimming Zero/Gain; INL AGND-A To DAC-4, DAC-5, DAC-6, DAC-7 OFFSET-B Reference Buffer B (Same Function Blocks for All Channels) OFFSET DAC B AIN-0 AGND-B Power-Up/ Power-Down Control VOUT-7 AIN-1 DGND DVDD AVDD AVSS REF-B Figure 1. Functional Block Diagram 10 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 PIN CONFIGURATIONS VOUT-3 REF-A 4 45 5 44 DGND NC RSTSEL USB/BTC 39 38 37 IOVDD 41 40 SCLK DVDD AIN-1 42 46 CS 3 44 NC AIN-0 43 AVDD 47 SDO 48 2 SDI 1 NC 45 AVDD LDAC 49 46 50 WAKEUP 51 48 52 47 USB/BTC 53 NC 54 NC 55 RSTSEL 56 DGND 57 RGZ PACKAGE QFN-48 (TOP VIEW) NC 58 IOVDD 59 SCLK 60 DVDD 61 SDI 62 CS 63 SDO LDAC 64 NC NC WAKEUP PAG PACKAGE TQFP-64 (TOP VIEW) AVDD 1 36 AVDD AIN-0 2 35 AIN-1 VOUT-3 3 34 VOUT-4 REF-A 4 33 REF-B VOUT-4 REF-B VOUT-2 6 43 VOUT-5 VOUT-1 7 42 VOUT-6 VOUT-2 5 32 VOUT-5 AGND-A 8 41 AGND-B VOUT-1 6 31 VOUT-6 AGND-A 9 40 AGND-B AGND-A 7 30 AGND-B OFFSET-A 10 39 OFFSET-B AGND-A 8 29 AGND-B OFFSET-A 9 28 OFFSET-B 10 27 VOUT-7 DAC8718 VOUT-0 11 38 AVSS 12 37 DAC8718 VOUT-7 AVSS (1) 20 21 22 23 24 NC DGND GPIO-1 GPIO-0 32 DGND 31 19 30 NC 29 17 28 18 27 NC 26 DVDD 25 16 24 NC 23 15 22 RST 21 13 20 14 19 CLR 18 GPIO-2 17 NC NC NC 33 GPIO-1 NC NC 16 GPIO-0 25 DGND 12 NC VMON NC NC DVDD 34 DGND AVSS NC 15 NC 26 NC 11 RST AVSS CLR NC GPIO-2 NC 35 NC 36 VMON 14 NC NC 13 VOUT-0 The thermal pad is internally connected to the substrate. This pad can be connected to AVSS or left floating. Keep the thermal pad separate from the digital ground, if possible. PIN DESCRIPTIONS (1) PIN NO. PIN NAME QFN-48 TQFP-64 I/O AVDD 1 1 I Positive analog power supply DESCRIPTION AIN-0 2 3 I Auxiliary analog input 0, directly routed to the analog mux VOUT-3 3 4 O DAC-3 output REF-A 4 5 I Group A (1) reference input VOUT-2 5 6 O DAC-2 output VOUT-1 6 7 O DAC-1 output AGND-A 7 8 I Group A analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND. AGND-A 8 9 I Group A analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND. OFFSET-A 9 10 O OFFSET DAC-A analog output. Must be connected to AGND-A during single power-supply operation (AVSS = 0V). This pin is not intended to drive an external load. VOUT-0 10 11 O DAC-0 output AVSS 11 12 I Negative analog power supply VMON 12 14 O Analog monitor output. This pin is either in Hi-Z status, connected to one of the eight DAC outputs, reference buffer outputs, offset DAC outputs, or one of the auxiliary analog inputs, depending on the content of the Monitor Register. See the Monitor Register, Table 12, for details. GPIO-2 13 19 I/O General-purpose digital input/output 2. This pin is a bidirectional digital input/output, open-drain and requires an external pull-up resistor. See the GPIO Pins section for details. CLR 14 20 I Clear input, level triggered. When the CLR pin is logic '0', all VOUT-X pins connect to AGND-x through switches and internal low-impedance. When the CLR pin is logic '1', all VOUT-X pins connect to the amplifier outputs. RST 15 21 I Reset input (active low). Logic low on this pin resets the DAC registers and DACs to the values defined by the RSTSEL pin. CS must be logic high when RST is active. Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 11 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com PIN DESCRIPTIONS (continued) PIN NAME QFN-48 TQFP-64 I/O DVDD 17 24 I Digital power supply DGND 20 25 I Digital ground DGND 22 28 I Digital ground GPIO-1 23 29 I/O General-purpose digital input/output 1. This pin is a bidirectional digital input/output, open-drain and requires an external resistor. See the GPIO Pins section for details. GPIO-0 24 30 I/O General-purpose digital input/output 0. This pin is a bidirectional digital input/output, open-drain and requires an external resistor. See the GPIO Pins section for details. DESCRIPTION AVSS 26 37 I Negative analog power supply VOUT-7 27 38 O DAC-7 output OFFSET-B 28 39 O OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation (AVSS = 0V). AGND-B 29 40 I Group B (1) analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND. AGND-B 30 41 I Group B analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND. VOUT-6 31 42 O DAC-6 output VOUT-5 32 43 O DAC-5 output REF-B 33 44 I Group B reference input VOUT-4 34 45 O DAC-4 output AIN-1 35 46 I Auxiliary analog input 1, directly routed to the analog mux AVDD 36 48 I Positive analog power supply USB/BTC 37 50 I Data format selection of Input DAC data and Offset DAC data. Data are in straight binary format when connected to DGND or in twos complement format when connected to IOVDD. The command data are always in straight binary format. Refer to Input Data Format section for details. RSTSEL 38 51 I Output reset selection. Selects the output voltage on the VOUT pin after power-on or hardware reset. Refer to the Power-On Reset section for details. DGND 40 54 I Digital ground IOVDD 41 55 I Interface power DVDD 42 56 I Digital power supply SCLK 43 57 I SPI bus serial clock input CS 44 58 I SPI bus chip select input (active low). Data are not clocked into SDI unless CS is low. When CS is high, SDO is in a high-impedance state and the SCLK and SDI signals are blocked from the device. SDI 45 59 I SPI bus serial data input SDO 46 61 O SPI bus serial data output. When the DSDO bit = '0', the SDO pin works as an output in normal operation. When the DSDO bit = '1', SDO is always in a Hi-Z state, regardless of the CS pin status. Refer to the Timing Diagrams section for details. LDAC 47 62 I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. See the Updating the DAC Outputs section for details. If asynchronous mode is desired, LDAC must be permanently tied low before power is applied to the device. If synchronous mode is desired, LDAC must be logic high during power-on. WAKEUP 48 63 I Wake-up input (active low). Restores the SPI from sleep to normal operation. See the Daisy-Chain Operation section for details. 16, 18, 19, 21, 25, 39 2, 13, 15-18, 22, 23, 26, 27, 31-36, 47, 49, 52, 53, 60, 64 -- NC 12 PIN NO. Not connected Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TIMING DIAGRAMS Case 1: Standalone mode: Update without LDAC pin; LDAC pin tied to logic low. t8 t4 CS t7 t1 Input Data Register and DAC Latch Updated When Correction Completes(1) SCLK t2 t5 t6 BIT 22 BIT 23 (MSB) SDI LDAC t3 BIT 1 BIT 0 Low NOTE: (1) If the correction engine is off, the DAC latch is reloaded immediately after the DAC Data Register is updated. Case 2: Standalone mode: Update with LDAC pin. t8 t4 CS t7 t1 Input Data Register Updated, but DAC Latch is Not Updated SCLK t2 t3 t5 BIT 23 (MSB) SDI LDAC t6 BIT 22 BIT 1 BIT 0 t9 High DAC Latch Updated t10 (2) NOTE: (2) The DAC latch is updated when LDAC goes low, as long as the timing requirement of t9 is satisfied. = Don't Care Bit 23 = MSB Bit 0 = LSB Figure 2. SPI Timing for Standalone Mode Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 13 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TIMING DIAGRAMS (continued) Case 3: Daisy-Chain Mode: Update without LDAC pin; LDAC pin tied to logic low. t8 t4 Input Data Register and DAC Latch Updated When Correction Completes(1) CS t7 t1 SCLK t2 t3 t5 BIT 23 (N) SDI t6 BIT 22 (N) BIT 0 (N) t13 LDAC BIT 0 (N+1) t12 t11 Hi-Z SDO BIT 23 (N+1) BIT 23 (N) Hi-Z BIT 0 (N) Low NOTE: (1) If the correction engine is off, the DAC latch is reloaded immediately after the DAC Data Register is updated. Case 4: Daisy-Chain Mode: Update with LDAC pin. t8 t4 CS Input Data Register Updated, but DAC Latch is Not Updated t7 t1 SCLK t2 t3 t5 BIT 23 (N) SDI t6 BIT 22 (N) BIT 0 (N) t13 BIT 0 (N+1) t12 t11 Hi-Z BIT 23 (N) SDO LDAC BIT 23 (N+1) Hi-Z BIT 0 (N) t9 High t10 DAC Latch Updated(2) NOTE: (2) The DAC latch is updated when LDAC goes low. The proper data are loaded if the t9 timing requirement is satisfied. Otherwise, invalid data are loaded. Case 5: Daisy-Chain Mode: Sleeping. CS SCLK First Word DB23 SDI Last Word DB23 DB0 DB0 t14 Hi-Z SDO DB23 DB0 = Don't Care Hi-Z DB23 DB0 Hi-Z Bit 23 = MSB Bit 0 = LSB Figure 3. SPI Timing for Daisy-Chain Mode 14 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TIMING DIAGRAMS (continued) Case 6: Readback for Standalone mode. t8 t4 t7 CS Internal Register Updated t1 SCLK t2 t3 t5 BIT 23 (= 1) SDI t6 BIT 22 BIT 0 BIT 23 (= 1) t13 Input Word Specifies Register to be Read SDO LDAC Hi-Z Hi-Z t11 BIT 23 BIT 22 BIT 1 BIT 0 NOP Command (write `1' to NOP bit) BIT 22 BIT 1 BIT 0 Hi-Z Data from the Selected Register Low = Don't Care Bit 23 = MSB Bit 0 = LSB Figure 4. SPI Timing for Readback Operation in Standalone Mode Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 15 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TIMING CHARACTERISTICS: IOVDD = +5V (1) (2) (3) (4) At -40C to +105C, DVDD = +5V, and IOVDD = +5V, unless otherwise noted. PARAMETER MIN MAX UNIT 50 MHz fSCLK Clock frequency t1 SCLK cycle time 20 ns t2 SCLK high time 10 ns t3 SCLK low time 7 ns t4 CS falling edge to SCLK falling edge setup time 8 ns t5 SDI setup time before falling edge of SCLK 5 ns t6 SDI hold time after falling edge of SCLK 5 ns t7 SCLK falling edge to CS rising edge 5 ns t8 CS high time 10 ns t9 CS rising edge to LDAC falling edge 5 ns t10 LDAC pulse duration t11 Delay from SCLK rising edge to SDO valid t12 Delay from CS rising edge to SDO Hi-Z t13 Delay from CS falling edge to SDO valid t14 SDI to SDO delay during sleep mode (1) (2) (3) (4) 10 3 2 ns 8 ns 5 ns 6 ns 5 ns Specified by design. Not production tested. Sample tested during the initial release and after any redesign or process changes that may affect these parameters. All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. SDO loaded with 10 series resistance and 10pF load capacitance for SDO timing specifications, with tR = tF 5ns. BLANKSPACE TIMING CHARACTERISTICS: IOVDD = +3V (1) (2) (3) (4) At -40C to +105C, DVDD = +3V/+5V, and IOVDD = +3V, unless otherwise noted. PARAMETER MIN MAX UNIT 25 MHz fSCLK Clock frequency t1 SCLK cycle time 40 ns t2 SCLK high time 19 ns t3 SCLK low time 7 ns t4 CS falling edge to SCLK falling edge setup time 15 ns t5 SDI setup time before falling edge of SCLK 5 ns t6 SDI hold time after falling edge of SCLK 5 ns t7 SCLK falling edge to CS rising edge 10 ns t8 CS high time 19 ns t9 CS rising edge to LDAC falling edge 5 ns t10 LDAC pulse duration t11 Delay from SCLK rising edge to SDO valid t12 t13 t14 SDI to SDO delay during sleep mode (1) (2) (3) (4) 16 10 3 ns 15 ns Delay from CS rising edge to SDO Hi-Z 7 ns Delay from CS falling edge to SDO valid 10 ns 10 ns 2 Specified by design. Not production tested. Sample tested during the initial release and after any redesign or process changes that may affect these parameters. All input signals are specified with tR = tF = 3ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. SDO loaded with 10 series resistance and 10pF load capacitance for SDO timing specifications, with tR = tF 5ns. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TIMING CHARACTERISTICS: IOVDD = +1.8V (1) (2) (3) (4) At -40C to +105C, DVDD = +3V/+5V, and IOVDD = +1.8V, unless otherwise noted. PARAMETER MIN MAX UNIT 16.6 MHz fSCLK Clock frequency t1 SCLK cycle time 60 ns t2 SCLK high time 28 ns t3 SCLK low time 7 ns t4 CS falling edge to SCLK falling edge setup time 28 ns t5 SDI setup time before falling edge of SCLK 10 ns t6 SDI hold time after falling edge of SCLK 5 ns t7 SCLK falling edge to CS rising edge 10 ns t8 CS high time 28 ns t9 CS rising edge to LDAC falling edge 5 ns t10 LDAC pulse duration t11 Delay from SCLK rising edge to SDO valid t12 Delay from CS rising edge to SDO Hi-Z t13 Delay from CS falling edge to SDO valid t14 SDI to SDO delay during sleep mode (1) (2) (3) (4) 10 3 2 ns 25 ns 15 ns 23 ns 25 ns Specified by design. Not production tested. Sample tested during the initial release and after any redesign or process changes that may affect these parameters. All input signals are specified with tR = tF = 6ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. SDO loaded with 10 series resistance and 10pF load capacitance for SDO timing specifications, with tR = tF 15ns. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 17 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) 1.0 4 All Eight Channels Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) All Eight Channels Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -1.0 -4 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 5. Figure 6. LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) 4 1.0 Typical Channel Shown Gain = 4 3 Typical Channel Shown Gain = 4 0.8 0.6 DNL Error (LSB) 2 INL Error (LSB) 8192 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 Figure 7. 18 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 8. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (-40C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (-40C) 4 1.0 Typical Channel Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) Typical Channel Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 9. Figure 10. LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) 1.0 4 Typical Channel Shown Typical Channel Shown 0.8 3 0.6 DNL Error (LSB) 2 INL Error (LSB) 8192 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -1.0 -4 0 8192 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 11. Figure 12. LINEARITY ERROR vs DIGITAL INPUT CODE (+105C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105C) 4 1.0 Typical Channel Shown Typical Channel Shown 0.8 3 0.6 DNL Error (LSB) 2 INL Error (LSB) 8192 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 Figure 13. 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 14. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 19 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 4 1.0 3 0.8 0.6 DNL Error (LSB) INL Max 2 INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 0 INL Min -1 0 -0.2 DNL Min -0.4 -0.6 -3 -0.8 -1.0 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 Figure 15. Figure 16. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 95 110 125 1.0 4 Gain = 4 0.6 DNL Error (LSB) INL Max 2 1 0 INL Min -1 Gain = 4 0.8 3 INL Error (LSB) 0.2 -2 -4 DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -1.0 -4 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 Figure 17. Figure 18. LINEARITY ERROR vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 4 1.0 AVDD = +18V AVSS = -18V 3 DNL Error (LSB) INL Max 1 0 INL Min -1 95 110 125 AVDD = +18V AVSS = -18V 0.8 0.6 2 INL Error (LSB) DNL Max 0.4 DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -4 -1.0 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 1.0 Figure 19. 20 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 Figure 20. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs AVDD AND AVSS 4 1.0 DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 3 2 0.6 INL Max 1 0 INL Min -1 DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 0.8 DNL Error (LSB) INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs AVDD AND AVSS DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -4 -1.0 6.0 7.5 9.0 10.5 12.0 13.5 AVDD = -AVSS (V) 16.5 18.0 2 1 0 -1 Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 5 15.0 16.5 18.0 DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 4 3 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 -5 Ch4 Ch5 Ch6 Ch7 -5 4.5 6.0 7.5 9.0 10.5 12.0 13.5 AVDD = -AVSS (V) 15.0 16.5 18.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 AVDD = -AVSS (V) Figure 23. Figure 24. BIPOLAR ZERO ERROR vs REFERENCE VOLTAGE BIPOLAR ZERO ERROR vs REFERENCE VOLTAGE 5 15.0 16.5 18.0 5 AVDD = +18V AVSS = -18V 4 3 2 1 0 -1 -2 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 -3 -4 AVDD = +18V AVSS = -18V Gain = 4 4 Bipolar Zero Error (mV) Bipolar Zero Error (mV) 9.0 10.5 12.0 13.5 AVDD = -AVSS (V) BIPOLAR GAIN ERROR vs AVDD AND AVSS 3 -4 7.5 BIPOLAR ZERO ERROR vs AVDD AND AVSS DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 -3 6.0 Figure 22. 4 -2 4.5 Figure 21. 5 Bipolar Zero Error (mV) 15.0 Bipolar Gain Error (mV) 4.5 3 2 1 0 -1 -2 -4 -5 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 -3 -5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 1.0 Figure 25. 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 Figure 26. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 21 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. BIPOLAR GAIN ERROR vs REFERENCE VOLTAGE BIPOLAR GAIN ERROR vs REFERENCE VOLTAGE 5 5 AVDD = +18V AVSS = -18V 3 2 1 0 -1 -2 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 -3 -4 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 -2 3.0 3.5 VREF (V) 4.0 BIPOLAR ZERO ERROR vs TEMPERATURE 4.5 5.0 5.5 5 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 -2 -3 3 2 Gain = 4 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 4 1 0 -1 -2 -3 -4 -5 -5 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) Figure 29. Figure 30. BIPOLAR GAIN ERROR vs TEMPERATURE BIPOLAR GAIN ERROR vs TEMPERATURE 5 4 4 3 3 Bipolar Gain Error (mV) 5 2 1 0 -1 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 80 95 110 125 Gain = 4 2 1 0 -1 -2 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 -3 -4 -5 -5 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 Figure 31. 22 2.5 BIPOLAR ZERO ERROR vs TEMPERATURE -1 -4 2.0 Figure 28. 0 -3 1.5 Figure 27. 1 -2 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 1.0 Bipolar Zero Error (mV) Bipolar Zero Error (mV) 0 -1 5.5 -4 Bipolar Gain Error (mV) 1 -4 5 2 2 -5 1.0 3 3 -3 -5 4 AVDD = +18V AVSS = -18V Gain = 4 4 Bipolar Gain Error (mV) Bipolar Gain Error (mV) 4 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 32. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. ANALOG POWER-SUPPLY CURRENT vs TEMPERATURE ANALOG POWER-SUPPLY CURRENT vs REFERENCE VOLTAGE 8 Analog Power-Supply Current (mA) Analog Power-Supply Current (mA) 8 7 6 IAVDD 5 4 -IAVSS 3 2 1 0 5 20 35 50 65 Temperature (C) 80 95 110 125 5 IAVDD 4 3 2 -IAVSS 1 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 Figure 33. Figure 34. ANALOG POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE DIGITAL POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 250 8 All DACs Loaded with Same Code Digital Power-Supply Current (mA) Analog Power-Supply Current (mA) 6 0 -55 -40 -25 -10 7 6 5 IAVDD 4 3 -IAVSS 2 1 5.5 One Digital Input Swept, All Others at GND or IOVDD 200 Sweep From 0V to 5.5V Sweep From 5.5V to 0V 150 100 50 0 0 0 8192 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Logic Input Voltage (V) Figure 35. Figure 36. DELTA OUTPUT VOLTAGE vs SOURCE AND SINK CURRENTS DAC OUTPUT NOISE DENSITY vs FREQUENCY 6 2000 FFFFh C000h 8000h 4000h 0000h 4 3 2 4.5 5.0 5.5 DAC Loaded with Midscale Code 1800 1600 Noise (nV/OHz) 5 DVOUT (mV) All DACs Loaded with Midscale Code AVDD = +18V AVSS = -18V 7 1 0 -1 -2 -3 1400 1200 1000 800 600 Gain = 6 400 -4 Gain = 4 200 -5 -6 0 -15 -12 -9 -6 -3 0 3 6 Current Output IOUT (mA) 9 12 15 1 Figure 37. 10 100 1k Frequency (Hz) 10k 100k Figure 38. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 23 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. SETTLING TIME -15V TO +15V TRANSITION SETTLING TIME +15V TO -15V TRANSITION Large-Signal VOUT 5V/div From Code: FFFFh To Code: 0000h Load: 10kW || 240pF 5V/div Small-Signal Error Small-Signal Error 1 LSB/div 5V/div Trigger Pulse: LDAC From Code: 0000h To Code: FFFFh Load: 10kW || 240pF 1 LSB/div Large-Signal VOUT 5V/div Trigger Pulse: LDAC Time (10ms/div) Time (10ms/div) Figure 39. Figure 40. SETTLING TIME 1/4 TO 3/4 FULL-SCALE TRANSITION SETTLING TIME 3/4 TO 1/4 FULL-SCALE TRANSITION From Code: C000h To Code: 4000h Load: 10kW || 240pF Large-Signal VOUT 5V/div Small-Signal Error Small-Signal Error 1 LSB/div Large-Signal VOUT 5V/div 5V/div Trigger Pulse: LDAC From Code: 4000h To Code: C000h Load: 10kW || 240pF 5V/div Trigger Pulse: LDAC Time (10ms/div) Time (10ms/div) Figure 41. Figure 42. GLITCH ENERGY 1 LSB STEP, RISING EDGE GLITCH ENERGY 1 LSB STEP, FALLING EDGE VOUT (1mV/div) Trigger Pulse 5V/div VOUT (1mV/div) Trigger Pulse 5V/div Glitch Impulse Glitch Impulse From Code: 8000h To Code: 7FFFh Channel 0 as Example Load: 10kW || 200pF From Code: 7FFFh To Code: 8000h Channel 0 as Example Load: 10kW || 200pF Time (2ms/div) Time (2ms/div) Figure 43. 24 1 LSB/div Figure 44. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. BIPOLAR ZERO ERROR HISTOGRAM BIPOLAR ZERO ERROR HISTOGRAM 40 60 50 30 45 Population (%) 25 20 15 10 40 35 30 25 20 15 10 5 Bipolar Zero Error (LSB) 13 15 9 11 5 7 1 3 -1 -3 -5 -7 -9 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 0 -13 5 0 -15 Population (%) Gain = 4 55 35 Bipolar Zero Error (LSB) Figure 45. Figure 46. BIPOLAR GAIN ERROR HISTOGRAM BIPOLAR GAIN ERROR HISTOGRAM 25 25 Gain = 4 20 13 15 6.0 9 11 5 7 3 1 -1 5.8 Bipolar Gain Error (LSB) -3 0 -5 0 -7 5 -11 5 -9 10 -13 10 15 -15 Population (%) 15 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 Population (%) 20 Bipolar Gain Error (LSB) Figure 47. Figure 48. NEGATIVE ANALOG POWER SUPPLY HISTOGRAM POSITIVE ANALOG POWER SUPPLY HISTOGRAM 45 30 40 25 30 Population (%) Population (%) 35 25 20 15 20 15 10 10 5 5.6 5.2 5.4 4.8 5.0 4.6 4.4 4.2 3.8 4.0 3.6 3.4 3.2 3.0 2.6 0 2.8 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 -3.2 -3.6 0 -4.0 5 AIDD (mA) AISS (mA) Figure 49. Figure 50. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 25 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25C, AVDD = 16.5V, AVSS = -16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. VOUT (5mV/div) DAC OUTPUT NOISE 0.1Hz TO 10Hz VOUT (5mV/div) DAC OUTPUT NOISE 0.1Hz TO 10Hz DAC Code = 8000h No Load Gain = 6 Channel 0 as Example Time (2ms/div) Time (2ms/div) Figure 51. 26 DAC Code = 8000h No Load Gain = 4 Channel 0 as Example Figure 52. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) 1.0 4 All Eight Channels Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) All Eight Channels Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -1.0 -4 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 53. Figure 54. LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) 4 1.0 Gain = 4 Gain = 4 0.8 3 0.6 DNL Error (LSB) 2 INL Error (LSB) 8192 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 Figure 55. 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 56. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 27 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (-40C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (-40C) 4 1.0 Typical Channel Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) Typical Channel Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 57. Figure 58. LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25C) 1.0 4 Typical Channel Shown Typical Channel Shown 0.8 3 0.6 DNL Error (LSB) 2 INL Error (LSB) 8192 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -1.0 -4 0 8192 0 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 59. Figure 60. LINEARITY ERROR vs DIGITAL INPUT CODE (+105C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105C) 4 1.0 Typical Channel Shown Typical Channel Shown 0.8 3 0.6 DNL Error (LSB) 2 INL Error (LSB) 8192 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 Figure 61. 28 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 62. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 4 1.0 3 0.8 0.6 DNL Error (LSB) INL Max 2 INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 0 -1 INL Min DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -1.0 -4 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 20 35 50 65 Temperature (C) 80 95 110 125 Figure 63. Figure 64. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 4 1.0 Gain = 4 Gain = 4 0.8 3 0.6 2 INL Max DNL Error (LSB) INL Error (LSB) 5 1 0 -1 INL Min -2 DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -0.6 -3 -0.8 -1.0 -4 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 95 110 125 Figure 65. Figure 66. LINEARITY ERROR vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 1.0 4 AVDD = +36V AVDD = +36V 0.8 3 0.6 2 INL Max DNL Error (LSB) INL Error (LSB) 80 1 0 -1 INL Min DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -1.0 -4 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 1.0 Figure 67. 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 Figure 68. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 29 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs ANALOG SUPPLY VOLTAGE DIFFERENTIAL LINEARITY ERROR vs ANALOG SUPPLY VOLTAGE 4 1.0 3 0.8 INL Max DNL Error (LSB) INL Error (LSB) DNL Max 0.6 2 1 0 INL Min -1 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -4 -1.0 9 12 15 18 21 24 AVDD (V) 27 30 33 36 9 21 24 AVDD (V) 27 30 ZERO-SCALE ERROR vs ANALOG SUPPLY VOLTAGE UNIPOLAR GAIN ERROR vs ANALOG SUPPLY VOLTAGE 5 All DACS Loaded with 0100h VREF = 2.048V Gain = 4 3 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 Ch4 Ch5 Ch6 Ch7 33 36 DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 4 Unipolar Gain Error (mV) Zero-Scale Error (mV) 18 Figure 70. 4 3 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 Ch4 Ch5 Ch6 Ch7 -5 -5 9 12 15 18 21 24 +AVDD (V) 27 30 33 36 9 12 15 18 21 24 +AVDD (V) 27 Figure 71. Figure 72. ZERO-SCALE ERROR vs REFERENCE VOLTAGE ZERO-SCALE ERROR vs REFERENCE VOLTAGE 5 30 33 36 5 All DACS Loaded with 0100h AVDD = +36V 4 3 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 Ch4 Ch5 Ch6 Ch7 All DACS Loaded with 0100h AVDD = +36V Gain = 4 4 Zero-Scale Error (mV) Zero-Scale Error (mV) 15 Figure 69. 5 3 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 -5 Ch4 Ch5 Ch6 Ch7 -5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 1.0 Figure 73. 30 12 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 Figure 74. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. UNIPOLAR GAIN ERROR vs REFERENCE VOLTAGE 5 Ch0 Ch1 Ch2 Ch3 3 2 5 AVDD = +36V Ch4 Ch5 Ch6 Ch7 1 0 -1 -2 -3 -4 2 1 0 -1 -2 -3 -5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 Figure 75. Figure 76. ZERO-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 5 4.5 5.0 5.5 5 All DACS Loaded with 0100h 4 All DACS Loaded with 0100h Gain = 4 4 3 3 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 Ch4 Ch5 Ch6 Ch7 Zero-Scale Error (mV) Zero-Scale Error (mV) 3 AVDD = +36V Gain = 4 Ch4 Ch5 Ch6 Ch7 -4 -5 2 1 0 -1 -2 Ch0 Ch1 Ch2 Ch3 -3 -4 -5 Ch4 Ch5 Ch6 Ch7 -5 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) Figure 77. Figure 78. UNIPOLAR GAIN ERROR vs TEMPERATURE UNIPOLAR GAIN ERROR vs TEMPERATURE 5 80 95 110 125 5 3 2 Ch4 Ch5 Ch6 Ch7 1 0 -1 -2 -3 -4 4 Unipolar Gain Error (mV) Ch0 Ch1 Ch2 Ch3 4 Unipolar Gain Error (mV) Ch0 Ch1 Ch2 Ch3 4 Unipolar Gain Error (mV) Unipolar Gain Error (mV) 4 UNIPOLAR GAIN ERROR vs REFERENCE VOLTAGE Gain = 4 Ch0 Ch1 Ch2 Ch3 3 2 Ch4 Ch5 Ch6 Ch7 1 0 -1 -2 -3 -4 -5 -5 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 -55 -40 -25 -10 Figure 79. 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 80. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 31 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. ANALOG POWER-SUPPLY CURRENT vs TEMPERATURE ANALOG POWER-SUPPLY CURRENT vs REFERENCE VOLTAGE 8 Analog Power-Supply Current (mA) Analog Power-Supply Current (mA) 8 7 6 5 4 3 2 1 0 All DACs Loaded with Midscale Code AVDD = +36V 7 6 5 IAVDD 4 3 2 1 0 -55 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 1.0 1.5 2.0 2.5 Figure 81. 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 Figure 82. ANALOG POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE Analog Power-Supply Current (mA) 8 All DACs Loaded with Same Code 7 6 IAVDD 5 4 3 2 1 0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 83. OUTPUT VOLTAGE vs SOURCE CURRENT CAPABILITY OUTPUT VOLTAGE vs SINK CURRENT CAPABILITY 30.5 2.5 Output Voltage VOUT (V) 30.0 29.5 Output Voltage VOUT (V) FFFFh FF00h FE00h FC00h F800h 29.0 28.5 28.0 2.0 1.5 1.0 0.5 27.5 0 3 6 9 12 15 0 -15 ISOURCE (mA) -12 -9 -6 -3 0 ISINK (mA) Figure 84. 32 0000h 0100h 0200h 0400h 0800h Figure 85. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. SETTLING TIME 0V TO 30V TRANSITION SETTLING TIME 30V TO 0V TRANSITION Large-Signal VOUT From Code: FFFFh To Code: 0100h Load: 10kW || 240pF 5V/div Small-Signal Error Small-Signal Error 1 LSB/div 5V/div Trigger Pulse: LDAC From Code: 0100h To Code: FFFFh Load: 10kW || 240pF 1 LSB/div Large-Signal VOUT 5V/div 5V/div Trigger Pulse: LDAC Time (10ms/div) Time (10ms/div) Figure 86. Figure 87. SETTLING TIME 1/4 TO 3/4 TRANSITION SETTLING TIME 3/4 TO 1/4 TRANSITION From Code: C000h To Code: 4000h Load: 10kW || 240pF Large-Signal VOUT 5V/div Small-Signal Error Small-Signal Error 1 LSB/div 1 LSB/div Large-Signal VOUT 5V/div 5V/div Trigger Pulse: LDAC From Code: 4000h To Code: C000h Load: 10kW || 240pF 5V/div Trigger Pulse: LDAC Time (10ms/div) Time (10ms/div) Figure 88. Figure 89. GLITCH ENERGY 1 LSB STEP, RISING EDGE GLITCH ENERGY 1 LSB STEP, FALLING EDGE Glitch Impulse Trigger Pulse 5V/div VOUT (1mV/div) VOUT (1mV/div) Trigger Pulse 5V/div Glitch Impulse From Code: 8000h To Code: 7FFFh Channel 0 as Example Load: 10kW || 200pF From Code: 7FFFh To Code: 8000h Channel 0 as Example Load: 10kW || 200pF Time (2ms/div) Time (2ms/div) Figure 90. Figure 91. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 33 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. ZERO-SCALE ERROR HISTOGRAM ZERO-SCALE ERROR HISTOGRAM 45 40 35 35 30 30 20 Zero-Scale Error (LSB) 13 15 9 5 7 1 0 3 0 -3 5 -1 10 5 -15 10 -7 15 -5 15 -9 20 25 -11 25 Code = 0100h Gain = 4 -13 Population (%) 40 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 Population (%) Code = 0100h 11 45 Zero-Scale Error (LSB) Figure 92. Figure 93. UNIPOLAR GAIN ERROR HISTOGRAM UNIPOLAR GAIN ERROR HISTOGRAM 25 25 Gain = 4 20 Unipolar Gain Error (LSB) 13 15 9 11 5 7 1 3 -1 -3 0 -5 0 -7 5 -9 5 -11 10 -13 10 15 -15 Population (%) 15 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 Population (%) 20 Unipolar Gain Error (LSB) Figure 94. Figure 95. ANALOG POWER-SUPPLY CURRENT HISTOGRAM 30 Population (%) 25 20 15 10 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 0 2.5 5 AIDD (mA) Figure 96. 34 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 THEORY OF OPERATION GENERAL DESCRIPTION The DAC8718 contains eight DAC channels and eight output amplifiers in a single package. Each channel consists of a resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each with a value of R, from REF-x to AGND, as shown in Figure 97. This type of architecture provides DAC monotonicity. The 16-bit binary digital code loaded to the DAC latch determines at which node on the string the voltage is tapped off before being fed into the output amplifier. The output amplifier multiplies the DAC output voltage by a gain of six or four. Using a gain of 6 and power supplies allowing for at least 0.5V headroom, the output span is 9V with a 1.5V reference, 18V with a 3V reference, and 30V with a 5V reference. REF-x R R R To Output Amplifier R R Figure 97. Resistor String CHANNEL GROUPS The eight DAC channels and two Offset DACs are arranged into two groups (A and B) with four channels and one Offset DAC per group. Group A consists of DAC-0, DAC-1, DAC-2, DAC-3, and Offset DAC-A. Group B consists of DAC-4, DAC-5, DAC-6, DAC-7, and Offset DAC-B. Group A derives its reference voltage from REF-A, and Group B derives its reference voltage from REF-B. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 35 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com USER-CALIBRATION FOR ZERO-CODE ERROR AND GAIN ERROR The DAC8718 implements a digital user-calibration function that allows for trimming gain and zero errors on the entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has a Zero Register and Gain Register. Using the correction engine, the data from the Input Data Register are operated on by a digital adder and multiplier controlled by the contents of the Zero and Gain registers, respectively. The calibrated DAC data are then stored in the DAC Data Register where they are finally transferred into the DAC latch and set the DAC output. Each time the data are written to the Input Data Register (or to the Gain or Zero registers), the data in the Input Data Register are corrected, and the results automatically transferred to the DAC Data Register. The range of the gain adjustment coefficient is 0.5 to 1.5. The range of the zero adjustment is -32768 LSB to +32767 LSB, or 50% of full scale. There is only one correction engine in the DAC8718, which is shared among all channels. If the user-calibration function is not needed, the correction engine can be turned off. Setting the SCE bit in the Configuration Register to '0' turns off the correction engine. Setting SCE to '1' enables the correction engine. When SCE = '0', the data are directly transferred to the DAC Data Register. In this case, writing to the Gain Register or Zero Register updates the Gain and Zero registers but does not start a math engine calculation. Reading these registers returns the written values. 36 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 ANALOG OUTPUTS (VOUT-0 to VOUT-7, with reference to the ground of REF-x) When the correction engine is off (SCE = '0'): VOUT = VREF Gain INPUT_CODE OFFSETDAC_CODE - VREF (Gain - 1) 65536 65536 (1) SPACE When the correction engine is on (SCE = '1'): VOUT = VREF Gain DAC_DATA_CODE OFFSETDAC_CODE - VREF (Gain - 1) 65536 65536 (2) SPACE Where: DAC_DATA_CODE = INPUT_CODE (USER_GAIN + 215) 216 + USER_ZERO Gain = the DAC gain defined by the GAIN bit in the Configuration Register. INPUT_CODE = data written into the Input Data Register (SCE = '1') or the DAC Data Register (SCE = '0'). OFFSETDAC_CODE = the data written into the Offset DAC Register. USER_GAIN = the code of the Gain Register. USER_ZERO = the code of the Zero Register. For single-supply operation, the OFFSET-A pin must be connected to the AGND-A pin and the OFFSET-B pin must be connected to the AGND-B pin through low-impedance connections (see the Layout section for details). Offset DAC-A and Offset DAC-B are in a power-down state. For dual-supply operation, the OFFSET-A and OFFSET-B default codes for a gain of 6 are 39322 with a 10 LSB variation, depending on the linearity of the Offset DACs. The default code for a gain of 4 is 43691 with a 10 LSB variation. The default codes of OFFSET-A and OFFSET-B are independently factory trimmed for both gains of 6 and 4. The power-on default value of the Gain Register is 32768, and the default value of the Zero Register is '0'. The DAC input registers are set to a default value of 0000h. Note that the maximum output voltage must not be greater than (AVDD - 0.5V) and the minimum output voltage must not be less than (AVSS + 0.5V); otherwise, the output may be saturated. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 37 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com INPUT DATA FORMAT The USB/BTC pin defines the input data format and the Offset DAC format. When this pin is connected to DGND, the Input DAC data and Offset DAC data are straight binary, as shown in Table 1 and Table 3. When this pin is connected to IOVDD, the Input DAC data and Offset DAC data are in twos complement format, as shown in Table 2 and Table 4. Table 1. Bipolar Output vs Straight Binary Code Using Dual Power Supplies with Gain = 6 USB CODE NOMINAL OUTPUT DESCRIPTION FFFFh +3 x VREF x (32767/32768) +Full-Scale - 1 LSB *** *** *** *** *** *** 8001h +3 x VREF x (1/32768) +1 LSB 8000h 0 Zero 7FFFh -3 x VREF x (1/32768) -1 LSB *** *** *** *** *** *** 0000h -3 x VREF x (32768/32768) -Full-Scale Table 2. Bipolar Output vs Twos Complement Code Using Dual Power Supplies with Gain = 6 BTC CODE NOMINAL OUTPUT DESCRIPTION 7FFFh +3 x VREF x (32767/32768) +Full-Scale - 1 LSB *** *** *** *** *** *** 0001h +3 x VREF x (1/32768) +1 LSB 0000h 0 Zero FFFFh -3 x VREF x (1/32768) -1 LSB *** *** *** *** *** *** 8000h -3 x VREF x (32768/32768) -Full-Scale Table 3. Unipolar Output vs Straight Binary Code Using Single Power Supply with Gain = 6 USB CODE NOMINAL OUTPUT DESCRIPTION FFFFh +6 x VREF x (65535/65536) +Full-Scale - 1 LSB *** *** *** *** *** *** 8001h +6 x VREF x (32769/65536) Midscale + 1 LSB 8000h +6 x VREF x (32768/65536) Midscale 7FFFh +6 x VREF x (32767/65536) Midscale - 1 LSB *** *** *** *** *** *** 0000h 0 0 Table 4. Unipolar Output vs Twos Complement Code Using Single Power Supply with Gain = 6 BTC CODE NOMINAL OUTPUT DESCRIPTION 7FFFh +6 x VREF x (65535/65536) +Full-Scale - 1 LSB *** *** *** *** *** *** 0001h +6 x VREF x (32769/65536) Midscale + 1 LSB 0000h +6 x VREF x (32768/65536) Midscale FFFFh +6 x VREF x (32767/65536) Midscale - 1 LSB *** *** *** *** *** *** 8000h 0 0 The data written to the Gain Register are always in straight binary, data to the Zero Register are in twos complement, and data to all other control registers are as specified in the definitions, regardless of the USB/BTC pin status. In reading operation, the read-back data are in the same format as written. 38 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 OFFSET DACS There are two 16-bit Offset DACs: one for Group A, and one for Group B. The Offset DACs allow the entire output curve of the associated DAC groups to be shifted by introducing a programmable offset. This offset allows for asymmetric bipolar operation of the DACs or unipolar operation with bipolar supplies. Thus, subject to the limitations of headroom, it is possible to set the output range of Group A and/or Group B to be unipolar positive, unipolar negative, symmetrical bipolar, or asymmetrical bipolar, as shown in Table 5 and Table 6. Increasing the digital input codes for the offset DAC shifts the outputs of the associated channels in the negative direction. The default codes for the Offset DACs in the DAC8718 are factory trimmed to provide optimal offset and gain performance for the default output range and span of symmetric bipolar operation. When the output range is adjusted by changing the value of the Offset DAC, an extra offset is introduced as a result of the linearity and offset errors of the Offset DAC. Therefore, the actual shift in the output span may vary slightly from the ideal calculations. For optimal offset and gain performance in the default symmetric bipolar operation, the Offset DAC input codes should not be changed from the default power-on values. The maximum allowable offset depends on the reference and the power supply. If INPUT_CODE from Equation 1 or DAC_DATA_CODE from Equation 2 is set to 0, then these equations simplify to Equation 3: VOUT = -VREF (Gain - 1) OFFSETDAC_CODE 65536 (3) This equation shows the transfer function of the Offset DAC to the output of the DAC channels. In any case, the analog output must not go beyond the specified range shown in the Analog Outputs section. After power-on or reset, the Offset DAC is set to the value defined by the selected data format and the selected analog output voltage. If the DAC gain setting is changed, the offset DAC code is reset to the default value corresponding to the new DAC gain setting. Refer to the Power-On Reset and Hardware Reset sections for details. For single-supply operation (AVSS = 0V), the Offset DAC is turned off, and the output amplifier is in a Hi-Z state. The OFFSET-x pin must be connected to the AGND-x pin through a low-impedance connection (see the Layout section for details). For dual-supply operation, this pin provides the output of the Offset DAC. The OFFSET-x pin is not intended to drive an external load. See Figure 98 for the internal Offset DAC and output amplifier configuration. Table 5. Example of Offset DAC Codes and Output Ranges with Gain = 6 and VREF = 5V (1) (2) OFFSET DAC CODE OFFSET DAC VOLTAGE DAC CHANNELS MFS (1) VOLTAGE DAC CHANNELS PFS (1) VOLTAGE 999Ah (2) 3.0V -15V +15V - 1 LSB +30V - 1 LSB 0000h 0V 0V FFFFh ~5.0V -25V +5V - 1 LSB 6666h ~2.0V -10V +20V - 1 LSB CCCDh ~4.0V -20V +10V - 1 LSB MFS = minus full-scale; PFS = plus full-scale. This is the default code for symmetric bipolar operation; actual codes may vary 10 LSB. Codes are in straight binary format. Table 6. Example of Offset DAC Codes and Output Ranges with Gain = 4 and VREF = 5V (1) (2) OFFSET DAC CODE OFFSET DAC VOLTAGE DAC CHANNELS MFS (1) VOLTAGE DAC CHANNELS PFS (1) VOLTAGE AAABh (2) ~3.33333V -10V +10V - 1 LSB 0000h 0V 0V +20V - 1 LSB FFFFh ~5.0V -15V +5V - 1 LSB 5555h ~1.666V -5V +15V - 1 LSB 8000h 2.5V -7.5V +12.5V - 1 LSB D555h ~4.1666V -12.5V +7.5V - 1 LSB MFS = minus full-scale; PFS = plus full-scale. This is the default code for symmetric bipolar operation; actual codes may vary 10 LSB. Codes are in straight binary format. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 39 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com VOUT = GAIN x V1 - (GAIN - 1) x VOFF DAC Channel V1 VOUT AGND-x Offset DAC VOFF OFFSET Figure 98. Output Amplifier and Offset DAC OUTPUT AMPLIFIERS The output amplifiers can swing to 0.5V below the positive supply and 0.5V above the negative supply. This condition limits how much the output can be offset for a given reference voltage. The maximum range of the output for 17V power and a +5.5V reference is -16.5V to +16.5V for gain = 6. Each output amplifier is implemented with individual over-current protection. The amplifier is clamped at 8mA, even if the output current goes over 8mA. 40 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0 to GPIO-2) The GPIO pins are general-purpose, bidirectional, digital input/outputs, as shown in Figure 99. When a GPIO pin acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'. Note that a pull-up resistor to IOVDD is required when using a GPIO pin as an output. When a GPIO pin acts as an input, the digital value on the pin is acquired by reading the corresponding GPIO bit. After power-on reset, or any forced hardware or software reset, the GPIO bits are set to '1', and the GPIO pins are in a high-impedance state. If not used, the GPIO pins must be tied to either DGND or to IOVDD through a pull-up resistor. Leaving the GPIO pins floating can cause high IOVDD supply currents. +V GPIO-n Enable Bit GPIO-n (when writing) Bit GPIO-n (when reading) Figure 99. GPIO-n Pin ANALOG OUTPUT PIN (CLR) The CLR pin is an active low input that should be high for normal operation. When this pin is in logic '0', all VOUT outputs connect to AGND-x through internal 15k resistors and are cleared to 0V, and the output buffer is in a Hi-Z state. While CLR is low, all LDAC pulses are ignored. When CLR is taken high again while the LDAC is high, the DAC outputs remain cleared until LDAC is taken low. However, if LDAC is tied low, taking CLR back to high sets the DAC output to the level defined by the value of the DAC latch. The contents of the Zero Registers, Gain Registers, Input Data Registers, DAC Data Registers, and DAC latches are not affected by taking CLR low. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 41 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com POWER-ON RESET The DAC8718 contains a power-on reset circuit that controls the output during power-on and power down. This feature is useful in applications where the known state of the DAC output during power-on is important. The Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL pin, as shown in Table 7. The Gain Registers and Zero Registers are loaded with default values. The Input Data Register is reset to 0000h, independent of the RSTSEL state. Table 7. Bipolar Output Reset Values for Dual Power-Supply Operation (1) RSTSEL PIN USB/BTC PIN INPUT FORMAT VALUE OF DAC DATA REGISTER AND DAC LATCH VALUE OF OFFSET DAC REGISTER FOR GAIN = 6 (1) DGND DGND Straight Binary 0000h 999Ah -Full-Scale VOUT IOVDD DGND Straight Binary 8000h 999Ah 0V DGND IOVDD Twos Complement 8000h 199Ah -Full-Scale IOVDD IOVDD Twos Complement 0000h 199Ah 0V Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary no more than 10 LSB from the nominal number listed in this table. In single-supply operation, the Offset DAC is turned off and the output is unipolar. The power-on reset is defined as shown in Table 8. Table 8. Unipolar Output Reset Values for Single Power-Supply Operation RSTSEL PIN USB/BTC PIN INPUT FORMAT VALUE OF DAC DATA REGISTER AND DAC LATCH DGND DGND Straight Binary 0000h 0V IOVDD DGND Straight Binary 8000h Midscale DGND IOVDD Twos Complement 8000h 0V IOVDD IOVDD Twos Complement 0000h Midscale VOUT HARDWARE RESET When the RST pin is low, the device is in hardware reset. All the analog outputs (VOUT-0 to VOUT-7), the DAC registers, and the DAC latches are set to the reset values defined by the RSTSEL pin as shown in Table 7 and Table 8. In addition, the Gain and Zero Registers are loaded with default values, communication is disabled, and the signals on CS and SDI are ignored (note that SDO is in a high-impedance state). The Input Data Register is reset to 0000h, independent of the RSTSEL state. On the rising edge of RST, the analog outputs (VOUT-0 to VOUT-7) maintain the reset value as defined by the RSTSEL pin until a new value is programmed. After RST goes high, the serial interface returns to normal operation. CS must be set to a logic high whenever RST is used. 42 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 UPDATING THE DAC OUTPUTS Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low before power is applied to the device. If synchronous mode is desired, LDAC must be logic high before and during power-on. The DAC8718 updates a DAC latch only if it has been accessed since the last time LDAC was brought low or if the LD bit is set to '1', thereby eliminating any unnecessary glitch. Any DAC channels that were not accessed are not loaded again. When the DAC latch is updated, the corresponding output changes to the new level immediately. Asynchronous Mode In this mode, the LDAC pin is set low at power-up. This action places the DAC8718 into Asynchronous mode, and the LD bit and LDAC signal are ignored. When the correction engine is off (SCE bit = '0'), the DAC Data Registers and DAC latches are updated immediately when CS goes high. When the correction engine is on (SCE bit = '1'), each DAC latch is updated individually when the correction engine updates the corresponding DAC Data Register. Synchronous Mode To use this mode, set LDAC high before CS goes low, and then take LDAC low or set the LD bit to '1' after CS goes high. If LDAC goes low or if the LD bit is set to '1' when SCE = '0', all DAC latches are updated simultaneously. If LDAC goes low or if the LD bit is set to '1' when SCE = '1', all DAC latches are updated simultaneously after the correction engine has updated the corresponding DAC register. In this mode, when LDAC stays high, the DAC latch is not updated; therefore, the DAC output does not change. The DAC latch is updated by taking LDAC low (or by setting the LD bit in the Configuration Register to '1') any time after the delay of t9 from the rising edge of CS. If the timing requirement of t9 is not satisfied, invalid data are loaded. Refer to the Timing Diagrams and the Configuration Register (Table 11) for details. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 43 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com MONITOR OUTPUT PIN (VMON) The VMON pin is the channel monitor output. It can be either high-impedance or monitor any one of the DAC outputs, auxiliary analog inputs, offset DAC outputs, or reference buffer outputs. The channel monitor function consists of an analog multiplexer addressed via the serial interface, allowing any channel output, reference buffer output, auxiliary analog inputs, or offset DAC output to be routed to the VMON pin for monitoring using an external ADC. The monitor function is controlled by the Monitor Register, which allows the monitor output to be enabled or disabled. When disabled, the monitor output is high-impedance; therefore, several monitor outputs may be connected in parallel with only one enabled at a time. Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the maximum current from the VMON pin must not be greater than the given specification because this could conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from VOUT-X) to the output of the multiplexer (VMON). Refer to the Monitor Register section and Table 12 for more details. ANALOG INPUT PINS (AIN-0 and AIN-1) Pins AIN-0 and AIN-1 are two analog inputs that directly connect to the analog mux of the analog monitor output. When AIN-0 or AIN-1 is accessed, it is routed via the mux to the VMON pin. Thus, one external ADC channel can monitor eight DACs plus two extra external analog signals, AIN-0 and AIN-1. POWER-DOWN MODE The DAC8718 is implemented with a power-down function to reduce power consumption. Either the entire device or each individual group can be put into power-down mode. If the proper power-down bit (PD-x) in the Configuration Register is set to '1', the individual group is put into power down mode. During power-down mode, the analog outputs (VOUT-0 to VOUT-7) connect to AGND-X through an internal 15k resistor, and the output buffer is in Hi-Z status. When the entire device is in power-down, the bus interface remains active in order to continue communication and receive commands from the host controller, but all other circuits are powered down. The host controller can wake the device from power-down mode and return to normal operation by clearing the PD-x bit; it takes 200s or less for recovery to complete. POWER-ON RESET SEQUENCING The DAC8718 permanently latches the status of some of the digital pins at power-on. These digital levels should be well-defined before or while the digital supply voltages are applied. Therefore, it is advised to have a pull up resistor to IOVDD for the digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL) to ensure that these levels are set correctly while the digital supplies are raised. For proper power-on initialization of the device, IOVDD and the digital pins must be applied before or at the same time as DVDD. If possible, it is preferred that IOVDD and DVDD can be connected together in order to simplify the supply sequencing requirements. Pull-up resistors should go to either supply. AVDD should be applied after the digital supplies (IOVDD and DVDD) and digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL). AVSS can be applied at the same time as or after AVDD. The REF-x pins must be applied last. 44 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 SERIAL INTERFACE The DAC8718 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to 50MHz and is compatible with SPI, QSPITM, MicrowireTM, and DSPTM standards. SPI Shift Register The SPI Shift Register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK. The SPI Shift Register consists of a read/write bit, five register address bits, 16 data bits, and two reserve bits for future devices, as shown in Table 9. The falling edge of CS starts the communication cycle. The data are latched into the SPI Shift Register on the falling edge of SCLK while CS is low. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a high-impedance state. The contents of the SPI shifter register are decoded and transferred to the proper internal registers on the rising edge of CS. The timing for this operation is shown in the Timing Diagrams section. The serial interface works with both a continuous and non-continuous serial clock. A continuous SCLK source can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and CS must be taken high after the final clock in order to latch the data. The serial interface requires CS to be logic high during the power-on sequencing; therefore, it is advised to have a pullup resistor to IOVDD on the CS pin. Refer to the Power-On Reset Sequencing section for further details. Stand-Alone Operation The serial clock can be a continuous or a gated clock. The first falling edge of CS starts the operation cycle. Exactly 24 falling clock edges must be applied before CS is brought back high again. If CS is brought high before the 24th falling SCLK edge, then the data written are not transferred into the internal registers. If more than 24 falling SCLK edges are applied before CS is brought high, then the last 24 bits are used. The device internal registers are updated from the Shift Register on the rising edge of CS. In order for another serial transfer to take place, CS must be brought low again. When the data have been transferred into the chosen register of the addressed DAC, all DAC latches and analog outputs can be updated by taking LDAC low. Daisy-Chain Operation For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices together. Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial interface lines. Note that before daisy-chain operation can begin, the SDO pin must be enabled by setting the SDO disable bit (DSDO) in the Configuration Register to '0'; this bit is cleared by default. The DAC8718 provides two modes for daisy-chain operation: normal and sleep. The SLEEP bit in the SPI Mode register determines which mode is used. In Normal mode (SLEEP bit = '0'), the data clocked into the SDI pin are transferred into the Shift Register. The first falling edge of CS starts the operating cycle. SCLK is continuously applied to the SPI Shift Register when CS is low. If more than 24 clock pulses are applied, the data ripple out of the Shift Register and appear on the SDO line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 x N, where N is the total number of DAC8718s in the chain. When the serial transfer to all devices is complete, CS is taken high. This action latches the data from the SPI Shift Registers to the device internal registers for each device in the daisy-chain, and prevents any further data from being clocked in. The serial clock can be a continuous or a gated clock. Note that a continuous SCLK source can only be used if CS is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock cycles must be used and CS must be taken high after the final clock in order to latch the data. In Sleep mode (SLEEP bit = '1'), the data clocked into SDI are routed to the SDO pin directly; the Shift Register is bypassed. The first falling edge of CS starts the operating cycle. When SCLK is continuously applied with CS low, the data clocked into the SDI pin appear on the SDO pin almost immediately (with approximately a 5 ns delay; see the Timing Diagrams section); there is no 24 clock delay, as there is in normal operting mode. While in Sleep mode, no data bits are clocked into the Shift Register, and the device does not receive any new data or commands. Putting the device into Sleep mode eliminates the 24 clock delay from SDI to SDO caused by the Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 45 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com Shift Register, thus greatly speeding up the data transfer. For example, consider three DAC8718s (A, B, and C) in a daisy-chain configuration. The data from the SPI controller are transferred first to A, then to B, and finally to C. In normal daisy-chain operation, a total of 72 clocks are needed to transfer one word to C. However, if A and B are placed into Sleep mode, the first 24 data bits are directly transferred to C (through A and B); therefore, only 24 clocks are needed. To wake the device up from sleep mode and return to normal operation, either one of following methods can be used: 1. Pull the WAKEUP pin low, which forces the SLEEP bit to '0' and returns the device to normal operating mode. 2. Use the W2 bit and the CS pin. When the W2 bit = '1', if CS is applied with no more than one falling edge of SCLK, then the rising edge of CS wakes the device from sleep mode back to normal operation. However, the device will not wake-up if more than one falling edge of SCLK exists while CS is low. Read-Back Operation The READ command is used to start read-back operation. However, before read-back operation can be initiated, the SDO pin must be enabled by setting the DSDO bit in the Configuration Register to '0'; this bit is cleared by default. Read-back operation is then started by executing a READ command (R/W bit = '1', see Table 9). Bits A4 to A0 in the READ command select the register to be read. The remaining data in the command are don't care bits. During the next SPI operation, the data appearing on the SDO output are from the previously addressed register. For a read of a single register, a NOP command can be used to clock out the data from the selected register on SDO. Multiple registers can be read if multiple READ commands are issued. The readback diagram in Figure 100 shows the read-back sequence. Single Reading CS SCLK R/W = `1' R/W = `0' DB0 DB23 SDI DB0 DB23 READ Command Specifies Register to be Read NOP Command (write `1' to NOP bit) DB0 DB23 SDO DB0 DB23 Undefined Data from Selected Register Multiple Readings CS SCLK R/W = `1' SDI R/W = `1' DB23 DB0 Command to Read Register A SDO DB23 DB0 R/W = `1' DB23 DB0 Command to Read Register B DB23 Undefined R/W = `0' DB23 DB0 DB23 Command to Read Register C DB0 DB23 Data from Register A DB0 DB23 NOP Command (write `1' to NOP bit) DB23 Data from Register B = Don't Care DB0 Command DB0 Data from Register C DB0 DB23 DB0 Undefined Bit 23 = MSB Bit 0 = LSB Figure 100. Read-Back Operation 46 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 SPI SHIFT REGISTER The SPI Shift Register is 24 bits wide, as shown in Table 9. The register mapping is shown in Table 10; X = don't care--writing to it has no effect, reading it returns '0'. Table 9. Shift Register Format MSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15:DB0 R/W X X A4 A3 A2 A1 A0 DATA R/W Indicates a read from or a write to the addressed register. R/W = '0' sets a write operation and the data are written to the specified register. R/W = '1' sets a read-back operation. Bits A4 to A0 select the register to be read. The remaining bits are don't care bits. During the next SPI operation, the data appearing on SDO pin are from the previously addressed register. A4:A0 Address bits that specify which register is accessed. DATA 16 data bits Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 47 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com Table 10. Register Map ADDRESS BITS DATA BITS A4 A3 A2 A1 A0 D15 D14 D13 GPIO-2 GPIO-1 GPIO-0 PD-A PD-B SCE D9 X D8 D7 GAIN-A GAIN-B D6 DSDO D5 REGISTER X (1) Configuration Register X (1) Monitor Register 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 OS15:OS0 (2) Offset DAC-A Data 0 0 1 0 0 OS15:OS0 (2) Offset DAC-B Data 0 0 1 0 1 Reserved (3) 0 0 1 1 0 0 0 1 1 1 DB15:DB0 Broadcast 0 1 0 0 0 DB15:DB0 DAC-0 0 1 0 0 1 DB15:DB0 DAC-1 0 1 0 1 0 DB15:DB0 DAC-2 0 1 0 1 1 DB15:DB0 DAC-3 0 1 1 0 0 DB15:DB0 DAC-4 0 1 1 0 1 DB15:DB0 DAC-5 0 1 1 1 0 DB15:DB0 DAC-6 0 1 1 1 1 DB15:DB0 DAC-7 1 0 0 0 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-0 1 1 0 0 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-0 1 0 0 0 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-1 1 1 0 0 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-1 1 0 0 1 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-2 1 1 0 1 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-2 1 0 0 1 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-3 1 1 0 1 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-3 1 0 1 0 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-4 1 1 1 0 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-4 1 0 1 0 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-5 1 1 1 0 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-5 1 0 1 1 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-6 1 1 1 1 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-6 1 0 1 1 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-7 1 1 1 1 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-7 SLEEP X (1) Reserved (3) W2 D3:D0 0 Analog Monitor Select NOP D4 0 48 RST D10 0 (3) LD D11 0 (1) (2) A/B D12 GPIO Register Reserved SPI MODE X = don't care--writing to this bit has no effect; reading the bit returns '0'. Table 7 lists the default values for a dual power supply. Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary no more than 10 LSB from the nominal number listed in Table 7. For a single power supply, the Offset DACs are turned off. Writing to a reserved bit has no effect; reading the bit returns '0'. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 INTERNAL REGISTERS The DAC8718 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data Registers, the Zero Registers, the DAC Data Registers, and the Gain Registers, and are described in the following section. The Configuration Register specifies which actions are performed by the device. Table 11 shows the details. Table 11. Configuration Register (Default = 8000h) BIT D15 NAME A/B DEFAULT VALUE DESCRIPTION 1 A/B bit. When A/B = '0', reading DAC-x returns the value in the Input Data Register. When A/B = '1', reading DAC-x returns the value in the DAC Data Register. When the correction engine is enabled, the data returned from the Input Data Register is the original data written to the bus, and the value in the DAC Data Register is the corrected data. D14 LD 0 Synchronously update DACs bit. When LDAC is tied high, setting LD = '1' at any time after the write operation and the correction process complete synchronously updates all DAC latches with the content of the corresponding DAC Data Register, and sets VOUT to a new level. The DAC8718 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After updating, the bit returns to '0'. When the correction engine is turned off, bit LD can be set to '1' any time after the writing operation is complete; the DAC latch is immediately updated when bit LD is set. When the LDAC pin is tied low, this bit is ignored. D13 RST 0 Software reset bit. Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit returns to '0'. 0 Power-down bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3). Setting the PD-A bit to '1' places Group A (DAC-0, DAC-1, DAC-2, and DAC-3) into power-down operation. All output buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-A through an internal 15-k resistor. The interface is still active. Setting the PD-A bit to '0' returns group A to normal operation. 0 Power-down bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7). Setting the PD-B bit to '1' places Group B (DAC-4, DAC-5, DAC-6, and DAC-7) into power-down operation. All output buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-B through an internal 15-k resistor. The interface is still active. Setting the PD-B bit to '0' returns group B to normal operation. D12 D11 PD-A PD-B D10 SCE 0 System-calibration enable bit. Set the SCE bit to '1' to enable the correction engine. When the engine is enabled, the input data are adjusted by the correction engine according to the contents of the corresponding Gain Register and Zero Register. The results are transferred to the corresponding DAC Data Register, and finally loaded into the DAC latch, which sets the VOUT-x pin output level. Set the SCE bit to '0' to turn off the correction engine. When the engine is turned off, the input data are transferred to the corresponding DAC Data Register immediately, and then loaded into the DAC latch, which sets the output voltage. Refer to the User Calibration for Zero-Code Error and Gain Error section for details. D9 -- 0 Reserved. Writing to this bit has no effect; reading this bit returns '0'. D8 GAIN-A 0 Gain bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3). Updating this bit to a new value automatically resets the Offset DAC-A Register to the factory-trimmed value for the new gain setting. Set the GAIN-A bit to '0' for an output span = 6 x REF-A. Set the GAIN-A bit to '1' for an output span = 4 x REF-A. D7 GAIN-B 0 Gain bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7). Updating this bit to a new value automatically resets the Offset DAC-B Register to the factory-trimmed value for the new gain setting. Set the GAIN-B bit to '0' for an output span = 6 x REF-B. Set the GAIN-B bit to '1' for an output span = 4 x REF-B. D6 DSDO 0 Disable SDO bit. Set the DSDO bit to '0' to enable the SDO pin (default). The SDO pin works as a normal SPI output. Set the DSDO bit to '1' to disable the SDO pin. The SDO pin is always in a Hi-Z state no matter what the status of the CS pin is. D5 NOP 0 No operation bit. During a write operation, setting the NOP bit to '1' has no effect (the bit returns to '0' when the write operation completes). Setting the NOP bit to '0', returns the device to normal operation. During a read operation, the bit always returns "0" D4 W2 0 Second wake-up operation bit. If the WAKEUP pin is high, an alternative method to wake-up the device from sleep in SPI is by using the CS pin. When W2 = '1', the rising edge of CS restores the device from sleep mode to normal operation, if no more than one falling edge of SCLK exists while CS is low. However, the device will not wake up if more than one falling edge of SCLK exists. Setting the W2 bit to '0' disables this function, and the rising edge of CS does not wake up the device. If the WAKEUP is low, this bit is ignored and the device is always in normal mode. D3:D0 -- 0 Reserved. Writing to these bits has no effect; reading these bits returns '0'. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 49 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com Monitor Register (default = 0000h). The Monitor Register selects one of the DAC outputs, auxiliary analog inputs, reference buffer outputs, or offset DAC outputs to be monitored through the VMON pin. When bits [D15:D4] = '0', the monitor is disabled and VMON is in a Hi-Z state. Note that if any value is written other than those specified in Table 12, the Monitor Register stores the invalid value; however, the VMON pin is forced into a Hi-Z state. Table 12. Monitor Register (Default = 0000h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3:D0 VMON CONNECTS TO 0 0 0 0 0 0 0 0 0 0 0 1 X (1) Reference buffer B output 0 0 0 0 0 0 0 0 0 0 1 0 X Reference buffer A output 0 0 0 0 0 0 0 0 0 1 0 1 X Offset DAC B output 0 0 0 0 0 0 0 0 0 1 1 0 X Offset DAC A output 0 0 0 0 0 0 0 0 0 1 0 0 X AIN-0 0 0 0 0 0 0 0 0 1 0 0 0 X AIN-1 0 0 0 0 0 0 0 1 0 0 0 0 X DAC-0 0 0 0 0 0 0 1 0 0 0 0 0 X DAC-1 0 0 0 0 0 1 0 0 0 0 0 0 X DAC-2 0 0 0 0 1 0 0 0 0 0 0 0 X DAC-4 0 0 0 1 0 0 0 0 0 0 0 0 X DAC-4 0 0 1 0 0 0 0 0 0 0 0 0 X DAC-5 0 1 0 0 0 0 0 0 0 0 0 0 X DAC-6 1 0 0 0 0 0 0 0 0 0 0 0 X DAC-7 0 0 0 0 0 0 0 0 0 0 0 0 X Monitor function disabled, Hi-Z (default) (1) X = don't care. BLANKSPACE GPIO Register (default = E000h). The GPIO Register determines the status of each GPIO pin. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GPIO-2 GPIO-1 GPIO-0 X X X X X X X X X X X X X GPIO-2:0 For write operations, the GPIO-n pin operates as an output. Writing a '1' to the GPIO-n bit sets the GPIO-n pin to high impedance, and writing a '0' sets the GPIO-n pin to logic low. An external pull-up resistor is required when using the GPIO-n pin as an output. For read operations, the GPIO-n pin operates as an input. Read the GPIO-n bit to receive the status of the corresponding GPIO-n pin. Reading a '0' indicates that the GPIO-n pin is low, and reading a '1' indicates that the GPIO-n pin is high. After power-on reset, or any forced hardware or software reset, all GPIO-n bits are set to '1', and the GPIO pins are in a high impedance state. 50 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 Offset DAC-A/B Registers (default = 999Ah for dual supplies or 0000h for single supplies). The Offset DAC-A and Offset DAC-B registers contain, by default, the factory-trimmed Offset DAC code providing optimal offset and span for symmetric bipolar operation when dual supplies are detected, and contain code 0000h when a single supply is detected. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 OS15:0 For dual-supply operation, the default code for a gain of 6 is 999Ah with a 10 LSB variation, depending on the linearity of each Offset DAC. The default code for a gain of 4 is AAABh with a 10 LSB variation. The default codes of Offset DAC-A and Offset DAC-B registers are independently factory trimmed for both gains of 6 and 4. When single-supply operation is present, writing to these registers is ignored and reading returns 0000h. When dual-supply operation is present, updating the GAIN-A (GAIN-B) bit on the configuration register automatically reloads the factory-trimmed code into the Offset DAC-A (Offset DAC-B) register for the new GAIN-A (GAIN-B) setting. See the Offset DACs for further details. BLANKSPACE SPI MODE Register (default = 0000h). The SPI Mode Register is used to put the device into SPI sleep mode. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SLEEP X X X X X X X X X X X X X X X SLEEP Set the SLEEP bit to '1' to put the device into SPI sleep mode. When the SLEEP bit = '0', the SPI is in normal mode. The bit is cleared ('0') after a hardware reset (through the RST pin) or if the WAKEUP pin is low. For normal SPI operation, the data entering the SDI pin is transferred into the Shift Register. However, for SPI sleep mode, the Shift Register is bypassed. The data entering into the SDI pin are directly transferred to the SDO pin instead of the Shift Register. BLANKSPACE Broadcast Register. The DAC8718 broadcast register can be used to update all eight DAC register channels simultaneously using data bits D15:D0. This write-only register uses address A4:A0 = 07h, and is only available when the SCE bit = '0' (default). If the SCE bit = '1', this register is ignored. Reading this register always returns 0000h. BLANKSPACE Input Data Register for DAC-n, where n = 0 to 7 (default = 0000h). This register stores the DAC data written to the device when the SCE bit = '1' and is controlled by the correction engine. When the SCE bit = '0' (default), the DAC Data Register stores the DAC data written to the device. When the data are loaded into the corresponding DAC latch, the DAC output changes to the new level defined by the DAC latch. The default value after power-on or reset is 0000h. Table 13. DAC-n (1) Input Data Register MSB D15 DB15 (1) (2) (2) LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 n = 0, 1, 2, 3, 4, 5, 6, or 7. DB15:DB0 are the DAC data bits. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 51 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com Zero Register n, where n = 0 to 7 (default = 0000h). The Zero Register stores the user-calibration data that are used to eliminate the offset error. The data are 16 bits wide, 1 LSB/step, and the total adjustment is -32768 LSB to +32767 LSB, or 50% of full-scale range. The Zero Register uses a twos complement data format. Table 14. Zero Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Z15:Z0--OFFSET BITS ZERO ADJUSTMENT 7FFFh +32767 LSB 7FFEh +32766 LSB *** *** *** *** *** *** 0001h +1 LSB 0000h 0 LSB (default) FFFFh -1 LSB *** *** *** *** *** *** 8001h -32767 LSB 8000h -32768 LSB BLANKSPACE Gain Register n, where n = 0 to 7 (default = 8000h). The Gain Register stores the user-calibration data that are used to eliminate the gain error. The data are 16 bits wide, 0.0015% FSR/step, and the total adjustment range 0.5 to 1.5. The Gain Register uses a straight binary data format. Table 15. Gain Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 52 G15:G0--GAIN-CODE BITS GAIN ADJUSTMENT COEFFICIENT FFFFh 1.499985 FFFEh 1.499969 *** *** *** *** *** *** 8001h 1.000015 8000h 1 (default) 7FFFh 0.999985 *** *** *** *** *** *** 0001h 0.500015 0000h 0.5 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 DAC8718 www.ti.com SBAS467A - MAY 2009 - REVISED DECEMBER 2009 APPLICATION INFORMATION BASIC OPERATION SDI CS SCLK 54 53 52 51 50 49 NC NC 55 USB/BTC SDO 2 NC RSTSEL LDAC 1 AVDD 56 RSTSEL 57 NC SCLK 58 NC CS 59 10kW DGND SDI 60 DVDD SDO 61 1 mF DVDD LDAC 62 1mF IOVDD WAKEUP 10mF 63 WAKEUP AVDD 64 NC IOVDD The DAC8718 is a highly-integrated device with high-performance reference buffers and output buffers, greatly reducing the printed circuit board (PCB) area and production cost. On-chip reference buffers eliminate the need for a negative external reference. Figure 101 shows a basic application for the DAC8718. AVDD 48 AVDD 10mF NC 47 AIN-0 3 AIN-0 VOUT-3 4 VOUT-3 VOUT-4 45 VOUT-4 REF-A 5 REF-A REF-B 44 REF-B VOUT-2 6 VOUT-2 VOUT-5 43 VOUT-5 VOUT-1 7 VOUT-1 VOUT-6 42 VOUT-6 AIN-1 46 8 AGND-A AIN-1 AGND-B 41 DAC8718 9 AGND-A OFFSET-A 10 OFFSET-A OFFSET-B 39 11 VOUT-0 VOUT-7 38 12 AVSS 24 NC 23 NC 22 GPIO-0 21 GPIO-1 20 DGND 19 NC 18 DGND 17 16 NC NC DVDD NC 34 NC 15 NC NC NC 35 RST 14 VMON CLR NC 36 GPIO-2 VMON 13 NC NC AVSS OFFSET-B VOUT-7 AVSS 37 NC 10mF VOUT-0 AGND-B 40 25 26 27 28 29 30 31 32 10mF AVSS NC 33 DVDD 10kW RST CLR 1mF 10kW 10kW NOTES: AVDD = +15V, AVSS = -15V, DVDD = +5V, IOVDD = +1.8V to +5V, REF-A = +5V, and REF-B = +2.5V. NOTES: The OFFSET-A and OFFSET-B pins must be connected to the AGND pin when used in unipolar operation. Figure 101. Basic Application Example Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 53 DAC8718 SBAS467A - MAY 2009 - REVISED DECEMBER 2009 www.ti.com PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the DAC8718 over the full operating temperature range, a precision voltage reference must be used. Careful consideration should be given to the selection of a precision voltage reference. The DAC8718 has two reference inputs, REF-A and REF-B. The voltages applied to the reference inputs are used to provide a buffered positive reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high-accuracy applications: initial accuracy, temperature coefficient of the output voltage, long-term drift, and output voltage noise. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight, long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference output voltage affects the output drift when the temperature changes. Choose a reference with a tight temperature coefficient specification to reduce the dependence of the DAC output voltage on ambient conditions. In high-accuracy applications, which have a relatively low noise budget, the reference output voltage noise also must be considered. Choosing a reference with as low an output noise voltage as practical for the required system resolution is important. Precision voltage references such as TI's REF50xx (2V to 5V) and REF32xx (1.25V to 4V) provide a low-drift, high-accuracy reference voltage. POWER-SUPPLY NOISE The DAC8718 must have ample supply bypassing of 1F to 10F in parallel with 0.1F on each supply, located as close to the package as possible; ideally, immediately next to the device. The 1F to 10F capacitors must be the tantalum-bead type. The 0.1F capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as common ceramic types, which provide a low-impedance path to ground at high frequencies to handle transient currents because of internal logic switching. The power-supply lines must be as large a trace as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line. Apart from these considerations, the wideband noise on the AVDD, AVSS, DVDD and IOVDD supplies should be filtered before feeding to the DAC to obtain the best possible noise performance. LAYOUT Precision analog circuits require careful layout, adequate bypassing, and a clean, well-regulated power supply to obtain the best possible dc and ac performance. Careful consideration of the power-supply and ground-return layout helps to meet the rated performance. DGND is the return path for digital currents and AGND is the power ground for the DAC. For the best ac performance, care should be taken to connect DGND and AGND with very low resistance back to the supply ground. The PCB must be designed so that the analog and digital sections are separated and confined to certain areas of the board. If multiple devices require an AGND-to-DGND connection, the connection is to be made at one point only. The star ground point is established as close as possible to the device. The power-supply traces must be as large as possible to provide low impedance paths and reduce the effects of glitches on the power-supply line. Fast switching signals must never be run near the reference inputs. It is essential to minimize noise on the reference inputs because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each other. This configuration reduces the effects of feedthrough on the board. A microstrip technique may be considered, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder-side. Each DAC group has a ground pin, AGND-x, which is the ground of the output from the DACs in the group. It must be connected directly to the corresponding reference ground in low-impedance paths to get the best performance. AGND-A must be connected with REFGND-A and AGND-B must be connected with REFGND-B. AGND-A and AGND-B must be tied together and connected to the analog power ground and DGND. During single-supply operation, the OFFSET-x pins must be connected to AGND-x with a low-impedance path because these pins carry DAC-code-dependent current. Any resistance from OFFSET-x to AGND-x causes a voltage drop by this code-dependent current. Therefore, it is very important to minimize routing resistance to AGND-x or to any ground plane that AGND-x is connected to. 54 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 PACKAGE OPTION ADDENDUM www.ti.com 5-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8718SPAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR DAC8718SPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR DAC8718SRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8718SRGZT ACTIVE VQFN RGZ 48 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8718SPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 DAC8718SRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 DAC8718SRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8718SPAGR TQFP PAG 64 1500 367.0 367.0 45.0 DAC8718SRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 DAC8718SRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 MECHANICAL DATA MTQF006A - JANUARY 1995 - REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0- 7 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. 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