3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 Clock Generation Chip MC100ES6039 Product Discontinuance Notice - Last Time Buy Expires on (12/19/2013) The MC100ES6039 is a low skew 2/4, 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/ disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = -3.135 V to -3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible 20-Lead Pb-Free Package Available MC100ES6039 REVISION 3 FEBRUARY 5, 2013 DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-07 EG SUFFIX 20-LEAD SOIC PACKAGE Pb-FREE PACKAGE CASE 751D-07 ORDERING INFORMATION Features * * * * * * * * * * DATASHEET 1 Device Package MC100ES6039DW SO-20 MC100ES6039DWR2 SO-20 MC100ES6039EG SO-20 (Pb-Free) MC100ES6039EGR2 SO-20 (Pb-Free) (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 Table 1. Pin Description Pin CLK EN ECL Diff Clock Inputs (1) ECL Sync Enable MR(1) ECL Master Reset 3 4 5 6 7 8 9 10 VBB ECL Reference Output CLK CLK VBB MR VCC NC DIVSELa 2 EN Function CLK(1) DIVSELb 1 VCC (1), Q0, Q1, Q0, Q1 ECL Diff 2/4 Outputs Q2, Q3, Q2, Q3 ECL Diff 4/6 Outputs DIVSELa(1) ECL Freq. Select Input 2/4 (1) ECL Freq. Select Input 4/6 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. DIVSELb ECL Positive Supply VCC Figure 1. 20-Lead Pinout (Top View) VEE ECL Negative Supply NC No Connect 1. Pins will default low when left open. DIVSELa Q0 CLK 2/4 Q0 R CLK Q1 Q1 Q2 EN 4/6 Q2 R Q3 MR DIVSELb Q3 VEE Figure 2. Logic Diagram Table 2. Function Tables CLK EN MR Z ZZ X L H X L L H Function Divide Hold Q0:3 Reset Q0:3 X = Don't Care Z = Low-to-High Transition ZZ = High-to-Low Transition MC100ES6039 REVISION 3 FEBRUARY 5, 2013 DIVSELa Q0:1 Outputs L H Divide by 2 Divide by 4 DIVSELb Q2:3 Outputs L H Divide by 4 Divide by 6 2 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP CLK Q (2) Q (4) Q (6) Figure 3. Timing Diagram CLK tRR RESET Q (n) Figure 4. Timing Diagram Table 3. Attributes Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test MC100ES6039 REVISION 3 FEBRUARY 5, 2013 3 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP Table 4. Maximum Ratings(1) Symbol Parameter Condition 1 VCC PECL Mode Power Supply VEE = 0 V VEE ECL Mode Power Supply VCC = 0 V VI PECL Mode Input Voltage ECL Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge IBB VBB Sink/Source Condition 2 Rating Units 3.9 V -3.9 V 3.9 -3.9 V V 50 100 mA mA 0.5 mA VI VCC VI VEE TA Operating Temperature Range -40 to +85 C Tstg Storage Temperature Range -65 to +150 C JA Thermal Resistance (Junction-to-Ambient) TBD TBD C/W C/W 0 LFPM 500 LFPM 20 SOIC 20 SOIC 1. Maximum Ratings are those values beyond which device damage may occur. Table 5. DC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1) Symbol Characteristic IEE Power Supply Current VOH Output HIGH Voltage(2) VOL Output LOW Voltage(2) VIH Input HIGH Voltage (Single-Ended) VIL VBB VPP VCMR -40C Min 0C to 85C Typ Max 35 60 Min Typ Unit 60 mA VCC -750 mV VCC -1950 VCC -1620 VCC -1250 VCC -2000 VCC -1680 VCC -1300 mV VCC -1165 VCC -880 VCC -1165 VCC -880 mV Input LOW Voltage (Single-Ended) VCC -1810 VCC -1475 VCC -1810 VCC -1475 mV Output Reference Voltage VCC -1400 VCC -1200 VCC -1400 VCC -1200 mV Differential Input VCC -1150 VCC -1020 VCC -800 VCC -1200 VCC -970 Voltage(3) Differential Cross Point IIH Input HIGH Current IIL Input LOW Current 35 Max Voltage(4) 0.12 1.4 0.12 1.4 V VEE+0.2 VCC-0.7 VEE+0.2 VCC-0.7 V 150 A 150 -200 -200 A 1. MC100ES6139 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. All loading with 50 to VCC-2.0 volts. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. MC100ES6039 REVISION 3 FEBRUARY 5, 2013 4 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP Table 6. AC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1) Symbol fmax Maximum Frequency tPLH, tPHL Propagation Delay tRR -40C Characteristic Min 25C Typ Max Min 875 850 575 500 Typ >1 CLK, Q (Diff) MR, Q Max Min 875 850 575 500 >1 575 500 Typ Max >1 Unit GHz 875 850 ps ps 200 100 200 100 200 100 ps ts Setup Time EN, CLK DIVSEL, CLK 200 400 120 180 200 400 120 180 200 400 120 180 ps ps th Hold Time CLK, EN CLK, DIVSEL 100 200 50 140 100 200 50 140 100 200 50 140 ps ps 550 450 550 450 550 450 ps tPW tSKEW Reset Recovery 85C Minimum Pulse Width Within Device Skew Q, Q Q, Q @ Same Frequency Device-to-Device Skew(2) tJITTER Cycle-to-Cycle Jitter VPP VCMR tr tf MR (RMS 1) Input Voltage Swing (Differential) Differential Cross Point Voltage Output Rise/Fall Times (20% - 80%) 150 80 50 300 80 50 300 ps ps ps 1 1 1 ps 1400 mV VCC-1.1 V 300 ps 1400 VEE+0.2 Q, Q 80 50 300 150 1400 VCC-1.1 VEE+0.2 50 300 150 VCC-1.1 VEE+0.2 50 300 50 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC -2.0 V. 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. Q D Receiver Device Driver Device Q D 50 50 VTT VTT = VCC -- 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation MC100ES6039 REVISION 3 FEBRUARY 5, 2013 5 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP PACKAGE DIMENSIONS PAGE 1 OF 2 CASE 751D-07 ISSUE J 20-LEAD SOIC PACKAGE MC100ES6039 REVISION 3 FEBRUARY 5, 2013 6 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP PACKAGE DIMENSIONS CASE 751D-07 ISSUE J 20-LEAD SOIC PACKAGE MC100ES6039 REVISION 3 FEBRUARY 5, 2013 7 PAGE 2 OF 2 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP Revision History Sheet Rev 3 Table Page 1 Description of Change Date Product Discontinuance Notice - Last Time Buy Expires on (12/19/2013) 2/5/2013 PACKAGE DIMENSIONS MC100ES6039 REVISION 3 FEBRUARY 5, 2013 8 (c)2013 Integrated Device Technology, Inc. MC100ES6039 Data Sheet 3.3V ECL/PECL/HSTL/LVDS /2/4, /4/6 CLOCK GENERATION CHIP We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. 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