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NJG1699MD7
Ver.2013-11-15
NOTE: Please note that any information on this catalog will be subject to change.
“H”=V
CTL(H),
“L”=V
CTL(L)
High Isolation SP4T SWITCH
GENERAL DESCRIPTION PACKAGE OUTLINE
The NJG1699MD7 is a GaAs high isolation SP4T switch MMIC. It
features low insertion loss and very high isolation. It has integrated
DC blocking capacitor at PC port.
The ESD protection circuits are integrated in the IC to achieve
high ESD tolerance.
The ultra-small and ultra-thin EQFN14-D7 package is adopted.
APPLICATIONS
Suitable for multi-mode 2G/3G and LTE application receive system
Rx signal switching
FEATURES
Low operation voltage V
DD
=+2.7V typ.
Low control voltage V
CTL(H)
=+1.8V typ.
High isolation 50dB typ. @f=1.0GHz, P
IN
=0dBm
48dB typ. @f=2.0GHz, P
IN
=0dBm
43dB typ. @f=2.7GHz, P
IN
=0dBm
Low insertion loss 0.55dB typ. @f=1.0GHz, P
IN
=0dBm
0.55dB typ. @f=2.0GHz, P
IN
=0dBm
0.65dB typ. @f=2.7GHz, P
IN
=0dBm
Small package EQFN14-D7 (Package size: 1.6x1.6x0.397mm typ.)
RoHS compliant and Halogen Free
MSL 1
PIN CONFIGURATION
TRUTH TABLE
ON PATH VCTL1 VCTL2
PC-P1 H L
PC-P2 L L
PC-P3 L H
PC-P4 H H
NJG1699MD7
(Top View)
GND
GND
GND
GND
GND
GND
PC
VDD
P4 P3
P2 P1
VCTL2
VCTL1
Pin connection
1. GND 8. GND
2. PC 9. VCTL2
3. VDD 10. VCTL1
4. GND 11. GND
5. P4 12. P2
6. GND 13. GND
7. P3 14. P1
Exposed PAD: GND
NJG1699MD7
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ABSOLUTE MAXIMUM RATINGS
(T
a
=+25°C, Z
s
=Z
l
=50Ω)
PARAMETER SYMBOL
CONDITIONS RATINGS UNITS
RF Input Power P
IN
V
DD
=2.7V 28 dBm
Supply Voltage V
DD
VDD terminal 5.0 V
Control Voltage V
CTL
VCTL1, VCTL2 terminal 5.0 V
Power Dissipation P
D
Four-layer FR4 PCB with through-hole
(76.2x114.3mm), T
j
=150°C 1300 mW
Operating Temp. T
opr
-40~+90 °C
Storage Temp. T
stg
-55~+150 °C
ELECTRICAL CHARACTERISTICS
(General conditions: T
a
=+25°C, Z
s
=Z
l
=50Ω, V
DD
=2.7V, V
CTL(L)
=0V, V
CTL(H)
=1.8V, with application circuit)
PARAMETERS SYMBOL
CONDITIONS MIN TYP MAX
UNITS
Supply Voltage V
DD
VDD terminal 1.5 2.7 4.5 V
Operating Current I
DD
- 20 40 µA
Control Voltage (LOW) V
CTL(L)
VCTL1, VCTL2 terminal 0 0 0.45 V
Control Voltage (HIGH)
V
CTL(H)
VCTL1, VCTL2 terminal 1.35 1.8 4.5 V
Control Current I
CTL
V
CTL(H)
=1.8V - 5 10 µA
Insertion Loss 1 LOSS1 f=1.0GHz, P
IN
=0dBm - 0.55 0.75 dB
Insertion Loss 2 LOSS2 f=2.0GHz, P
IN
=0dBm - 0.55 0.75 dB
Insertion Loss 3 LOSS3 f=2.7GHz, P
IN
=0dBm - 0.60 0.80 dB
Isolation 1 ISL1 PC-P1, P2, P3, P4
f=1.0GHz, P
IN
=0dBm 45 50 - dB
Isolation 2 ISL2 PC-P1, P2, P3, P4
f=2.0GHz, P
IN
=0dBm 45 48 - dB
Isolation 3 ISL3 PC-P1, P2, P3, P4
f=2.7GHz, P
IN
=0dBm 40 43 - dB
Input power at 0.2dB
Compression Point P
-0.2dB
f=2.0GHz 18 22 - dBm
VSWR VSWR f=2.0GHz, On port - 1.3 1.5 -
Switching time T
SW
50% V
CTL
to 10/90% RF - 2 5 µs
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NJG1699MD7
TERMINAL INFORMATION
No. SYMBOL DESCRIPTION
1 GND Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
2 PC RF input/output port. No DC blocking capacitor is required for this port
because of internal capacitor.
3 VDD
Positive voltage supply terminal. The positive voltage (+1.5~+4.5V) has to be
supplied. Please connect a bypass capacitor with GND terminal for excellent
RF performance.
4 GND Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
5 P4
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
6 GND Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
7 P3
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
8 GND Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
9 VCTL2 Control signal input terminal. This terminal is set to High-Level (+1.35~+4.5V)
or Low-Level (0~+0.45V).
10 VCTL1 Control signal input terminal. This terminal is set to High-Level (+1.35~+4.5V)
or Low-Level (0~+0.45V).
11 GND Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
12 P2
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
13 GND Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
14 P1
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
Exposed
Pad GND Ground terminal.
NJG1699MD7
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ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
NJG1699MD7
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ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
NJG1699MD7
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ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
NJG1699MD7
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ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
APPLICATION CIRCUIT
No external DC blocking capacitor at PC terminal is required because of the internal capacitor in IC.
PARTS LIST
Part ID Value Notes
C1~C4 56pF MURATA (GRM15)
C5 1000pF MURATA (GRM15)
1
2
3
4
5 6 7
8
9
10
11
121314
DECODER
1000pF
2.7V
0/1.8V
0/1.8V
PC
P1 P2
P3P4
56pF 56pF
56pF 56pF
NJG1699MD7
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APPLIED CIRCUIT BOARD EXAMPLES
(TOP VIEW)
<PCB LAYOUT GUIDELINE>
PRECAUTIONS
[1] The DC current at RF ports must be equal to zero, which can be achieved with DC blocking capacitors
(C1~C4).
(However, in case there is no possibility that DC current flows, the DC blocking capacitors are unnecessary, i.e. the
RF signals are fed by SAW filters that block DC current by nature, etc.)
[2] To reduce stripline influence on RF characteristics, please locate the bypass capacitor (C5) close to VDD
terminal.
[3] For good isolation, the GND terminals must be connected to the PCB ground plane of substrate, and the
through-holes connecting the backside ground plane should be placed near by the pin connection.
PCB:
FR
-
4, t=0.2mm
Capacitor Size: 1005 (1.0 x 0.5 mm)
Strip Line Width: 0.4mm
PCB Size: 25.8 x 25.8mm
Through Hole Diameter: 0.2mm
Paths Frequency
(GHz)
Loss
(dB)
1.0 0.31
2.0 0.44
PC-P1
PC-P2
PC-P3
PC-P4 2.7 0.55
Losses of PCB, capacitors and connectors
P2
P1
P3
P4
PC
C1
C2
C4
C3
C5
VCTL1
VCTL2
VDD
GND Via Hole
Diameter φ= 0.2mm
PKG Terminal
PCB
PKG Outline
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NJG1699MD7
RECOMMENDED FOOTPRINT PATTERN (EQFN14-D7 PACKAGE Reference)
Detail A
PKG:
1.6mm x 1.6mm
Pin pitch: 0.4mm
:Mask (Open area) *Metal mask thickness : 100um
:Resist(Open area)
:Land
NJG1699MD7
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PACKAGE OUTLINE (EQFN14-D7)
Exposed PAD
Ground connection is required.
Units : mm
Board : Cu
Terminal treat : SnBi
Molding material : Epoxy resin
Weight : 3.4mg
Caution
s
on using
this
product
This product contains Gallium-Arsenide (GaAs) which is a harmful material.
• Do NOT eat or put into mouth.
• Do NOT dispose in fire or break up this product.
• Do NOT chemically make gas or powder with this product.
•
To
wast
e
th
is
product, please obey the relati
ng
law
of
your
country.
This product may be damaged with electric static discharge (ESD) or spike voltage. Please handle
with care to avoid these damages
.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
