K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 1 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
Document Title
256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
1.0
Remark
Preliminary
Preliminary
Preliminary
Final
History
Initial draft
Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change ISB2 form 50mA to 60mA
Draft Date
May. 18 . 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 2 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
8Mb SB/SPB Synchronous SRAM Ordering Information
Org. Part Number Mode VDD Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz) PKG Temp
512Kx18
K7B801825B-Q(H)C(I)65/75/85 SB 3.3 6.5/7.5/8.5 ns
Q:
100TQFP
H:
119BGA
C:
Commercial
Temperature
Range
I:
Industrial
Temperature
Range
K7A801800B-Q(H)C(I)16/14 SPB(2E1D) 3.3 167/138 MHz
K7A801809B-Q(H)C(I)25/22/20 SPB(2E1D) 3.3 250/225/200 MHz
K7A801801B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz
K7A801808B-QC(I)25/22/20 SPB(2E2D) 3.3 250/225/200 MHz
256Kx32
K7B803225B-QC(I)65/75/85 SB 3.3 6.5/7.5/8.5 ns
K7A803200B-QC(I)16/14 SPB(2E1D) 3.3 167/138 MHz
K7A803209B-QC(I)25/22/20 SPB(2E1D) 3.3 250/225/200 MHz
K7A803201B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz
K7A803208B-QC(I)25/22/20 SPB(2E2D) 3.3 250/225/200 MHz
256Kx36
K7B803625B-Q(H)C(I)65/75/85 SB 3.3 6.5/7.5/8.5 ns
K7A803600B-Q(H)C(I)16/14 SPB(2E1D) 3.3 167/138 MHz
K7A803609B-Q(H)C(I)25/22/20 SPB(2E1D) 3.3 250/225/200 MHz
K7A803601B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz
K7A803608B-QC(I)25/22/20 SPB(2E2D) 3.3 250/225/200 MHz
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 3 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
The K7B803625B, K7B803225B and K7B801825B are
9,437,184-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pentium
and Power PC based System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B803625B, K7B803225B and K7B801825B are fabri-
cated using SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP and 119BGA pack-
age(100pin TQFP only for K7B803225B). Multiple power and
ground pins are utilized to minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
• Operating in commeical and industrial temperature range.
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
OE
ZZ
DQa
0
~ DQd
7
or DQa0 ~ DQb7
BURST CONTROL
LOGIC BURST 256Kx36/32 , 512Kx18
ADDRESS
CONTROL
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
LOGIC
CONTROL
REGISTER
CONTROL
REGISTER
A
′
0
~A
′
1
A
0
~A
1
or A
2
~A
18
or A
0
~A
18
DQPa ~ DQPd
A
0
~A
17
A
2
~A
17
(x=a,b,c,d or a,b)
DQPa,DQPb
FAST ACCESS TIMES
PARAMETER Symbol -65 -75 -85 Unit
Cycle Time tCYC 7.5 8.5 10 ns
Clock Access Time tCD 6.5 7.5 8.5 ns
Output Enable Access Time tOE 3.5 3.5 4.0 ns
OUTPUT
BUFFER
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 4 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
PIN CONFIGURATION(TOP VIEW)
PIN
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
3. DQPa~DQPd are NC for K7B803225B
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A17
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,42,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc/NC
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd/NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A15
A14
A13
A12
A11
A10
A17
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
A16
K7B803625B(256Kx36)
K7B803225B(256Kx32)
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 5 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A18
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
VDD
VSS
N.C.
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
N.C.
N.C.
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A15
A14
A13
A12
A11
A18
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
A16
K7B801825B(512Kx18)
A17
A10
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 6 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7B803625B(256Kx36)
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1234567
AVDDQ A A ADSP A A VDDQ
BNC CS2AADSC A A NC
CNC A A VDD A A NC
DDQc DQPc VSS NC VSS DQPb DQb
EDQc DQc VSS CS1VSS DQb DQb
FVDDQ DQc VSS OE VSS DQb VDDQ
GDQc DQc WEcADV WEbDQb DQb
HDQc DQc VSS GW VSS DQb DQb
JVDDQ VDD NC VDD NC VDD VDDQ
KDQd DQd VSS CLK VSS DQa DQa
LDQd DQd WEdNC WEaDQa DQa
MVDDQ DQd VSS BW VSS DQa VDDQ
NDQd DQd VSS A1*VSS DQa DQa
PDQd DQPd VSS A0*VSS DQPa DQa
RNC ALBO VDD NC ANC
TNC NC A A A NC ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0, A1
ADV
ADSP
ADSC
CLK
CS1
CS2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
VDDQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 7 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
K7B801825B(512Kx18)
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1234567
AVDDQ A A ADSP A A VDDQ
BNC CS2AADSC A A NC
CNC A A VDD A A NC
DDQb NC VSS NC VSS DQPa NC
ENC DQb VSS CS1VSS NC DQa
FVDDQ NC VSS OE VSS DQa VDDQ
GNC DQb WEbADV VSS NC DQa
HDQb NC VSS GW VSS DQa NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQb VSS CLK VSS NC DQa
LDQb NC VSS NC WEaDQa NC
MVDDQ DQb VSS BW VSS NC VDDQ
NDQb NC VSS A1*VSS DQa NC
PNC DQPb VSS A0*VSS NC DQa
RNC A LBO VDD NC ANC
TNC A A NC A A ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0,A1
ADV
ADSP
ADSC
CLK
CS1
CS2
WEx
(x=a,b)
OE
GW
BW
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQPa~Pb
VDDQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 8 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
FUNCTION DESCRIPTION
The K7B803625B, K7B803225B and K7B801825B are synchronous SRAM designed to support the burst address accessing
sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock
edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B803625B, a 256Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE (Interleaved Burst)
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE (Linear Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 9 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS2ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED OPERATION
HXXXLX X ↑N/A Not Selected
L L XLX X X ↑N/A Not Selected
LXHLX X X ↑N/A Not Selected
L L X X LX X ↑N/A Not Selected
LXHXLX X ↑N/A Not Selected
LHL L X X X ↑External Address Begin Burst Read Cycle
LHLHLXL↑External Address Begin Burst Write Cycle
LHLHLXH↑External Address Begin Burst Read Cycle
XXXH H LH↑Next Address Continue Burst Read Cycle
HXXXHLH↑Next Address Continue Burst Read Cycle
XXXH H L L ↑Next Address Continue Burst Write Cycle
HXXXHL L ↑Next Address Continue Burst Write Cycle
XXXH H H H ↑Current Address Suspend Burst Read Cycle
HXXXH H H ↑Current Address Suspend Burst Read Cycle
XXXHHH L↑Current Address Suspend Burst Write Cycle
HXXXH H L↑Current Address Suspend Burst Write Cycle
WRITE TRUTH TABLE( x36/32)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbWEcWEdOPERATION
H H XXXX READ
HLHHHH READ
HL L HHH WRITE BYTE a
HLHLH H WRITE BYTE b
HLH H L L WRITE BYTE c and d
HLLLLL WRITE ALL BYTEs
LXXXXX WRITE ALL BYTEs
TRUTH TABLES
WRITE TRUTH TABLE(x18)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbOPERATION
HHX X READ
HLH H READ
HL L HWRITE BYTE a
HLHLWRITE BYTE b
HL L L WRITE ALL BYTEs
LX X X WRITE ALL BYTEs
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 10 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDITION MIN MAX UNIT
Input Capacitance CIN VIN=0V -5pF
Output Capacitance COUT VOUT=0V -7pF
ASYNCHRONOUS TRUTH TABLE
Operation ZZ OE I/O STATUS
Sleep Mode HXHigh-Z
Read L L DQ
LHHigh-Z
Write LXDin, High-Z
Deselected LXHigh-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.465 V
VDDQ 3.135 3.3 3.465 V
Ground VSS 0 0 0 V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.465 V
VDDQ 2.375 2.5 2.9 V
Ground VSS 0 0 0 V
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.3 to 4.6 V
Voltage on VDDQ Supply Relative to VSS VDDQ VDD V
Voltage on Input Pin Relative to VSS VIN -0.3 to VDD+0.3 V
Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.3 V
Power Dissipation PD1.6 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TOPR 0 to 70 °C
Industrial TOPR -40 to 85 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 11 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
VSS
VIH
VSS-1.0V
20% tCYC(MIN)
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
Parameter Symbol Test Conditions Min Max Unit Notes
Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 µA
Output Leakage Current IOL Output Disabled, Vout=VSS to VDDQ -2 +2 µA
Operating Current ICC Device Selected, IOUT=0mA,
ZZ≤VIL , Cycle Time ≥ tCYC Min
-65 -300
mA 1,2-75 -280
-85 -260
Standby Current
ISB
Device deselected, IOUT=0mA,
ZZ≤VIL, f=Max, All Inputs≤0.2V or
≥ VDD-0.2V
-65 -140
mA-75 -130
-85 -120
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V) -100 mA
ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH -60 mA
Output Low Voltage(3.3V I/O) VOL IOL=8.0mA -0.4 V
Output High Voltage(3.3V I/O) VOH IOH=-4.0mA 2.4 -V
Output Low Voltage(2.5V I/O) VOL IOL=1.0mA -0.4 V
Output High Voltage(2.5V I/O) VOH IOH=-1.0mA 2.0 -V
Input Low Voltage(3.3V I/O) VIL -0.3* 0.8 V
Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.3** V3
Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V
Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.3** V3
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70
°
C)
TEST CONDITIONS
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER VALUE
Input Pulse Level(for 3.3V I/O) 0 to 3.0V
Input Pulse Level(for 2.5V I/O) 0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O 1.5V
Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2
Output Load See Fig. 1
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 12 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
PARAMETER SYMBOL -65 -75 -85 UNIT
MIN MAX MIN MAX MIN MAX
Cycle Time tCYC 7.5 -8.5 -10 -ns
Clock Access Time tCD -6.5 -7.5 -8.5 ns
Output Enable to Data Valid tOE -3.5 -3.5 -4.0 ns
Clock High to Output Low-Z tLZC 2.5 -2.5 -2.5 -ns
Output Hold from Clock High tOH 2.5 -2.5 -2.5 -ns
Output Enable Low to Output Low-Z tLZOE 0-0-0-ns
Output Enable High to Output High-Z tHZOE -3.5 -3.5 -4.0 ns
Clock High to Output High-Z tHZC -3.8 -4.0 -5.0 ns
Clock High Pulse Width tCH 2.2 -2.5 -3.0 -ns
Clock Low Pulse Width tCL 2.2 -2.5 -3.0 -ns
Address Setup to Clock High tAS 1.5 -2.0 -2.0 -ns
Address Status Setup to Clock High tSS 1.5 -2.0 -2.0 -ns
Data Setup to Clock High tDS 1.5 -2.0 -2.0 -ns
Write Setup to Clock High (GW, BW, WEX)tWS 1.5 -2.0 -2.0 -ns
Address Advance Setup to Clock High tADVS 1.5 -2.0 -2.0 -ns
Chip Select Setup to Clock High tCSS 1.5 -2.0 -2.0 -ns
Address Hold from Clock High tAH 0.5 -0.5 -0.5 -ns
Address Status Hold from Clock High tSH 0.5 -0.5 -0.5 -ns
Data Hold from Clock High tDH 0.5 -0.5 -0.5 -ns
Write Hold from Clock High (GW, BW, WEX)tWH 0.5 -0.5 -0.5 -ns
Address Advance Hold from Clock High tADVH 0.5 -0.5 -0.5 -ns
Chip Select Hold from Clock High tCSH 0.5 -0.5 -0.5 -ns
ZZ High to Power Down tPDS 2-2-2-cycle
ZZ Low to Power Up tPUS 2-2-2-cycle
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
353Ω / 1538Ω5pF*
+3.3V for 3.3V I/O
319Ω / 1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50ΩVL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
/+2.5V for 2.5V I/O
30pF*
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 13 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
01 1 1
1
00
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register 1
0 0 1 IDCODE Identification Register 3
0 1 0 SAMPLE-Z Boundary Scan Register 2
0 1 1 BYPASS Bypass Register 4
1 0 0 SAMPLE Boundary Scan Register 5
1 0 1 RESERVED Do Not Use 6
1 1 0 BYPASS Bypass Register 4
1 1 1 BYPASS Bypass Register 4
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 14 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
ID REGISTER DEFINITION
Part Revision Number
(31:28) Part Configuration
(27:18) Vendor Definition
(17:12) Samsung JEDEC Code
(11: 1) Start Bit(0)
256Kx36 0000 00110 00100 XXXXXX 00001001110 1
512Kx18 0000 00111 00011 XXXXXX 00001001110 1
SCAN REGISTER DEFINITION
Part Instruction Register Bypass Register ID Register Boundary Scan
256Kx36 3 bits 1 bits 32 bits 70 bits
512Kx18 3 bits 1 bits 32 bits 70 bits
119BGA BOUNDARY SCAN EXIT ORDER(x36)
36 4B ADSC OE 4F 35
37 4E CS1ADV 4G 34
38 4H GW CLK 4K 33
39 3G WEcBW 4M 32
40 3C AADSP 4A 31
41 3B AWEb5G 30
42 3A A A 5C 29
43 2B CS2 A5B 28
44 2C A A 5A 27
45 2A A A 6B 26
46 2D DQPc A6A 25
47 1E DQc A6C 24
48 2F DQc DQPb 6D 23
49 1G DQc DQb 6E 22
50 2H DQc DQb 6G 21
51 1D DQc DQb 7H 20
52 2E DQc DQb 7D 19
53 2G DQc DQb 7E 18
54 1H DQc DQb 6F 17
55 2K DQd DQb 7G 16
56 1L DQd DQb 6H 15
57 2M DQd DQa 7K 14
58 1N DQd DQa 6L 13
59 1P DQd DQa 6N 12
60 1K DQd DQa 7P 11
61 2L DQd DQa 6K 10
62 2N DQd DQa 7L 9
63 2P DQPd DQa 6M 8
64 3R LBO DQa 7N 7
65 3L WEdDQPa 6P 6
66 2R AZZ 7T 5
67 3T A A 6R 4
68 4N A1 WEa5L 3
69 4P A0 A5T 2
70 2T NC A4T 1
119BGA BOUNDARY SCAN EXIT ORDER(x18)
36 4B ADSC OE 4F 35
37 4E CS1ADV 4G 34
38 4H GW CLK 4K 33
39 3G WEbBW 4M 32
40 3C AADSP 4A 31
41 3B ANC 5G 30
42 3A A A 5C 29
43 2B CS2 A5B 28
44 2C A A 5A 27
45 2A A A 6B 26
46 2D NC A6A 25
47 1E NC A6C 24
48 2F NC NC 7D 23
49 1G NC NC 6E 22
50 2H NC NC 6G 21
51 1D DQb NC 7H 20
52 2E DQb DQPa 6D 19
53 2G DQb DQa 7E 18
54 1H DQb DQa 6F 17
55 2K DQb DQa 7G 16
56 1L DQb DQa 6H 15
57 2M DQb DQa 7K 14
58 1N DQb DQa 6L 13
59 2P DQPb DQa 6N 12
60 1K NC DQa 7P 11
61 2L NC NC 6K 10
62 2N NC NC 7L 9
63 1P NC NC 6M 8
64 3R LBO NC 7N 7
65 3L NC NC 6P 6
66 2R AZZ 7T 5
67 3T A A 6R 4
68 4N A1 WEa5L 3
69 4P A0 A5T 2
70 2T A A 6T 1
NOTE : NC ; Don’t care.
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 15 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
JTAG DC OPERATING CONDITIONS
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
1. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 3.135 3.3 3.465 V
Input High Level ( 3.3V I/O / 2.5V I/O ) VIH 2.0 / 1.7 -VDD+0.3 V1
Input Low Level ( 3.3V I/O / 2.5V I/O ) VIL -0.3 -0.8 / 0.7 V
Output High Voltage ( 3.3V I/O / 2.5V I/O ) VOH 2.4 / 2.0 - - V
Output Low Voltage ( 3.3V I/O / 2.5V I/O ) VOL --0.4 / 0.4 V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter Symbol Min Max Unit Note
TCK Cycle Time tCHCH 50 -ns
TCK High Pulse Width tCHCL 20 -ns
TCK Low Pulse Width tCLCH 20 -ns
TMS Input Setup Time tMVCH 5-ns
TMS Input Hold Time tCHMX 5-ns
TDI Input Setup Time tDVCH 5-ns
TDI Input Hold Time tCHDX 5-ns
SRAM Input Setup Time tSVCH 5-ns
SRAM Input Hold Time tCHSX 5-ns
Clock Low to Output Valid tCLQV 010 ns
JTAG AC TEST CONDITIONS
Parameter Symbol Min Unit Note
Input High/Low Level ( 3.3V I/O / 2.5V I/O ) VIH/VIL 3.0 / 0 , 2.5 / 0 V
Input Rise/Fall Time ( 3.3V I/O / 2.5V I/O ) TR/TF 1.0 / 1.0 , 1.0 /1 .0 ns
Input and Output Timing Reference Level VDDQ/2 V
TCK
TMS
TDI
PI
tCHCH
tMVCH tCHMX
tCHCL tCLCH
tDVCH tCHDX
tCLQV
TDO
(SRAM)
tSVCH tCHSX
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 16 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tSS tSH
tSS tSH
tAS tAH
A1 A2 A3
BURST CONTINUED WITH
NEW BASE ADDRESS
tWS tWH
tCSS tCSH
tADVS tADVH
tOE tHZOE
tLZOE tCD
tOH
(ADV INSERTS WAIT STATE)
tHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
Q1-1
Don′t Care
Undefined
tCYC
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 17 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
Data In
OE
Data Out
tCH tCL
tSS tSH
tAS tAH
A1 A2 A3
(ADSC EXTENDED BURST)
tLZOE
D2-1D1-1
tCSS tCSH
(ADV SUSPENDS BURST)
D2-2 D2-3 D2-4 D3-1 D3-2 D3-3D2-2 D3-4
Q0-3 Q0-4
tSS tSH
tWS tWH
tADVS tADVH
tDS tDH
TIMING WAVEFORM OF WRTE CYCLE
Don′t Care
Undefined
tCYC
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 18 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
OE
Data Out
tCH tCL
tDS tDH
Q3-3
Data In tOE tOH
A1 A2 A3
D2-1
Q3-1 Q3-2 Q3-4
tSS tSH
tAS tAH
tWS tWH
tADVS tADVH
tLZOE
tHZOE
tCD
tHZC tLZC
Don′t Care
Undefined
tCYC
Q1-1
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 19 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
CLOCK
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data In
tCH tCL
tHZOE
D6-1
Data Out
tWS tWH
tCD tOH
tOE
D5-1 D7-1
tWS tWH
tLZOE
tDH
tDS
A1 A2 A3 A4 A5 A6 A7 A8 A9
Q3-1Q1-1 Q2-1 Q4-1 Q8-1 Q9-1
tCSS tCSH
tSS tSH
Don′t Care
Undefined
tCYC
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 20 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
D7-1
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
OE
Data In
tCH tCL
tHZOE
Data Out
tAS tAH
tCD tOH
tOE
D5-1
tLZOE
tDHtDS
A1 A2 A3 A4 A5 A6 A9
Q3-1Q1-1 Q2-1 Q4-1 Q8-1 Q9-1
tCSS tCSH
tSS tSH
A7 A8
D6-1
Don′t Care
Undefined
tCYC
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 21 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
TIMING WAVEFORM OF POWER DOWN CYCLE
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
Data In
tCH tCL
D2-2
OE
tWH
tHZOE
tLZOE D2-1
A1
tSS tSH
Data Out
tPUS
A2
ADSC
Q1-1
ZZ
tAS tAH
tCSS tCSH
tOE
tHZC
tPDS
Sleep State
ZZ Setup Cycle
Normal Operation Mode
ZZ Recovery Cycle
tWS
Don′t Care
Undefined
tCYC
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 22 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
APPLICATION INFORMATION
DEPTH EXPANSION
Data
Address
CLK
ADS
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
256Kx36
SB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
256Kx36
SB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:18]
A
[18]
A
[0:17]
A
[18]
A
[0:17]
I/O
[0:71]
Microprocessor
CLOCK
ADSP
ADDRESS
Data Out
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
OE
Data Out
tSS tSH
A1 A2
WRITE
CS1
An+1
ADV
(Bank 0)
(Bank 1) Q2-1 Q2-2 Q2-4Q2-3
tAS tAH
tCSS tCSH
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
[0:n]
Don′t Care Undefined
tCD
tLZC
The Samsung 256Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
(ADSP CONTROLLED , ADSC=HIGH)
*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 23 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
APPLICATION INFORMATION
The Samsung 512Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
Data
Address
CLK
ADS
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
512Kx18
SB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
512Kx18
SB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:19]
A
[19]
A
[0:18]
A
[19]
A
[0:18]
I/O
[0:71]
CLOCK
ADSP
ADDRESS
Data Out
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
OE
Data Out
tSS tSH
A1 A2
WRITE
CS1
An+1
ADV
(Bank 0)
(Bank 1) Q2-1 Q2-2 Q2-4Q2-3
tAS tAH
tCSS tCSH
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
[0:n]
Don′t Care Undefined
tCD
tLZC
(ADSP CONTROLLED , ADSC=HIGH)
*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 24 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
PACKAGE DIMENSIONS
0.10 MAX
0~8°
22.00 ±0.30
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
1.40 ±0.10 1.60 MAX
0.05 MIN
(0.58)
0.50 ±0.10
#1
(0.83) 0.50 ±0.10
100-TQFP-1420A
0.65 0.30 ±0.10
0.10 MAX
+ 0.10
- 0.05
0.127
Units ; millimeters/Inches
K7B801825B 256Kx36/x32 & 512Kx18 Synchronous SRAM
- 25 - Rev 1.0
Nov 2001
K7B803225B
K7B803625B
119BGA PACKAGE DIMENSIONS
0.750±0.15
1.27
1.27
12.50±0.10
0.60±0.10 0.60±0.10
1.50REF
C1.00 C0.70
14.00±0.10
22.00±0.10
20.50±0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
Indicator of
Ball(1A) Location
