ol 67C401/13 67C402/23 Advanced ; Micro First-In First-Out (FIFO) 64x4, 64x5 Memory Devices 10/15 MHz (Cascadable) CMOS Features Ordering Information Zero standby power Part * High-speed 15-MHz shitt-in/shift-out rates Number |Package|Temp| Output Description Very low active power consumption 67401-10 Com | Totem Pole] 10 MHz 64x4 TTL-compatible inputs and outputs Readily expandable in word width and depth 87401-15 Com | Totem Pole) 15 MHz 64x4 RAM-based architecture for short tall-through delay 674013-10 cp 020 Com | 3-State 10 MHz 64x4 * Full CMOS 8-transistor cell for maximum nolse immunity 674013-15 | pp 020, Com |3-State 15MHz 64x4 * Asynchronous operation 67C402-10 | PL020 | Gon, | Totem Pole! 10MHz 64x5 Output Enabl 4013/23 * Output Enable feature (674013/23) 670402-15 Com |Totem Pole] 15MHz 64x5 General Description 67C4023-10 Cc 3-S 1OMHz 64x5 The 67C40X/XX series devices are high-performance CMOS - om |3-State ze RAM-based First-In First-Out (FIFO) buffer memory products 67C4023-15 Com | 3-State 15MHz 64x5 organized as 64 words by 4 or by 5 bits wide. These devices use Monolithic Memories latest CMOS process technology and Pin Configurations meet the demands for high-speed, low-power operation. By 67C401/13 utilizing an on-chip, dual-port RAM. a very short fall-through time is realized, thus improving overall system performance. By N Vw : : C/OE 6 using both Read and Write pointers for addressing each memory CG ps] vee location, the data can propagate to the outputs in much less time INPUT READY CI hs] SHIFT OUT than in traditional register-based FIFOs. These FIFOs are easily integrated into many applications and perform particularly well SHIFT IN CG ia] OUTPUT READY for high-speed disc controllers, graphics, and communication bo Ee 3] 00 network systems. The 550-, watt standby power specification makes these devices ideal for ultra-low-power and battery- D1 GE | o1 powered systems. DATA IN E ri OUTPUTS D2 [6 nf o2 Block Diagram of ra 2 INPUT SHIFT DATA IN READY IN exo [i [3] MASTER RESET INPUT INPUT 67C0402/23 >| CONTROL LoGic REGISTER vu MASTER i m MeSeT Nnc/BE a vec INPUT READY [2 17] SHIFT OUT WRITE 64x4/5 READ P| POINTER + DUAL PORT | POINTER SHIFT IN GI oO OUTPUT READY COUNTER ARAM COUNTER G FF cole 15] 00 01 @ ra] os OUTPUT OUTPUT OUTPUT OATA IN 02 Cf 3) 2 ouTPpuTSs ENABLE REGISTER CONTROL LOGIC o [7] 12] 03 o4 io 11} 04 . DATA OUT SHIFT OUTPUT ano [3] | MASTER RESET OUT READY ical Rey. Amendment 10683 A 70 Issue Date: May 1988 2-65Absolute Maximum Ratings Supply voltage Vo 62. EE EEE ene teen Cet EERE EEE ners -05Vto7V Input Voltage oo EE EEE EEE EEE EEE REET EERE eee EE nee -15Vto7V Off-state output voltage 6 EEE EE EEE EEE E EOE TE EEE EEE ES -05V to Voce +0.5V Storage temperature 206. en eee e Een EEC ern ern eens -65C to +150C Power dissipation... 00 enn ene E EE EE EEE EER een Een EEE EER CEE EEE tees 10W Latch-up trigger current (all OUtpUtS) . en EE EEE EEE Eee EE EES 140 mA Operating Conditions over Temperature Range SYMBOL PARAMETER FIGURE a ihcaiaateatinee UNIT Vcc Supply voltage 45 5.6 | 45 5.5 Vv Ta Operating free-air temperature 0 70 | 0 70 | C {iN Shift in rate 1 10 15 | MHz toi Shift in HIGH time 1.B 14 14 ns tsiL Shift in LOW time 1 25 25 ns tips Input data setup to SI (Shift In) 1 0 0 ns tloH Input data hold time from SI (Shift In) 1 40 40 ns trips Input data setup to JR (Input Ready) 3 0 0 ns tRiDH input data hold time from IR (Input Ready) 3 30 30 ns fout Shift out rate 4 10 15 | MHz |'SoH__ | ShitoutHIGH time 48 | 24 21 ns tsor Shift out LOW time 4 25 25 ns tMRW- Master Reset pulse 8 35 35 ns tures Master Reset to Si 8 65 65 ns * See AC lest and high-speed application nate Electrical Characteristics over Operating Conditions * 67C40X/XX-10 67C40X/XX-15 SYMBOL PARAMETER TEST CONDITION | MIN MAX | MIN MAX UNIT viv Low-level input voltage 08 0.8 Vv Vin" High-level input voltage 2 2 lin Input current Voc = MAX GND<ViN <Vcc ioc 1 -1 1 yA loz Off-state output current Voc = MAX GND<VouT <Voc -5 5 -5 5 uA lo = 20 nA 0.1 0.1 i VOL Low-level output voltage Voc = MIN Voi lol =8mA 0.4 0.4 IOH = -20 pA voc -0.1 Voc -0.1 VOH High-level output voltage Voc = MIN Voi 10H = -4mA 2.4 24 1os** | Output short-circuit current | Voc = MAX| Vo =0V -90 -20 | -90 -20. | mA Vin = Voc Standby supply current 100 100 | uA tcc | any supe ere" veg = MAX| Mit_= GND a ; lout =o Vit = MIN, Vip = MAX Operating supply current fin = tot = MAX 35 45 mA * These are absolute voltages with respect to GND (Pon 9) and include all overshoots due to system and or tester nose ** Not more than one outpul should be shorted ata tene and duration of the short cucurt should not exceed one second 2-66 67C401/13 67C402/23Switching Characteristics Over Operating Conditions SYMBOL PARAMETER FIGURE Mex Mena UNIT tia Shift Int to Input Ready LOW ; 60 55 | ns tiAH Shift In | to Input Ready HIGH 50 50 | ns torn Shift Out t to Output Ready LOW 55 45 | ns tory Shift Out} to Output Ready HIGH 4 50 41 | ns tODH Output Data Hold (previous word) 5 5 ns tops Output Data Shift (next word) 35 30 | ns ter Data throughput 3,6 100 90 | ns tmMRORL | Master Reset! to Output Ready LOW 100 100 | ns 'MRIRH Master Reset ; to Input Ready HIGH 8 100 100 | ns tMRO Master Reset | to Outputs LOW 35 35 ns tIPH Input ready pulse HIGH 3,B 19 16 ns topH Output ready pulse HIGH 6B 14 14 ns torpD Output ready ! to Data Valid 4 -3 -3 | ns *PHZ Output Disable Delay 6 - ns tpLz A 25 25 tPZL Output Enable Delay 30 %0 ns tpzH 30 30 * See AC test and high-speed application note Capacitances* SYMBOL PARAMETER TEST CONDITION ae | MI max [UNIT CIN Input capacitance Ta = 25C, f = 1 MHz 10 10 pF CouT | Output capacitance Voc =45V 7 7 | pF * Not tested in production. av ENABLE Vy f Vy ov ez He'erze| 81 AND $2 CLOSED WAVEFORM 1 $1 CLOSED 15V $2 OPEN Vr 4 vou *as Vou pzH Le tpriz o { | Vou WAVEFORM 2 81 OPEN V7 You -05V 82 CLOSED = 1.5 ov $1 AND Vr = 18 82 CLOSED Figure A. Enable and Disable Waveform 1 is for a data output with internal conditions such that (he output is low except when disabled by the output contro! Waveform 2 is fora data output with internal conditions such that the output is high except when disabled by the output control. 670401413 67C402/23 2-67Standard AC Test Load sv OUTPUT {@) TEST POINT R2 = 30 pF w Input Pulse Amplitude = 3 V input Rise and Fall Time (10%-90%) - 2.5 ns Measurements made at 1.5 V All Diodes are 1N916 or 1N3064 Functional Description Data input The FIFO consists of a dual-port RAM and two ring counters for read and write. After power-up, the Master Reset should be pulsed LOW, which internally resets both the read and write counters. When the Input Ready (!R) is HIGH, the FIFO is ready to accept DATA from the D, inputs. Data then present at the inputs is written into the first location of the RAM when Shilt-in (SI) is brought HIGH. A SI HIGH signal causes the IR to go LOW. When the St is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. The write pointer now points to the next location in the RAM. If the memory is full, then the IR will remain LOW. Data Output Data is read from the Oy outputs. Just after the first shift-in, the first data word is available at the outputs, which is indicated by the Output Ready (OR) going HIGH. When the OR is HIGH, data may be shifted out by bringing the Shift-Out (SO) HIGH. AHIGH signal at SO causes the read pointer to point to the next location in the RAM, and also the OR to go LOW. Valid data is maintained while the SO is HIGH. When the SO is brought LOW, the OR goes HIGH, indicating the presence of new valid data. If the FIFO is emptied, OR stays LOW, and O, remains as before, (i.e., data does not change if the FIFO is empty). A dual-port RAM inside the chip provides the capability of simultaneous and asynchronous writes (Shift-Ins)} and reads (Shift-Outs). Resistor Values lon R1 R2 8mA 600 1) 1200 0 Three-State Test Load TEST POINT vec R1 $1 cL $ S pF R2 $ 4--_} AC Test and High-Speed App. Notes Since the FIFO is a very-high-speed device, care must be exer- cised in the design of the hardware and the timing utilized within the design. Device grounding and decoupling is crucial to correct operation as the FIFO will respond to very smail glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. Monolithic Memories recom- mends a monolithic ceramic capacitor of 0.1 wF directly between - Voc and GND with very short lead length. In addition, care must be xercised in how the timing is set up and how the parameters are measured. For example, since an AND gate function is associated with both the Shift-In-Input Ready combination, as well as the Shift-Out-Output Ready combination, timing meas- urements may be misleading: i.e., rising edge of the Shift-In pulse is not recognized until input ready is HIGH. If Input Ready is not high due to (a) too high a frequency, or (b) FIFO being full or effected by Master Reset, the Shift-In activity will be ignored. This will affect the device from a functional standpoint, and will also cause the effective timing of Input Data Hold time (T/pH) and the next activity of Input Ready (Tip) to be extended relative to Shift-In going HIGH. This same type of problem is also related to TIRH. TORL. and TORH 4s related to Shift-In and Shift-Out. For high-speed applications, proper grounding tech- nique is essential. 2-68 67C40113 67C402/23SHIFT IN {gin (iu: i \ NAH INPUT READY \ f Lele > INPUT Dara wom QIAO a tog Figure 1. Input Timing SHIET IN Ye 55 INPUT READY 7 __ Q VAAAAAS [AAAAARAARAAAAAAAAAAAAAAAAAAARARAAAAAAAAAAAAAAAAAAAAL mvpur para YX)}\\ Xe STABLE DATA WUAN VINA YAN XAH EXAM ES AAH SRAM A AAA AAA Figure 2. The Mechanism of Shifting Data into the FIFO @ Input Ready HIGH indicates space is available and a Shift-In pulse may be apptied @ input Osta is loaded into the first available memory location. Input Ready goes LOW indicating this memory location is full. Shift-tn going LOW allows Input Ready to sense the status of the next memory location. The next memory location is empty as indicated by Input Ready HIGH. If the FIFO is already fuli then the Input Ready remains low. Note: Shift-in pulses applied whiie input Ready is LOW will be ignored SHIFT OUT . VMAAARAARARAAAS YYYAYYYANYYYYXK VAAARARARAARRAARAL VAS AANA AXXO (INPUT DATA STABLE DATA Figure 3. Data is Shifted in Whenever Shift In and Input Ready are Both HIGH CO AAAS @ FIFO is initially full. @ Shift In is held HIGH. @ Shitt Out pulse is applied. An empty location is detected by the interna! pointers on the falling edge of SO. @ As econ as Input Ready becomes HIGH the Input Data is loaded into this location. 67C401/13 67C402/23 2-69SHIFT OUT Figure 4. Output Timing The diagram assumes that the FIFO contains at jeast three words: A-Data (first input word). 8-Data (second input word), and C-Data (third input word) @ Output data changes on the falling edge of SO after a valid Shift-Out Sequence, ie., OR and SO are both high together. SHIFT OUT \ , OUTPUT READY OUTPUT DATA A-DATA B-DATA A OR B-> Figure 5. The Mechaniem of Shifting Data Out of the FIFO @ Output Ready HIGH indicates that data is available and a Shift-Out pulse may be applied, Shift-Out goes HIGH causing B-Data (second input word) to advance to the output register Output data remains as valid A-Dats while Shift-Out is HIGH. @ Output Ready goes LOW. @ Shift-out goes LOW causing Output Ready to go HIGH and new data (B} to appear at the data outputs, If the FIFO nas only one word loaded (A-Data) then Output Ready stays LOW and the output data remains the same (A-Data). SHIFT IN K SHIFT OUT 7 OUTPUT READY LY J Figure 6. tp7 and topy Specification FIFO initiatly empty. Shift-Out held HIGH. @ Shift-In pulse app A tutl | isd d by the i Pp On the falling edge of Shift-In. @ As soon as Output Ready becomes HIGH, the word is shifted out. 2-70 67C401/13 67C402/23SHIFT OUT \ pao _ VIITIITTTSET ETT TS. OUTPUT READY LEELLEATTAETETIOT TEE: @ OUTPUT DATA K A-DATA x Figure 7. Data is Shifted Out Whenever Shift Out and Output Ready are Both HIGH @ The internal logic does nol detect the presence of any words in the FIFO @ New data (A) arrives at the ouiputs @ Output Ready goes HIGH indicating arrival of the new data Since Shitt Out is held HIGH. Outpul Ready goes immediately LOW @ As soon as Shift Out goes LOW the Output Data's subject to change Output Ready will go HIGH or remain LOW depending on whether there are any additional words in the FIFO MASTER RESET y INPUT READY Pe tuRW OUTPUT READY I tMRIRH t tMROAL| at twrs SHIFT IN DATA OUTPUTS TTT] \ + tanoo| Figure 8. Master Reset Timing @ FIFO ts initally tull lec vs. Frequency sO wl - | I 8 2 oh 10/- T, = 06 fin = four Var = MAX, Vipq = MIN 0 4 1 i o 61 5 10 8 FREQUENCY MHz 67C401/13 670402/23 2-71Guaranteed Distribution of tip, ison v8. Temperature (For Cascadability Only) 87CAON/XX-15 Veo = 45 B7C4ON/XX-15 Voc = 55 AMBIENT TEMPERATURE C AMBIENT TEMPERATURE C 0 67C40K/XX-10 Voc = 45V 0 87C40X/XX-10 Veg = 8.5 'sou 15 . 10 Las 0 AMBIENT TEMPERATURE C AMBIENT TEMPERATURE C Guaranteed Distribution of topy, tgi}4 v8. Temperature (For Cascadabillty Only) 67C40X/XX-10/15 Voc: 45 B7C40X/XX-10/15 Veo *5.5V 70 AMBIENT TEMPERATURE C AMBIENT TEMPERATURE C Figure B. Cascadability 2-72 670401/13 67C402/23