LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 LF147/LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers Check for Samples: LF147, LF347-N FEATURES DESCRIPTION * * * * * * * * * * The LF147 is a low cost, high speed quad JFET input operational amplifier with an internally trimmed input offset voltage ( BI-FET IITM technology). The device requires a low supply current and yet maintains a large gain bandwidth product and a fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF147 is pin compatible with the standard LM148. This feature allows designers to immediately upgrade the overall performance of existing LF148 and LM124 designs. 1 23 Internally Trimmed Offset Voltage: 5 mV max Low Input Bias Current: 50 pA Low Input Noise Current: 0.01 pA/Hz Wide Gain Bandwidth: 4 MHz High Slew Rate: 13 V/s Low Supply Current: 7.2 mA High Input Impedance: 1012 Low Total Harmonic Distortion: 0.02% Low 1/f Noise Corner: 50 Hz Fast Settling Time to 0.01%: 2 s Simplified Schematic The LF147 may be used in applications such as high speed integrators, fast D/A converters, sample-andhold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device has low noise and offset voltage drift. Connection Diagram 1/4 Quad LF147 available as per JM38510/11906. Figure 1. 14-Pin PDIP / CDIP / SOIC Top View See Package Number J0014A, D0014A or NFF0014A 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BI-FET II is a trademark of dcl_owner. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated LF147, LF347-N SNOSBH1D - MAY 1999 - REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Absolute Maximum Ratings (1) (2) LF147 LF347B/LF347 22V 18V Differential Input Voltage 38V 30V (3) 19V 15V Continuous Continuous 900 mW 1000 mW Supply Voltage Input Voltage Range Output Short Circuit Duration Power Dissipation (4) (5) (6) Tj max 150C jA 150C CDIP (J) Package 70C/W PDIP (NFF) Package 75C/W SOIC Narrow (D) 100C/W SOIC Wide (D) 85C/W Operating Temperature Range See Lead Temperature (Soldering, 10 sec.) ESD Tolerance (1) (2) (3) (4) (5) (6) (7) (8) 260C 260C SOIC Package Vapor Phase (60 seconds) 215C Infrared (15 seconds) 220C (8) 900V (1) (2) Parameter Conditions LF147 Min VOS Input Offset Voltage RS=10 k, TA=25C VOS/ T Average TC of Input Offset Voltage RS=10 k IOS Input Offset Current Tj=25C, Max 1 5 10 (2) (3) Input Bias Current RIN Input Resistance Tj=25C, (2) (3) 25 50 LF347 Typ Max 3 5 10 100 200 25 50 Max 5 10 13 100 25 200 50 1012 mV mV V/C 10 8 1012 Units Typ 4 50 1012 Min 7 25 Over Temperature Tj=25C Min 8 Over Temperature IB LF347B Typ Over Temperature 2 260C Soldering (10 seconds) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. For operating at elevated temperature, these devices must be derated based on a thermal resistance of jA. Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside ensured limits. The LF147 is available in the military temperature range -55CTA125C, while the LF347B and the LF347 are available in the commercial temperature range 0CTA70C. Junction temperature can rise to Tj max = 150C. Human body model, 1.5 k in series with 100 pF. Symbol (3) (7) PDIP / CDIP DC Electrical Characteristics (1) (2) See -65CTA150C Storage Temperature Range Soldering Information (7) 100 pA 4 nA 200 pA 8 nA Refer to RETS147X for LF147D and LF147J military specifications. Unless otherwise specified the specifications apply over the full temperature range and for VS=20V for the LF147 and for VS=15V for the LF347B/LF347. VOS, IB, and IOS are measured at VCM=0. The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj=TA+jA PD where jA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 DC Electrical Characteristics (1)(2) (continued) Symbol AVOL Parameter Conditions Large Signal Voltage Gain VS=15V, TA=25C LF147 Min Typ 50 LF347B Max Min Typ 100 50 LF347 Max Min Typ 100 25 100 Units Max V/mV VO=10V, RL=2 k Over Temperature 25 VO Output Voltage Swing VS=15V, RL=10 k 12 13. 5 12 13. 5 12 13. 5 V VCM Input Common-Mode Voltage Range VS=15V 11 +15 11 +15 11 +15 V CMRR Common-Mode Rejection Ratio RS10 k PSRR Supply Voltage Rejection Ratio See IS Supply Current (4) 25 -12 (4) 15 -12 V/mV -12 V 80 100 80 100 70 100 dB 80 100 80 100 70 100 dB 7.2 11 7.2 11 7.2 11 mA Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice from VS = 5V to 15V for the LF347 and LF347B and from VS = 20V to 5V for the LF147. AC Electrical Characteristics Symbol (1) (2) Parameter Conditions LF147 Min Amplifier to Amplifier Coupling Typ LF347B Max Min -120 TA=25C, Typ LF347 Max Min -120 Typ Units Max -120 dB 13 V/s f=1 Hz-20 kHz (Input Referred) SR Slew Rate VS=15V, TA=25C 8 GBW Gain-Bandwidth Product VS=15V, TA=25C 2.2 4 MHz en Equivalent Input Noise Voltage TA=25C, RS=100, f=1000 Hz 20 20 20 nV / Hz in Equivalent Input Noise Current Tj=25C, f=1000 Hz 0.01 0.01 0.01 pA / Hz THD Total Harmonic Distortion AV=+10, RL=10k, <0.0 2 <0.0 2 <0.0 2 % VO=20 Vp-p, 13 8 4 2.2 13 8 4 2.2 BW=20 Hz-20 kHz (1) (2) Unless otherwise specified the specifications apply over the full temperature range and for VS=20V for the LF147 and for VS=15V for the LF347B/LF347. VOS, IB, and IOS are measured at VCM=0. Refer to RETS147X for LF147D and LF147J military specifications. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N 3 LF147, LF347-N SNOSBH1D - MAY 1999 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 4 Input Bias Current Input Bias Current Figure 2. Figure 3. Supply Current Positive Common-Mode Input Voltage Limit Figure 4. Figure 5. Negative Common-Mode Input Voltage Limit Positive Current Limit Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Negative Current Limit Output Voltage Swing Figure 8. Figure 9. Output Voltage Swing Gain Bandwidth Figure 10. Figure 11. Bode Plot Slew Rate Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N 5 LF147, LF347-N SNOSBH1D - MAY 1999 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 6 Distortion vs Frequency Undistorted Output Voltage Swing Figure 14. Figure 15. Open Loop Frequency Response Common-Mode Rejection Ratio Figure 16. Figure 17. Power Supply Rejection Ratio Equivalent Input Noise Voltage Figure 18. Figure 19. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Open Loop Voltage Gain Output Impedance Figure 20. Figure 21. Inverter Settling Time Figure 22. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N 7 LF147, LF347-N SNOSBH1D - MAY 1999 - REVISED MARCH 2013 www.ti.com Pulse Response RL=2 k, CL=10 pF Small Signal Inverting Large Signal Inverting Small Signal Non-Inverting Large Signal Non-Inverting Current Limit (RL=100) 8 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 APPLICATION HINTS The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on 4.5V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The LF147 will drive a 2 k load resistance to 10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pick-up" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N 9 LF147, LF347-N SNOSBH1D - MAY 1999 - REVISED MARCH 2013 www.ti.com Detailed Schematic 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 Typical Applications Figure 23. Digitally Selectable Precision Attenuator All resistors 1% tolerance * Accuracy of better than 0.4% with standard 1% value resistors No offset adjustment necessary * Expandable to any number of stages * Very high input impedance A1 A2 A3 VO 0 0 0 0 0 0 1 -1 dB 0 1 0 -2 dB 0 1 1 -3 dB 1 0 0 -4 dB 1 0 1 -5 dB 1 1 0 -6 dB 1 1 1 -7 dB Attenuation Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N 11 LF147, LF347-N SNOSBH1D - MAY 1999 - REVISED MARCH 2013 www.ti.com Figure 24. Long Time Integrator with Reset, Hold and Starting Threshold Adjustment * VOUT starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage: * Output starts when VINVTH * Switch S1 permits stopping and holding any output value * Switch S2 resets system to zero Figure 25. Universal State Variable Filter For circuit shown: fo=3 kHz, fNOTCH=9.5 kHz Q=3.4 Passband gain: Highpass--0.1 Bandpass--1 Lowpass--1 Notch--10 * foxQ200 kHz * 10V peak sinusoidal output swing without slew limiting to 200 kHz * See LM148 data sheet for design equations 12 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N LF147, LF347-N www.ti.com SNOSBH1D - MAY 1999 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LF147 LF347-N 13 PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LF147-MD8 ACTIVE DIESALE Y 0 100 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LF147J ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 LF347BN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF347BN LF347M NRND SOIC D 14 55 TBD Call TI Call TI 0 to 70 LF347M LF347M/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LF347M LF147J LF347MX NRND SOIC D 14 2500 TBD Call TI Call TI 0 to 70 LF347M LF347MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LF347M LF347N/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF347N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LF347MX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LF347MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF347MX SOIC D 14 2500 367.0 367.0 35.0 LF347MX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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