a YAMAHA & Si YAC516 DAC16-L Delta Sigma Modulation D/A Converter with 8 times Over-sampling Filter MOVERVIEW The YACS516 is a delta sigma D/A converter with 8 times over-sampling filter, designed for use with YAMAHA sound generator chips. Because of the built-in post filter and output buffer, high quality sound system can be designed with a small number of components. In addition, 3.3V operation and power down mode make the YAC516 most suitable for the sound system of Green PC and Notebook PC. MFEATURES - 1-bit delta sigma DAC. - Sampling rate ranging from 10kHz to 50kHz. - On chip 8 times over-sampling filter. Passband:20 kHz(@ fs=44.1 kHz) Passband ripple: +0.02dB Stopband attenuation: 57dB - On chip post filter. - On chip output buffer. - High tolerance to clock jitter. - THD+N: -86dB. - Dynamic range: 92dB. - Wide voltage operation: 3V ~ 5.25V - Low power dissipation: 75mW at SV. - 24 pin SSOP(YACS16-E), 28 pin SOP (YAC516-M). YAMAHA CORPORATION YAC516 CATALOG CATALOG No. : LSI-4AC516A4 1997.10YAU MEPIN LAYOUT YAC516-E TST1 DVDD DGND /PDIN AIC MCLK CKS BICK SDATA LRCK (N.C.) (N.C.) YAC516-M PUTT TPP PP o on nN DW OO FF WD HP = >_> oa -_- 12 24 23 22 O) 21 20 19 18 17 16 15 YAC516-E 14 13 UUUUUUUUUUUU 24pin SSOP Top View PUTT EE oO ON DW OHO FF WO LY = mak & O 6 - Oo 28 NA 27 26 25 24 23 YAC516-M ~ 21 20 19 18 17 16 15 UUUUUUUUUU UU 28pin SOP Top View TST2 VREFL VREFH (N.C.) (N.C.) AGND AVDD VCOM AOUTL AOUTR (N.C.) (N.C.) YAC516YAC516 VAMIAGIA EEPIN DESCRIPTION No Pin Name | I/O Function 24SSOP | 28SOP 1 1 TST1 I- | Test Pin Must be left floating or tied DGND 2 2 DVDD - | Digital power supply pin (+5V) 3 3 DGND - | Digital ground pin 4 4 /PDIN | | Power down input pin When this is brought "L" level, the YAC516 is switched to power down mode and is held in reset. The YAC516 should always be reset upon power-up. 5 5 (Ic 1 | Initial clear input pin This pin has the same function as the /PDIN pin. The /IC pin and /PDIN pin are ANDed internally. 6 6 MCLK | | Master clock input pin An external CMOS clock should be input on this pin. The input clock frequency is selected by CKS pin. 7 7 CKS | |Master clock select pin "H": MCLK=384 fs "L": MCLK=256fs 8 8 BICK | | Serial bit input clock pin This clock is used to latch SDATA. 9 9 SDATA | | Serial data input pin 2's compliment MSB-first data is input on this pin. 10 10 LRCK | {L/R clock pin This input determines which channel is currently being input on the SDATA pin. H':L$ch, "L": Roh 15 19 AOUTR | OA |Rch analog output pin 16 20 AOUTL | OA /|Lch analog output pin 17 21 VCOM OA |Common voltage pin, AVDD/2 Normally connected to AGND with a 0.1pF ceramic capacitor in parallel with a 10uF electrolytic capacitor. 18 22 AVDD - | Analog power supply pin(+5V) 19 23 AGND - |Analog ground pin 22 26 VREFH iA |"H" voltage reference input pin The differential voltage between VREFH and VREFL inputs set the analog output range. The VREFH pin is normally connected to AVDD and the VREFL pin is connected to AGND. A 0.1pF ceramic capacitor should be as near to both pins. 23 27 VREFL IA |"L" voltage reference input pin 24 28 TST2 O | Test pin Must be left floating. All pins except the above pins are NC (No Connection) pins. Do not connect externally. I-:Input pin with pull down resistor JA:Analog input pin OA:Analog output pinYAN YAC516 MBLOCK DIAGRAM DVDD LRCK BICK SDATA Serial Input Interface 8x Interpolator 8x Interpolator /PDIN AC MCLK MFUNCTION 1. System Clock DGND AZ Modulator Az Modulator CKS AVDD VREFH AGND VREFL Fig 1. Block diagram VCOM AOUTL AOQUTR The external clock which are required to operate the YAC516 are MCLK(256/384fs), LRCK (fs), BICK(32/s~). MCLK should be synchronized with LRCK but the phase is free of care. The frequency of MCLK is determined by the desired Input Word Rate (fs), and the setting of the Clock Select, CKS pins. Setting CKS to "L" level selects an MCLK frequency of 256fs while setting CKS to "H'" level selects 384/s. When the 384fs is selected, the internal master clock becomes 256fs(=384/s Xx 2/3). Table 1 illustrates standard audio word rates and corresponding frequencies used in the YACS16. As the YACS516 includes the phase detect circuit using LRCK, the YACS516 is reset automatically when the synchronization is out of phase by changing the clock frequencies.YAC516 _ YAMS Therefore, the reset is not needed except only upon power-up. (Please refer to the "4.System Reset" section.) All external clock(MCLK, BICK, LRCK) should always be present whenever the YACS516 is in normal operation mode(/PDIN = /RST = "H"). If these clock are not provided, the YAC516 may draw excess current and do not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clock are not present, the YAC5S16 should be in the power-down mode (/PDIN = "L" or /RST ="L"), Table 1. Example of Master Clock LRCK (fs) (kHz) CKS MCLK (MHz) 32.0 L 8.1920 H 12.2880 44.1 L 11.2896 H 16.9344 48.0 L 12.2880 H 18.4320 2.Serial Data Interface The YAC516 has three serial input pins(SSDATA, BICK, LRCK). Data bits is clocked into the YACS16 via SDATA pin and is latched by LRCK. The data format is MSB-first and 2's compliment. tack | ich Ach [ ack TULTN| Pn) Ain (nnn) unin. SDATA | [Dont Care igiaigra) ERT Don't Care 1414/19]19 ETT] Fig 2. Data Input Format 3. Power-Down Mode The YAC516 is placed in the power-down mode by setting /PDIN (or /IC) to "L" level. In the power-down mode, the analog output pins go floating. 4.System Reset The YAC516 should be reset once by bringing /PDIN (or /IC) to "L" level upon power-up. The internal timing starts clocking by the rising edge of LRCK after exiting reset by MCLK. If the phase difference between LRCK and internal control signals isAMAIA YAC516 larger than +1/16 ~ -1/16 of word period(1/fs), the synchronization of internal control signals with LRCK is done automatically at the first rising edge of LRCK. Since RAM address shifts during this synchronization, the correct data would not be output until 18 sampled data input. 5. Grounding and Power Supply Decoupling The DAC requires careful attention to power supply and grounding arrangement. Figure 3 shows a example of power arrangements which AVDD is supplied from a clean analog supply in system and DVDD is supplied from AVDD via 10Q resistor. Alternatively if AVDD and DVDD are supplied separately, AVDD and DVDD should be powered at the same time op AVDD should be powered earlier than DVDD. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitor for high frequency should be as near to the YAC516 as possible, with the low value ceramic capacitor across VREFH and VREFL being the nearest. 6.SYSTEM DESIGN 10 + r WA, aa +t < +5V Analog ion 0.1 nT T0.1 ul oF Ou DVDD AVDD Audio LRCK VREFH oy Data BICK Ap VREFL f Processor SDATA L External MCLK AOUTLL_+ Leh Analog Out Mode Select CkS Power Down /PDIN AOUTRF-_ Rch Analog Out Control AC TST1 VCOM + _L | TST2 10p [et ~ Fig 3. Typical Connection DiagramYAC516 YANWUA TIA MELECTRICAL SPECIFICATION 1.ABSOLUTE MAXIMUM RATING (AGND, DGND=0V; Note 1) Parameter Symbol min max units Power Supplies: Analog (AVDD pin) AVDD -0.3 6.0 Vv Digital (DVDD pin) DVDD -0.3 AVDD+0.3 Vv Input Current, Any pin except Supplies lin - +10 mA Input Voltage Vino -0.3 AVDD+0.3 Vv Ambient Operating Temperature Top 0) 70 Cc Storage Temperature Tstq -50 125 Cc Note: 1. All voltages with respect to ground. Warning: Operation at or beyond these limits may result in permanent damage to the device. Norma! operation is not guaranteed at these extremes. 2. RECOMMENDED OPERATING CONDITIONS (AGND, DGND=OV; Note 1) Parameter Symbol min typ max units Power Supplies: Analog (AVDD pin) AVDD 3.0 5.0 5.25 Vv Digital (DVDD pin) DVDD 3.0 5.0 |! AVDD Vv AVDD - DVDD AVDD 0 - 1.0 Vv "H" Level Voltage Reference (Note 2); VREFH - AVDD - V "L" Level Voltage Reference VREFL - AGND - Vv VREFH VREFL AVREF 2.5 - AVDD V Note: 1.All voltages with respect to ground. 2.AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. 3.Analog output voltage scales with the voltage of (VREFH-VREFL). AOUT(typ. @O0dB) = 2.88 x (VREFH - VREFL)/5.YANISANTIA YAC516 3.ANALOG CHARACTERISTIC (Top=25C; AVDD, DVDD=5.0V; VREFH=AVDD, VREFL=AGND; fs=44.1kHz; Signal Frequency=1kHz; RL>10kQ; Measurement Bandwidth=10Hz~20kHz; unless otherwise specified) Parameter [min typ max units Dynamic Characteristics THD+N -80 -86 dB (Note 4) -74 -80 dB Dynamic Range (A-Weighted) 86 92 dB (Note 4) 82 88 dB S/N (A-Weighted) 86 92 dB (Note 4) 82 88 dB Cross talk 80 90 dB DC Accuracy Gain Drift 60 ppm/C Maximum Output Voltage (Note 5) 2.73 2.88 3.03 Vv (Note 4) 1.80 1.90 2.00 V Power Supplies Power Supply Current (Note 6) Normal Operation AVDD 11 15 mA DVDD 4 6 mA Power-Down Mode AVDD+DVDD 10 50 pA Power Dissipation , Normal Operation 75 105 mw Power-Down Mode (Note 7) 50 250 pW Power Supply Rejection 50 dB Note: 4.AVDD, DVDD = 3.3V 5.Full-scale voltage (OdB). Output voltage scale with the voltage of (VREFH - VREFL) AOUT(typ. @O0dB) = 2.83 x (VREFH - VREFL)/5. 6.The typical supply current of DVDD drops to 2.2mA at 3.3V supply voltage. The AVDD supply current does not change. 7.External clocks (MCLK, BICK, LRCK) are fixed to "H" level (or "L" level).YAC516 VANS 4. FILTER CHARACTERISTIC (Top=25C; AVDD, DVDD=3.0 ~ 5.25V; fs=44.1kHz) Parameter | Symbol | min | typ | max units Digital Filter Passband +0.1dB_ (Note 8) PB 0 18.0 kHz -3.0dB 0 20.0 kHz -6.0dB 0 22.05 kHz Stopband (Note 9) SB 26.0 kHz Passband Ripple PR +0.02 dB Stopband Attenuation SA 57 dB Group Delay (Note 9) GD 14.2/ fs $s DAC 2nd Order Analog Filter Frequency Response 18kHz -0.1 dB 20.0kHz -0.5 dB 44.1kHz -6.0 dB Note: 8.The passband and stopband frequencies scale with fs. For example, PB=0.4535/s(@-3.0dB), SB=0.5896fs(@-57dB) 9. The calculating delay time which occurred by digital filtering. This time is from setting the 16-bit data of both channels to input register to the output of analog signal. GD=14.2/fs @fs=44.1 kHz 5. DIGITAL CHARACTERISTIC (Top=25C; AVDD, DVDD=3.0 ~ 5.25V; fs=44.1kHz) Parameter Symbol min typ max units "H"Level Input Voltage Vin | 70%DVDD - - V "L" Level Input Voltage Vit - - 30%DVDD V Input Leakage Current lin - - +10 pAVANS YAC516 6. SWITCHING CHARACTERISTIC (Top=25C; AVDD, DVDD=3.0 ~ 5.25V; C.=20pF) Parameter Symbol min typ max units Master Clock Frequency 2568: fox 2.56 11.2896 12.8 MHz Pulse Width Low teLk 28 ns Pulse Width High teLkH 28 ns 3848s: foux 3.84 16.9344 19.2 MHz Pulse Width Low teLKL 23 ns Pulse Width High teLKH 23 ns LRCK Frequency fs 5 44.1 50 kHz Serial Interface Timing (Note 10) BICK Period tack 313 ns BICK Pulse Width Low tack. 100 ns BICK Pulse Width High tackn 100 ns LRCK Hold Time (note 11) | thay 50 tack_-50 | ns LRCK Setup Time (note 11); tLrRs 50 SDATA Hold Time tspH 50 ns SDATA Setup Time tsps 50 ns Reset Timing /PDIN, /IC pulse Width (Note12)!_ ticw 100 ns Note: 10. Refer to the operating overview section "Serial Data Interface". 11. BICK rising edge must not occur at same time as LRCK edge. 12. The YAC516 can be reset by bringing /PDIN (or /IC) "L" to "H" only upon power up. 7. TIMING CHART toukt tcLKH. | MCLK TS J Chart 1. Master Clock Input Timing tack. |, tacuH 50%DVDD 50%DVDD SDATA7777- x sorrosocncnssees x b-- LSB yy sosseeepescsess x. sorrsecseses 50%DVDD LAH 'Las_,| LROK rrr trent cen pec en ccc Bcc cnn cc dan anccec cans cence ceera cn 50%DVDD Chart 2. Data Input Timing licw IPDIN AG 72-00 cccecenecnce enn eon ne cenc none nnee conan ern enenennenenenes senenenancs 30%DVOD Chart 3. Reset Timing 10YAC516 YANNI MPACKAGE YAC516-E (24SSOP) 7.80+0.40 24 13 MIND OOD 00 9 % a o oO t : + = oO Oo 3 i O : S 1 12 CS % 0.20+0.10 4h P-O.65TYP. <2 0-10 HES = 5 es >, me x 4 = wo | sw oD zi =6 O . > AYAAOTARSLEBMRe TS. < EK KARTEL YU EBEGL, o M4z(UNIT) : mm(millimeters) The figure in the parenthesis (_ ) FIX: 0.17+40.05 should be used as a reference. (LEAD THICKNESS) Plastic body dimensions do not include burr of resin. UNIT: mm Note : The LSIs for surface mount need especial consideration on strage and soldering conditions. For detailed information, please contact your nearest agent of yamaha. 41YAMUANTI YAC516 YAC516-M (28SOP) 18.10+0.30 TOMINOMon onan ror Deo to 4 | TUTOUTOTOO TT fF 1 27/P | | al j 340%0.10 . im GS 2 0.15+0.10 (LEAD THICKNESS) 3.00MAX 2.60+0.15 oO t oO + jt | 6 & 0-10 | AyIAIAOTTAELESae TS. Hifi (UNIT) : mm(millimeters) The figure in the parenthesis (_) should be used as a reference. UNIT: mm yamaha. Note : The LSIs for surface mount need especial consideration on strage and soldering conditions. For detailed information, please contact your nearest agent of 12YAC516 YAMANE MEMO 13AIM AN A YAC516 rc ~ IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE. The specifications of this product are subject to improvement changes without prior notice. ( _ AGENCY _- YAMAHA CORPORATION Address inquiries to: Semiconductor Sales & Marketing Department = Head Office 203, Matsunokijima, Toyooka-mura, Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 = Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 = Osaka Office Namba Tsujimoto Nissei Bldg. 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 = U.S.A. Office YAMAHA Systems Technology 100 Century Center Court, San Jose, CA 95112 Tel. +1-408-467-2300 Fax. +1-408-437-8791 COPYING PROHIBITED : 1987 YAMAHA CORPORATION 0.2K 8402 OH