FN6498 Rev 3.00 Page 1 of 25
Aug 25, 2010
FN6498
Rev 3.00
Aug 25, 2010
ISL6252, ISL6252A
Highly Integrated Battery Charger Controller for Notebook Computers
DATASHEET
The ISL6252, ISL6252A is a highly integrated battery charger
controller for Li-ion/Li-ion polymer batteries. High Efficiency is
achieved by a synchronous buck topology. The low side
MOSFET emulates a diode at light loads to improve the light
load efficiency and prevent system bus boosting.
The constant output voltage can be selected for 2, 3 and 4
series Li-ion cells with 0.5% accuracy over-temperature. It can
also be programmed between 4.2V + 5%/cell and
4.2V - 5%/cell to optimize battery capacity. When supplying
the load and battery charger simultaneously, the input current
limit for the AC adapter is programmable to within 3%
accuracy to avoid overloading the AC adapter, and to allow
the system to make efficient use of available adapter power
for charging. It also has a wide range of programmable
charging current. The ISL6252, ISL6252A provides outputs
that are used to monitor the current drawn from the AC
adapter, and monitor for the presence of an AC adapter. The
ISL6252, ISL6252A automatically transitions from regulating
current mode to regulating voltage mode.
Features
• ±0.5% Charge Voltage Accuracy (-10°C to +100°C)
• ±3% Accurate Input Current Limit
• ±3% Accurate Battery Charge Current Limit
• ±25% Accurate Battery Trickle Charge Current Limit
• Programmable Charge Current Limit, Adapter Current
Limit and Charge Voltage
• Fixed 300kHz PWM Synchronous Buck Controller with
Diode Emulation at Light Load
• Overvoltage Protection
• Output for Current Drawn from AC Adapter
• AC Adapter Present Indicator
• Fast Input Current Limit Response
• Input Voltage Range 7V to 25V
• Support 2-, 3- and 4-Cells Battery Pack
• Up to 17.64V Battery-Voltage Set Point
• Thermal Shutdown
• Less than 10µA Battery Leakage Current
• Supports Pulse Charging
• Pb-free (RoHS Compliant)
Applications
• Notebook, Desknote and Sub-notebook Computers
• Personal Digital Assistant
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6252HRZ ISL 6252HRZ -10 to +100 28 Ld 5x5
QFN
L28.5x5
ISL6252HAZ ISL 6252HAZ -10 to +100 24 Ld
QSOP
M24.15
ISL6252AHRZ ISL6252 AHRZ -10 to +100 28 Ld 5x5
QFN
L28.5x5
ISL6252AHAZ ISL6252 AHAZ -10 to +100 24 Ld
QSOP
M24.15
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die
attach materials, and 100% matte tin plate plus anneal
(e3 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering
operati ons). Intersil P b-free products are MSL classified
at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requir ements of IPC/JEDEC J STD-
020.
3. For Moisture Sensi tivity Level (MSL) , please see device
information page for ISL6252, ISL6252A. For more
information on MSL please see techbrief TB363.
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 2 of 25
Aug 25, 2010
Pinouts
ISL6252, ISL6252A
(28 LD QFN)
TOP VIEW
ISL6252, ISL6252A
(24 LD QSOP)
TOP VIEW
1
2
3
4
5
6
7
21
20
19
18
17
16
15
28 27 26 25 24 23 22
8 9 10 11 12 13 14
EN
CELLS
ICOMP
VCOMP
ICM
VREF
CHLIM
ACLIM
PGND
LGATE
VDDP
BOOT
CSOP
PHASE
UGATE
ACSET
DCIN
ACPRN
CSON
VADJ
GND
CSIN
CSIP
NA
NA
NA
VDD
NA
DCIN
124
VDD
223
ACPRN ACSET
322
CSON
421
CSOP
EN
520
CSIN
CELLS
619
CSIP
ICOMP
718
VCOMP
817
ICM
916
PHASE
VREF
10 15
UGATE
CHLIM
11 14
BOOT
ACLIM
12 13
VDDP
VADJ LGATE
GND PGND
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 3 of 25
Aug 25, 2010
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
+
-
514k
32k
DCIN
VDD
BOOT
UGATE
PHASE
EN
GND FB CSON CSOP CHLIM
ACLIM
ICOMP
VCOMP
VADJ
CELLS
VREF
ICM CSIP CSIN
+-
+
-
CA1
X19.9
+
-
CA2
X19.9
1.26V
ACSET
ACPRN
LDO
REGULATOR
VDDP
LGATE
PGND
PWM
300kHz
RAMP
+
-
1.065V
16k
48k
288k
+
-
gm1
REFERENCE
VOLTAGE
SELECTOR
VDD
514k
VREF
152k
152k
VREF
2.1V
MIN
CURRENT
BUFFER
gm3
ADAPTER
CURRENT
LIMIT SET
+
-
MIN
VOLTAGE
BUFFER
+
-
gm2
-0.25
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 4 of 25
Aug 25, 2010
FIGURE 2. ISL6252, ISL6252A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
ICM
GND
DCIN
ACSET
VDDP
VDD
ACPRN
ICOMP
VCOMP
VADJ
EN
ACLIM
VREF
CHLIM
Q1
L
4.7µH
F
C10
R1
AC ADAPTER
R5
100k
R8
130k
1%
R9
10.2k
1%
C4
0.1µF
1µF
ISL6252
ISL
FLOATING
4.2V/CELL
R10
4.7
3.3V
BAT+
BAT-
VDD
4 CELLS
D1
D2
VDDP
VREF
TRICKLE
CHARGE
R12
20k 1%
Q6
130k
1%
R13
1.87k
1%
2.6A CHARGE LIMIT
253mA TRICKLE CHARGE
CHARGE
ENABLE
C11
3300pF
R7: 100
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
ICM
GND
DCIN
ACSET
VDDP
VDD
ACPRN
ICOMP
VCOMP
VADJ
EN
ACLIM
VREF
CHLIM
Q2 L
µ
1%
0.1
C9
1
ISL6252
IS6252
R10
C7
1µF
BAT-
VDD
D1
OPTIONAL
D2
C5
C6
R6
TO HOST
CONTROLLER
R11
C1:10
BATTERY
PACK
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
ICM
GND
DCIN
ACSET
VDDP
VDD
ACPRN
ICOMP
VCOMP
VADJ
EN
ACLIM
VREF
CHLIM
Q1
L
F
C10
20m
100k
C4
0.1
1
ISL6252
ISL6252
R10
4.7
3.3V
BAT-
VDD
4 CELLS
D1
D2
R12
20k 1%
R13
2.6A CHARGE LIMIT
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
ICM
GND
DCIN
ACSET
VDDP
VDD
ACPRN
ICOMP
VCOMP
VADJ
EN
ACLIM
VREF
CHLIM
Q2 L
0.1
1
ISL6252
R10
C7
BAT-
VDD
D1
D2
R11
C1:10
4.7k
10nF
6.8nF
ISL6252A
22µF
SYSTEM LOAD
R2
20m
R21
C2
0.1µF
0.1
2.2
C2
0.1
0.1
R22 22
C3C3
R11 22
R12 22
0.047µF
C8
0.1µF
VDD
R23
10k
D5
1N914
D3 D4
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 5 of 25
Aug 25, 2010
FIGURE 3. ISL6252, ISL6252A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
VADJ
GND
DCIN
ACSET
VDDP
VDD
ACPRN
CHLIM
EN
ICM
ACLIM
VREF
ICOMP
VCOMP
Q1
Q2
C1:10µF
SYSTEM LOAD
R1
ADAPTER
R2
20m
R21
R6
R5
100k
R8
130k
1%
R9
10.2k
1%
C2
0.1µF
C4
0.1µF
C3
C5
10nF
C6
6.8nF
C9
1µF
D3
ISL6252
ISL6252
C7
µF
R10
4.7
BAT+
SCL
SDL
TEMP
BAT-
SCL
SDL
A/D INPUT
GND
VCC
D/A OUTPUT
OUTPUT
DIGITAL
INPUT
HOST
AVDD/VREF
GND
FLOATING
4.2V/CELL
5.15A INPUT
CURRENT LIMIT
R11, R12
R13: 10k
A/D INPUT
100k
R7: 100
C11
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
VADJ
GND
DCIN
ACSET
VDDP
VDD
ACPRN
CHLIM
EN
ICM
ACLIM
VREF
ICOMP
VCOMP
R1
R6
4.7k
1%
0.1
0.1
1
GND
BATTERY
PACK
ISL6252
ISL
3300pF
VDDP
D2
D1
OPTIONAL
CSIN
UGATE
PHASE
LGATE
PGND
CSOP
CSON
CELLS
VADJ
GND
DCIN
ACSET
VDDP
VDD
ACPRN
CHLIM
EN
ICM
ACLIM
VREF
ICOMP
VCOMP
Q2
SYSTEM LOAD
R1
2.2
C2
0.1
C4
0.1
C3
C6
C9
C7
R10
GND
3-CELLS
R16
R7:
C11
CSIP
BOOT
R1
20m
0.1
0.1
1
1
GND
ISL6252
3300pF
VDDP
D2
D1
ISL6252A
L
4.7µH
C10
22µF
R22 22
R11 22
R12 22
0.047µF
C8
0.1µF
VDD
R23
10k
D5
1N914
CSON
D4
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 6 of 25
Aug 25, 2010
Absolute Maximum Ratings Thermal Information
ACSET to GND (Note 4) . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +35V
BOOT to VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 28V
ACLIM, ACPRN, CHLIM, VDD to GND . . . . . . . . . . . . . . -0.3V to 7V
BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD +0.3V
VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . PHASE -0.3V to BOOT +0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . PGND -0.3V to VDDP +0.3V
Thermal Resistance JA
(°C/W) JC (°C/W)
QFN Package (Notes 5, 6). . . . . . . . . . 39 9.5
QSOP Package (Note 5) . . . . . . . . . . . 80 N/A
Junction Temperature Range. . . . . . . . . . . . . . . . . . -10°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. ACSET may be operated 1V below GND if the current through ACSET is limited to less than 1mA.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA, TA= -10°C to +100°C,
TJ+125°C, Unless Otherwise Noted. Boldface limits apply over the operating temperature
range, -10°C to +100°C.
PARAMETER TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
SUPPLY AND BIAS REGULATOR
DCIN Input Voltage Range 725V
DCIN Quiescent Current EN = VDD or GND, 7V DCIN 25V 1.4 3mA
Battery Leakage Current (Note 6) DCIN = 0, no load 3 10 µA
VDD Output Voltage/Regulation 7V DCIN 25V, 0 IVDD 30mA 4.925 5.075 5.225 V
VDD Undervoltage Lockout Trip Point VDD Rising 4.0 4.4 4.6 V
Hysteresis 200 250 400 mV
Reference Output Voltage VREF 0 IVREF 300µA 2.365 2.39 2.415 V
Battery Charge Voltage Accuracy CSON = 16.8V, CELLS = VDD, VADJ = Float-0.5 0.5 %
CSON = 12.6V, CELLS = GND, VADJ = Float -0.5 0.5 %
CSON = 8.4V, CELLS = Float, VADJ = Float -0.5 0.5 %
CSON = 17.64V, CELLS = VDD, VADJ = VREF -0.5 0.5 %
CSON = 13.23V, CELLS = GND,
VADJ = VREF
-0.5 0.5 %
CSON = 8.82V, CELLS = Float, VADJ = VREF -0.5 0.5 %
CSON = 15.96V, CELLS = VDD, VADJ = GND -0.5 0.5 %
CSON=11.97V, CELLS=GND, VADJ=GND -0.5 0.5 %
CSON = 7.98V, CELLS = Float, VADJ = GND -0.5 0.5 %
TRIP POINTS
ACSET Threshold 1.24 1.26 1.28 V
ACSET Input Bias Current Hysteresis 2.4 3.4 4.4 µA
ACSET Input Bias Current ACSET 1.26V 2.4 3.4 4.4 µA
ACSET Input Bias Current ACSET < 1.26V -1 01µA
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 7 of 25
Aug 25, 2010
OSCILLATOR
Frequency 245 300 355 kHz
PWM Ramp Voltage (peak-peak) CSIP = 18V 1.6 V
CSIP = 11V 1 V
SYNCHRONOUS BUCK REGULATOR
Maximum Duty Cycle 97 99 99.6 %
UGATE Pull-up Resistance BOOT-PHASE = 5V, 500mA source current 1.8 3.0
UGATE Source Current BOOT-PHASE = 5V, BOOT-UGATE = 2.5V 1.0 A
UGATE Pull-down Resistance BOOT-PHASE = 5V, 500mA sink current 1.0 1.8
UGATE Sink Current BOOT-PHASE = 5V, UGATE-PHASE = 2.5V 1.8 A
LGATE Pull-up Resistance VDDP-PGND = 5V, 500mA source current 1.8 3.0
LGATE Source Current VDDP-PGND = 5V, VDDP-LGATE = 2.5V 1.0 A
LGATE Pull-down Resistance VDDP-PGND = 5V, 500mA sink current 1.0 1.8
LGATE Sink Current VDDP-PGND = 5V, LGATE = 2.5V 1.8 A
Dead Time Falling UGATE to rising LGATE or
falling LGATE to rising UGATE
10 30 ns
CHARGING CURRENT SENSING AMPLIFIER
Input Common-Mode Range 018V
Input Bias Current at CSOP 5 < CSOP < 18V 0.25 2µA
Input Bias Current at CSON 5 < CSON < 18V 75 100 µA
CHLIM Input Voltage Range 03.6V
ISL6252
CSOP to CSON Full-Scale Current Sense
Voltage
ISL6252: CHLIM = 3.3V 160 165 170 mV
ISL6252: CHLIM = 2.0V 95 100 105 mV
ISL6252: CHLIM = 0.2V 5.0 10 15.0 mV
ISL6252A
CSOP to CSON Full-Scale Current Sense
Voltage
ISL6252A: CHLIM = 3.3V 161.7 165 168.3 mV
ISL6252A: CHLIM = 2.0V 97 100 103 mV
ISL6252A: CHLIM = 0.2V 7.5 10 12.5 mV
ISL6252 CSOP to CSON Full-Scale
Current Sense Voltage Formula
Charge current limit mode
0.2V < CHLIM < 3.3V
CHLIM*50
- 5
CHLIM*50
+ 5
mV
ISL6252A CSOP to CSON Full-Scale
Current Sense Voltage Formula
Charge current limit mode
0.2V < CHLIM < 3.3V
CHLIM*49.72
- 2.4
CHLIM*50.28
+ 2.4
mV
CHLIM Input Bias Current CHLIM = GND or 3.3V, DCIN = 0V -1 1 µA
CHLIM Power-down Mode Threshold
Voltage
CHLIM rising 80 88 95 mV
CHLIM Power-down Mode Hysteresis
Voltage
15 25 40 mV
ADAPTER CURRENT SENSING AMPLIFIER
Input Common-Mode Range 7 25 V
Input Bias Current at CSIP and CSIN
Combined
CSIP = CSIN = 25V 100 130 µA
Input Bias Current at CSIN 0 < CSIN < DCIN 0.10 µA
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA, TA= -10°C to +100°C,
TJ+125°C, Unless Otherwise Noted. Boldface limits apply over the operating temperature
range, -10°C to +100°C. (Continued)
PARAMETER TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 8 of 25
Aug 25, 2010
ADAPTER CURRENT LIMIT THRESHOLD
CSIP to CSIN Full-Scale Current Sense
Voltage
ACLIM = VREF 97 100 103 mV
ACLIM = Float 72 75 78 mV
ACLIM = GND 47 50 53 mV
ACLIM Input Bias Current ACLIM = VREF 10 16 20 µA
ACLIM = GND -20 -16 -10 µA
VOLTAGE REGULATION ERROR AMPLIFIER
Error Amplifier Transconductance from
CSON to VCOMP
CELLS = VDD 30 µA/V
CURRENT REGULATION ERROR AMPLIFIER
Charging Current Error Amplifier
Transconductance
50 µA/V
Adapter Current Error Amplifier
Transconductance
50 µA/V
BATTERY CELL SELECTOR
CELLS Input Voltage for 4-Cell Select 4.3 V
CELLS Input Voltage for 3-Cell Select 2V
CELLS Input Voltage for 2-Cell Select 2.1 4.2 V
LOGIC INTERFACE
EN Input Voltage Range 0VDDV
EN Threshold Voltage Rising 1.030 1.06 1.100 V
Falling 0.985 1.000 1.025 V
Hysteresis 30 60 90 mV
EN Input Bias Current EN = 2.5V 1.8 2.0 2.2 µA
ACPRN Sink Current ACPRN = 0.4V 3811 mA
ACPRN Leakage Current ACPRN = 5V -0.5 0.5 µA
ICM Output Accuracy
(VICM = 19.9 x (VCSIP - VCSIN))
CSIP-CSIN = 100mV -3 0+3 %
CSIP-CSIN = 75mV -4 0+4 %
CSIP-CSIN = 50mV -5 0+5 %
Thermal Shutdown Temperature 150 °C
Thermal Shutdown Temperature
Hysteresis
25 °C
NOTE:
7. This is the sum of currents in these pins (CSIP, CSIN, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET,
VADJ, CELLS, ACLIM, CHLIM.
8. P arameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are
established by characterization and are not production tested .
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA, TA= -10°C to +100°C,
TJ+125°C, Unless Otherwise Noted. Boldface limits apply over the operating temperature
range, -10°C to +100°C. (Continued)
PARAMETER TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 9 of 25
Aug 25, 2010
Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA= +25°C, Unless Otherwise Noted.
FIGURE 4. VDD LOAD REGULATION FIGURE 5. VREF LOAD REGULATION
FIGURE 6. ACCURACY vs AC ADAPTER CURRENT FIGURE 7. SYSTEM EFFICIENCY vs CHARGE CURRENT
FIGURE 8. AC AND DC ADAPTER DETECTION FIGURE 9. LOAD TRANSIENT RESPONSE
VDD LOAD REGULATION ACCURACY (%)
0.6
0.3
0.0
-0.3
-0.6 150 5 10 20 40
LOAD CURRENT (mA)
VREF LOAD REGULATION ACCURACY (%)
0.10
0.08
0.06
0.04
0.00 0 100 200 300 400
0.02
LOAD CURRENT (µA)
0
1
2
3
4
5
6
7
8
9
10
10 20 30 40 50 60 70 80 90 100
|ACCURACY |
(%)
CSIP-CSIN (mV)
0
LOAD CURRENT (A)
EFFICIENCY (%)
100
96
92
88
84
80
76 1.50 0.5 1.0 2.0 2.5 3.0 3.5 4.0
VCSON = 16.8V
VCSON = 8.4V
2 CELLS
VCSON = 12.6V
3 CELLS
4 CELLS
DCIN
10V/div
ACSET
1V/div
DCSET
1V/div
DCPRN
5V/div
ACPRN
5V/div
DCIN
10V/div
ACSET
1V/div
DCSET
1V/div
DCPRN
5V/div
ACPRN
5V/div
LOAD
CURRENT
5A/div
A
DAPTER
CURRENT
5A/div
CHARGE
CURRENT
2A/div
BATTERY
VOLTAGE
2V/div
LOAD STEP: 0-4A
CHARGE CURRENT: 3A
A
C ADAPTER CURRENT LIMIT: 5.15A
LOAD STEP: 0A TO 4A
CHARGE CURRENT: 3A
AC ADAPTER CURRENT LIMIT: 5.15A
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 10 of 25
Aug 25, 2010
FIGURE 10. CHARGE ENABLE AND SHUTDOWN FIGURE 11. BATTERY INSERTION AND REMOVAL
FIGURE 12. SWITCHING WAVEFORMS AT DIODE EMULATION FIGURE 13. SWITCHING WAVEFORMS IN CC MODE
FIGURE 14. AC ADAPTER REMOVAL FIGURE 15. AC ADAPTER INSERTION
Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA= +25°C, Unless Otherwise Noted. (Continued)
CSON
5V/div
EN
5V/div
INDUCTOR
CURRENT
2A/div
CHARGE
CURRENT
2A/div
CSON
5V/div
EN
5V/div
INDUCTOR
CURRENT
2A/div
CHARGE
CURRENT
2A/div
INDUCTOR
CURRENT
2A/div
CSON
10V/div
VCOMP
ICOMP
BATTERY
INSERTION
BATTERY
REMOVAL
VCOMP
2V/div
ICOMP
2V/div
INDUCTOR
CURRENT
2A/div
CSON
10V/div
VCOMP
ICOMP
BATTERY
INSERTION
BATTERY
REMOVAL
VCOMP
2V/div
ICOMP
2V/div
BATTERY
INSERTION
BATTERY
REMOVAL
VCOMP
ICOMP
PHASE
10V/div
INDUCTOR
CURRENT
1A/div
UGATE
5V/div
CHLIM=0.2V
CSON=8V
PHASE
10V/div
INDUCTOR
CURRENT
1A/div
UGATE
5V/div
PHASE
10V/div
INDUCTOR
CURRENT
1A/div
UGATE
5V/div
CHLIM=0.2V
CSON=8V
CHLIM = 0.2V
CSON = 8V
PHASE
10V/div
LGATE
2V/div
UGATE
2V/div
PHASE
10V/div
LGATE
2V/div
UGATE
2V/div
INDUCTOR
CURRENT
2A/div
BGATE-CSIP
2V/div
SYSTEM BUS
VOLTAGE
10V/div
SGATE-CSIP
2V/div
ADAPTER REMOVAL
INDUCTOR
CURRENT
2A/div
BGATE-CSIP
2V/div
SYSTEM BUS
VOLTAGE
10V/div
SGATE-CSIP
2V/div
INDUCTOR
CURRENT
2A/div
BGATE-CSIP
2V/div
SYSTEM BUS
VOLTAGE
10V/div
SGATE-CSIP
2V/div
ADAPTER REMOVAL
ADAPTER REMOVAL
INDUCTOR
CURRENT
2A/div
SGATE-CSIP
2V/div
SYSTEM BUS
VOLTAGE
10V/div
BGATE-CSIP
2V/div
ADAPTER INSERTION
INDUCTOR
CURRENT
2A/div
SGATE-CSIP
2V/div
SYSTEM BUS
VOLTAGE
10V/div
BGATE-CSIP
2V/div
INDUCTOR
CURRENT
2A/div
SGATE-CSIP
2V/div
SYSTEM BUS
VOLTAGE
10V/div
BGATE-CSIP
2V/div
ADAPTER INSERTION
ADAPTER INSERTION
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 11 of 25
Aug 25, 2010
Functional Pin Descriptions
BOOT
Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin
and connect to the cathode of the bootstrap Schottky diode.
UGATE
UGATE is the high side MOSFET gate drive output.
LGATE
LGATE is the low side MOSFET gate drive output; swing
between 0V and VDDP.
PHASE
The Phase connection pin connects to the high side MOSFET
source, output inductor, and low side MOSFET drain.
CSOP/CSON
CSOP/CSON is the battery charging current sensing
positive/negative input. The differential voltage across CSOP
and CSON is used to sense the battery charging current, and
is compared with the charging current limit threshold to
regulate the charging current. The CSON pin is also used as
the battery feedback voltage to perform voltage regulation.
CSIP/CSIN
CSIP/CSIN is the AC adapter current sensing positive/negative
input. The differential voltage across CSIP and CSIN is used to
sense the AC adapter current, and is compared with the AC
adapter current limit to regulate the AC adapter current.
GND
GND is an analog ground.
DCIN
The DCIN pin is the input of the internal 5V LDO. Connect it to
the AC adapter output. Connect a 0.1µF ceramic capacitor
from DCIN to CSON.
ACSET
ACSET is an AC adapter detection input. Connect to a resistor
divider from the AC adapter output.
ACPRN
Open-drain output signals AC adapter is present. ACPRN pulls
low when ACSET is higher than 1.26V; and pulled high when
ACSET is lower than 1.26V.
EN
EN is the Charge Enable input. Connecting EN to high enables
the charge control function, connecting EN to low disables
charging functions. Use with a thermistor to detect a hot
battery and suspend charging.
ICM
ICM is the adapter current output. The output of this pin
produces a voltage proportional to the adapter current.
PGND
PGND is the power ground. Connect PGND to the source of
the low side MOSFET.
VDD
VDD is an internal LDO output to supply IC analog circuit.
Connect a 1µF ceramic capacitor to ground.
VDDP
VDDP is the supply voltage for the low-side MOSFET gate
driver. Connect a 4.7 resistor to VDD and a 1µF ceramic
capacitor to power ground.
ICOMP
ICOMP is a current loop error amplifier output.
VCOMP
VCOMP is a voltage loop amplifier output.
CELLS
This pin is used to select the battery voltage. CELLS = VDD for
a 4S battery pack, CELLS = GND for a 3S battery pack,
CELLS = Float for a 2S battery pack.
VADJ
VADJ adjusts battery regulation voltage. VADJ = VREF for
4.2V + 5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND for
FIGURE 16. TRICKLE TO FULL-SCALE CHARGING
Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA= +25°C, Unless Otherwise Noted. (Continued)
CHLIM
1V/div
CHARGE
CURRENT
1A/div
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 12 of 25
Aug 25, 2010
4.2V - 5%/cell. Connect to a resistor divider to program the
desired battery cell voltage between 4.2V - 5% and 4.2V + 5%.
CHLIM
CHLIM is the battery charge current limit set pin. CHLIM input
voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the set
point for CSOP to CSON is 165mV. The charger shuts down if
CHLIM is forced below 88mV.
ACLIM
ACLIM is the adapter current limit set pin. ACLIM = VREF for
100mV, ACLIM = Floating for 75mV, and ACLIM = GND for
50mV. Connect a resistor divider to program the adapter
current limit threshold between 50mV and 100mV.
VREF
VREF is a 2.39V reference output pin. It is internally
compensated. Do not connect a decoupling capacitor.
Theory of Operation
Introduction
Unless otherwise noted, all descriptions of ISL6252 refer to
both ISL6252 and ISL6252A. The ISL6252 includes all of the
functions necessary to charge 2- to 4-cell Li-ion and Li-polymer
batteries. A high efficiency synchronous buck converter is used
to control the charging voltage and charging current up to 10A.
The ISL6252 has input current limiting and analog inputs for
setting the charge current and charge voltage; CHLIM inputs
are used to control charge current and VADJ inputs are used to
control charge voltage.
The ISL6252 charges the battery with constant charge current,
set by CHLIM input, until the battery voltage rises up to a
programmed charge voltage set by VADJ input; then the charger
begins to operate at a constant voltage charge mode. The
charger also drives an adapter isolation P-Channel MOSFET to
efficiently switch in the adapter supply.
ISL6252 is a complete power source selection controller for
single battery systems and also aircraft power applications. It
drives a battery selector P-Channel MOSFET to efficiently
select between a single battery and the adapter. It controls the
battery discharging MOSFET and switches to the battery when
the AC adapter is removed or switches to the AC adapter when
the AC adapter is inserted for single battery system.
The EN input allows shutdown of the charger through a
command from a micro-controller. It also uses EN to safely
shutdown the charger when the battery is in extremely hot
conditions. The amount of adapter current is reported on the
ICM output. Figure 1 shows the “IC Functional Block Diagram”
on page 3.
The synchronous buck converter uses external N-Channel
MOSFETs to convert the input voltage to the required charging
current and charging voltage. Figure 2 shows the ISL6252
typical application circuit with charging current and charging
voltage fixed at specific values. The typical application circuit
shown in Figure 3 shows the ISL6252 typical application circuit,
which uses a micro-controller to adjust the charging current set
by CHLIM input for aircraft power applications. The voltage at
CHLIM and the value of R1 sets the charging current. The
DC/DC converter generates the control signals to drive two
external N-Channel MOSFETs to regulate the voltage and
current set by the ACLIM, CHLIM, VADJ and CELLS inputs.
The ISL6252 features a voltage regulation loop (VCOMP) and
two current regulation loops (ICOMP). The VCOMP voltage
regulation loop monitors CSON to ensure that its voltage never
exceeds the voltage and regulates the battery charge voltage
set by VADJ. The ICOMP current regulation loops regulate the
battery charging current delivered to the battery to ensure that
it never exceeds the charging current limit set by CHLIM; and
the ICOMP current regulation loops also regulate the input
current drawn from the AC adapter to ensure that it never
exceeds the input current limit set by ACLIM, and to prevent a
system crash and AC adapter overload.
PWM Control
The ISL6252 employs a fixed frequency PWM current mode
control architecture with a feed-forward function. The
feed-forward function maintains a constant modulator gain of
11 to achieve fast line regulation as the buck input voltage
changes. When the battery charge voltage approaches the
input voltage, the DC/DC converter operates in dropout mode,
where there is a timer to prevent the frequency from dropping
into the audible frequency range. It can achieve duty cycle of
up to 99.6%.
To prevent boosting of the system bus voltage, the battery
charger operates in standard-buck mode when CSOP-CSON
drops below 4.25mV. Once in standard-buck mode, hysteresis
does not allow synchronous operation of the DC/DC converter
until CSOP-CSON rises above 12.5mV.
An adaptive gate drive scheme is used to control the dead time
between two switches. The dead time control circuit monitors
the LGATE output and prevents the upper side MOSFET from
turning on until LGATE is fully off, preventing cross-conduction
and shoot-through. In order for the dead time circuit to work
properly, there must be a low resistance, low inductance path
from the LGATE driver to MOSFET gate, and from the source
of MOSFET to PGND. The external Schottky diode is between
the VDDP pin and BOOT pin to keep the bootstrap capacitor
charged.
Setting the Battery Regulation Voltage
The ISL6252 uses a high-accuracy trimmed band-gap voltage
reference to regulate the battery charging voltage. The VADJ
input adjusts the charger output voltage, and the VADJ control
voltage can vary from 0 to VREF, providing a 10% adjustment
range (from 4.2V - 5% to 4.2V + 5%) on CSON regulation
voltage. An overall voltage accuracy of better than 0.5% is
achieved.
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 13 of 25
Aug 25, 2010
The per-cell battery termination voltage is a function of the
battery chemistry (consult the battery manufacturers to
determine this voltage):
• Float VADJ to set the battery voltage
VCSON =4.2V number of the cells
• Connect VADJ to VREF to set 4.41V number of cells
• Connect VADJ to ground to set 3.99V number of cells
so, the maximum battery voltage of 17.6V can be achieved. note
that other battery charge voltages can be set by connecting a
resistor divider from VREF to ground. The resistor divider should
be sized to draw no more than 100µA from VREF; or connect a
low impedance voltage source like the D/A converter in the micro-
controller. The programmed battery voltage per cell can be
determined by Equation 1:
An external resistor divider from VREF sets the voltage at
VADJ according to Equation 2:
To minimize accuracy loss due to interaction with VADJ's
internal resistor divider, ensure the AC resistance looking back
into the external resistor divider is less than 25k.
Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+ cells.
When charging other cell chemistries, use CELLS to select an
output voltage range for the charger. The internal error amplifier
gm1 maintains voltage regulation. The voltage error amplifier is
compensated at VCOMP. The component values shown in Figure
3 provide suitable performance for most applications. Individual
compensation of the voltage regulation and current-regulation
loops allows for optimal compensation.
Setting the Battery Charge Current Limit
The CHLIM input sets the maximum charging current. The
current set by the current sense-resistor connects between
CSOP and CSON. The full-scale differential voltage between
CSOP and CSON is 165mV for CHLIM = 3.3V, so the
maximum charging current is 4.125A for a 40m sensing
resistor. Other battery charge current-sense threshold values
can be set by connecting a resistor divider from VREF or 3.3V
to ground, or by connecting a low impedance voltage source
like a D/A converter in the micro-controller. Unlike VADJ and
ACLIM, CHLIM does not have an internal resistor divider
network. The charge current limit threshold is given by
Equation 3:
To set the trickle charge current for the dumb charger, an A/D
output controlled by the micro-controller is connected to
CHLIM pin. The trickle charge current is determined by
Equation 4:
When the CHLIM voltage is below 88mV (typical), it will disable
the battery charge. When choosing the current sensing
resistor, note that the voltage drop across the sensing resistor
causes further power dissipation, reducing efficiency. However,
adjusting CHLIM voltage to reduce the voltage across the
current sense resistor R1 will degrade accuracy due to the
smaller signal to the input of the current sense amplifier. There
is a trade-off between accuracy and power dissipation. A low
pass filter is recommended to eliminate switching noise.
Connect the resistor to the CSOP pin instead of the CSON pin,
as the CSOP pin has lower bias current and less influence on
current-sense accuracy and voltage regulation accuracy.
Charge Current Limit Accuracy
The “Electrical Specifications” table on page 6 gives minimum
and maximum values for the CSOP-CSON voltage resulting
from IC variations at 3 different CHLIM voltages (CSOP-CSON
Full-Scale Current Sense Voltage on page 7). It also gives
formulae for calculating the minimum and maximum CSOP-
CSON voltage at any CHLIM voltage. Equation 5 shows the
formula for the max full scale CSOP-CSON voltage (in mV) for
the ISL6252A:
TABLE 1. CELL NUMBER PROGRAMMING
CELLS CELL NUMBER
VDD 4
GND 3
Float 2
VCELL 0.175 VVADJ
3.99V+= (EQ. 1)
VVADJ VREF Rbot_VADJ 514k
Rtop_VADJ 514k
Rbot_VADJ 514k
+
-----------------------------------------------------------------------------------------------------------------
=
(EQ. 2)
ICHG 165mV
R1
-------------------
VCHLIM
3.3V
----------------------
=(EQ. 3)
ICHG 165mV
R1
-------------------
VCHLIM trickle,
3.3V
----------------------------------------
=(EQ. 4)
ISL6252A
CSOP CSON–
MAX CHLIM 50.28 2.4+=
CSOP CSON–
MIN CHLIM 49.72 2.4–=(EQ. 5)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 14 of 25
Aug 25, 2010
Equation 5 shows the formula for the max full scale
CSOP-CSON voltage (in mV) for the ISL6252:
With CHLIM = 1.5V, the maximum CSOP-CSON voltage is
78mV and the minimum CSOP-CSON voltage is 72mV.
When ISL6252A is in charge current limiting mode, the
maximum charge current is the maximum CSOP-CSON
voltage divided by the minimum sense resistor. This can be
calculated for ISL6252A with Equation 7:
Maximum charge current can be calculated for ISL6252 with
Equation 8:
With CHLIM = 0.7V and R1 = 0.02, 1%:
Setting the Input Current Limit
The total input current from an AC adapter, or other DC source,
is a function of the system supply current and the battery-
charging current. The input current regulator limits the input
current by reducing the charging current, when the input
current exceeds the input current limit set point. System
current normally fluctuates as portions of the system are
powered up or down. Without input current regulation, the
source must be able to supply the maximum system current
and the maximum charger input current simultaneously. By
using the input current limiter, the current capability of the AC
adapter can be lowered, reducing system cost.
The ISL6252 limits the battery charge current when the input
current-limit threshold is exceeded, ensuring the battery
charger does not load down the AC adapter voltage. This
constant input current regulation allows the adapter to fully
power the system and prevent the AC adapter from
overloading and crashing the system bus.
An internal amplifier gm3 compares the voltage between CSIP
and CSIN to the input current limit threshold voltage set by
ACLIM. Connect ACLIM to REF, Float and GND for the full-
scale input current limit threshold voltage of 100mV, 75mV and
50mV, respectively, or use a resistor divider from VREF to
ground to set the input current limit as Equation 10:
An external resistor divider from VREF sets the voltage at
ACLIM according to Equation 11:
where Rbot_ACLIM and Rtop_ACLIM are external resistors at
ACLIM.
To minimize accuracy loss due to interaction with ACLIM's
internal resistor divider, ensure the AC resistance looking back
into the resistor divider is less than 25k.
When choosing the current sense resistor, note that the
voltage drop across this resistor causes further power
dissipation, reducing efficiency. The AC adapter current sense
accuracy is very important. Use a 1% tolerance current-sense
resistor. The highest accuracy of ±3% is achieved with 100mV
current-sense threshold voltage for ACLIM = VREF, but it has
the highest power dissipation. For example, it has 400mW
power dissipation for rated 4A AC adapter and 1 sensing
resistor may have to be used. ±4% and ±6% accuracy can be
achieved with 75mV and 50mV current-sense threshold
voltage for ACLIM = Floating and ACLIM = GND, respectively.
A low pass filter is suggested to eliminate the switching noise.
Connect the resistor to CSIN pin instead of CSIP pin because
CSIN pin has lower bias current and less influence on the
current-sense accuracy.
AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to
ACSET to detect when AC power is available, as shown in
Figure 2. ACPRN is an open-drain output and is high when
ACSET is less than Vth,rise, and active low when ACSET is
above Vth,fall. Vth,rise and Vth,fall are given by Equation 12 and
Equation 13:
where:
•I
hys is the ACSET input bias current hysteresis, and
•V
ACSET = 1.24V (min), 1.26V (typ) and 1.28V (max).
The hysteresis is IhysR8, where Ihys = 2.2µA (min), 3.4µA (typ)
and 4.4µA (max).
ISL6252
MAX CSOP CSON–CHLIM 50 5+=
MIN CSOP CSON–CHLIM 50 5–=(EQ. 6)
ISL6252A
ICHG MAXCHLIM 50.28 2.4+R1MIN
=
ICHG MINCHLIM 49.72 2.4–R1MAX
=(EQ. 7)
ISL6252
ICHG MAXCHLIM 50 5+R1MIN
=
ICHG MINCHLIM 50 5–R1MAX
=(EQ. 8)
ISL6252A
ICHG MAX1.5V 50.28 2.4+0.0198 3930mA==
ICHG MIN1.5V 49.72 2.4–0.0202 3573mA==(EQ. 9)
IINPUT
1
R2
-------0.05
VREF
-----------------VACLIM 0.05+
=(EQ. 10)
VACLIM VREF
Rbot ACLIM152k
Rtop ACLIM152k
Rbot ACLIM152k
+
------------------------------------------------------------------------------------------------------------------------
=
(EQ. 11)
Vth rise
R8
R9
-------1+
VACSET
=(EQ. 12)
Vth fall
R8
R9
-------1+
VACSET Ihys R8
–=(EQ. 13)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 15 of 25
Aug 25, 2010
Current Measurement
Use ICM to monitor the input current being sensed across
CSIP and CSIN. The output voltage range is 0V to 2.5V. The
voltage of ICM is proportional to the voltage drop across CSIP
and CSIN, and is given by Equation 14:
where IINPUT is the DC current drawn from the AC adapter.
ICM has ±3% accuracy. It is recommended to have an RC filter
at the ICM output for minimizing the switching noise.
LDO Regulator
VDD provides a 5.0V supply voltage from the internal LDO
regulator from DCIN and can deliver up to 30mA of current.
The MOSFET drivers are powered by VDDP, which must be
connected to VDDP as shown in Figure 2. VDDP connects to
VDD through an external low pass filter. Bypass VDDP and
VDD with a 1µF capacitor.
Shutdown
The ISL6252 features a low-power shutdown mode. Driving
EN low shuts down the ISL6252. In shutdown, the DC/DC
converter is disabled, and VCOMP and ICOMP are pulled to
ground. The ICM, ACPRN output continue to function.
EN can be driven by a thermistor to allow automatic shutdown
of the ISL6252 when the battery pack is hot. Often a NTC
thermistor is included inside the battery pack to measure its
temperature. When connected to the charger, the thermistor
forms a voltage divider with a resistive pull-up to the VREF.
The threshold voltage of EN is 1.0V with 60mV hysteresis. The
thermistor can be selected to have a resistance vs temperature
characteristic that abruptly decreases above a critical
temperature. This arrangement automatically shuts down the
ISL6252 when the battery pack is above a critical temperature.
Another method for inhibiting charging is to force CHLIM below
85mV (typ).
Short Circuit Protection and 0V Battery Charging
Since the battery charger will regulate the charge current to the
limit set by CHLIM, it automatically has short circuit protection
and is able to provide the charge current to wake up an
extremely discharged battery.
Over-Temper ature Protection
If the die temp exceeds +150°C, it stops charging. Once the
die temp drops below +125°C, charging will start up again.
Overvoltage Protection
ISL6252 has an Overvoltage Protection circuit that limits the
output voltage when the battery is removed or disconnected by
a pulse charging circuit. If CSON exceeds the output voltage
set point by more than VOVP an internal comparator pulls
VCOMP down and turns off both upper and lower FETs of the
buck, as in Figure 17. The trip point for Overvoltage Protection
is always above the nominal output voltage and can be
calculated from Equation 15:
F
or example, if the CELLS pin is connected to ground
(NCELLS = 3) and VADJ is floating (VADJ = 1.195V) then
VOUT,NOM = 12.6V and VOVP = 12.693V or
VOUT,NOM +93mV.
There is a delay of approximately 400nsec between VOUT
exceeding the OVP trip point and pulling VCOMP, LGATE and
UGATE low.
During normal operation with cells installed, the CSON pin
voltage will be the cell stack voltage. When EN is low and the
cells are removed, this voltage may drop below 100mV. Due to
non-linearities in the OVP comparator at this low input level,
the VCOMP pin may be held low even after EN is commanded
high. If regulation is required in the absence of cells then a
series resistor and diode need to be installed which inject
current into the CSON pin from the VDD pin. See R23 and D5
in Figure 3. This will maintain the CSON pin voltage well within
its linear range in the absence of cells, and will be effectively
out of the circuit when the diode is reversed biased by the cell
stack. Resistor values from 10k to 100k have been found to be
effective.
Application Information
The following battery charger design refers to the typical
application circuit in Figure 2, where typical battery
configuration of 4S2P is used. This section describes how to
select the external components including the inductor, input
and output capacitors, switching MOSFETs, and current
sensing resistors.
ICM 19.9 IINPUT R2
=(EQ. 14)
VOVP VOUT NOMNCELLS 42.2mV 22.2mV
VADJ
2.39V
----------------
–
+=
(EQ. 15)
FIGURE 17. OVERVOLTAGE PROTECTION IN ISL6252
BATTERY
REMOVAL
WHEN VOUT EXCEEDS
THE OVP THRESHOLD
VCOMP IS PULLED LOW
AND FETS TURN OFF
VCOMP
ICOMP
VOUT
PHASE
CURRENT FLOWS IN THE
LOWER FET BODY DIODE
UNTIL INDUCTOR CURRENT
REACHES ZERO
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 16 of 25
Aug 25, 2010
Inductor Selection
The inductor selection has trade-offs between cost, size,
crossover frequency and efficiency. For example, the lower the
inductance, the smaller the size, but ripple current is higher.
This also results in higher AC losses in the magnetic core and
the windings, which decrease the system efficiency. On the
other hand, the higher inductance results in lower ripple current
and smaller output filter capacitors, but it has higher DCR (DC
resistance of the inductor) loss, lower saturation current and
has slower transient response. So, the practical inductor
design is based on the inductor ripple current being ±15% to
±20% of the maximum operating DC current at maximum input
voltage. Maximum ripple is at 50% duty cycle or
VBAT =V
IN,MAX/2. The required inductance can be calculated
from Equation 16:
Where VIN,MAX and fSW are the maximum input voltage, and
switching frequency, respectively.
The inductor ripple current I is found from Equation 17:
where the maximum peak-to-peak ripple current is 30% of the
maximum charge current is used.
For VIN,MAX = 19V, VBAT = 16.8V, IBAT,MAX = 2.6A, and
fs= 300kHz, the calculated inductance is 8.3µH. Choosing the
closest standard value gives L = 10µH. Ferrite cores are often
the best choice since they are optimized at 300kHz to 600kHz
operation with low core loss. The core must be large enough
not to saturate at the peak inductor current IPeak in
Equation 18:
Inductor saturation can lead to cascade failures due to very
high currents. Conservative design limits the peak and RMS
current in the inductor to less than 90% of the rated saturation
current.
Crossover frequency is heavily dependent on the inductor
value. fCO should be less than 20% of the switching frequency
and a conservative design has fCO less than 10% of the
switching frequency. The highest fCO is in voltage control
mode with the battery removed and may be calculated
(approximately) from Equation 19:
Output Capacitor Select ion
The output capacitor in parallel with the battery is used to
absorb the high frequency switching ripple current and smooth
the output voltage. The RMS value of the output ripple current
IRMS is given by Equation 20:
where the duty cycle D is the ratio of the output voltage (battery
voltage) over the input voltage for continuous conduction mode
which is typical operation for the battery charger. During the
battery charge period, the output voltage varies from its initial
battery voltage to the rated battery voltage. So, the duty cycle
change can be in the range of between 0.53 and 0.88 for the
minimum battery voltage of 10V (2.5V/Cell) and the maximum
battery voltage of 16.8V. The maximum RMS value of the
output ripple current occurs at the duty cycle of 0.5 and is
expressed as Equation 21:
For VIN,MAX = 19V, VBAT = 16.8V, L = 10µH, and fs= 300kHz,
the maximum RMS current is 0.19A. A typical 10F ceramic
capacitor is a good choice to absorb this current and also has
very small size. Organic polymer capacitors have high
capacitance with small size and have a significant equivalent
series resistance (ESR). Although ESR adds to ripple voltage,
it also creates a high frequency zero that helps the closed loop
operation of the buck regulator.
EMI considerations usually make it desirable to minimize ripple
current in the battery leads. Beads may be added in series with
the battery pack to increase the battery impedance at 300kHz
switching frequency. Switching ripple current splits between
the battery and the output capacitor depending on the ESR of
the output capacitor and battery impedance. If the ESR of the
output capacitor is 10m and battery impedance is raised to
2 with a bead, then only 0.5% of the ripple current will flow in
the battery.
MOSFET Selection
The Notebook battery charger synchronous buck converter
has the input voltage from the AC adapter output. The
maximum AC adapter output voltage does not exceed 25V.
Therefore, 30V logic MOSFET should be used.
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous buck
converter is equal to the AC adapter output voltage, which is
relatively constant. The maximum efficiency is achieved by
selecting a high side MOSFET that has the conduction losses
equal to the switching losses. Switching losses in the low-side
FET are very small. The choice of low-side FET is a trade-off
between conduction losses (rDS(ON)) and cost. A good rule of
thumb for the rDS(ON) of the low-side FET is 2x the rDS(ON) of
the high-side FET.
L
VIN MAX
4f
SW IRIPPLE
---------------------------------------------
=(EQ. 16)
IRIPPLE 0.3 ILMAX
=(EQ. 17)
IPEAK ILMAX1
2
---
+IRIPPLE
=(EQ. 18)
fCO
511R
SENSE
2L
-------------------------------------------
=(EQ. 19)
IRMS
VIN MAX
12LF
SW
----------------------------------- D1D–=(EQ. 20)
IRMS
VIN MAX
4 12Lf
SW
-----------------------------------------
=(EQ. 21)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 17 of 25
Aug 25, 2010
The LGATE gate driver can drive sufficient gate current to
switch most MOSFETs efficiently. However, some FETs may
exhibit cross conduction (or shoot through) due to current
injected into the drain-to-source parasitic capacitor (Cgd) by
the high dV/dt rising edge at the phase node when the
high-side MOSFET turns on. Although LGATE sink current
(1.8A typical) is more than enough to switch the FET off
quickly, voltage drops across parasitic impedances between
LGATE and the MOSFET can allow the gate to rise during the
fast rising edge of voltage on the drain. MOSFETs with low
threshold voltage (<1.5V) and low ratio of Cgs/Cgd (<5) and
high gate resistance (>4) may be turned on for a few ns by
the high dV/dt (rising edge) on their drain. This can be avoided
with higher threshold voltage and Cgs/Cgd ratio. Another way
to avoid cross conduction is slowing the turn-on speed of the
high-side MOSFET by connecting a resistor between the
BOOT pin and the boot strap capacitor.
For the high-side MOSFET, the worst-case conduction losses
occur at the minimum input voltage as shown in Equation 22:
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to calculate
the switching losses in the high-side MOSFET since it must
allow for difficult-to-quantify factors that influence the turn-on
and turn-off times. These factors include the MOSFET internal
gate resistance, gate charge, threshold voltage, stray
inductance, pull-up and pull-down resistance of the gate driver.
The following switching loss calculation (Equation 23) provides
a rough estimate.
where the following are the peak gate-drive source/sink current
of Q1, respectively:
•Q
gd: drain-to-gate charge
•Q
rr: total reverse recovery charge of the body-diode in
low-side MOSFET
•I
LV: inductor valley current
•I
LP: Inductor peak current
•I
g,sink
•I
g,source
Low switching loss requires low drain-to-gate charge Qgd.
Generally, the lower the drain-to-gate charge, the higher the
ON-resistance. Therefore, there is a trade-off between the ON-
resistance and drain-to-gate charge. Good MOSFET selection
is based on the Figure of Merit (FOM), which is a product of the
total gate charge and ON-resistance. Usually, the smaller the
value of FOM, the higher the efficiency for the same
application.
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input voltage
(Equation 24):
Choose a low-side MOSFET that has the lowest possible ON-
resistance with a moderate-sized package (like the SO-8) and
is reasonably priced. The switching losses are not an issue for
the low-side MOSFET because it operates at zero-voltage-
switching.
Choose a Schottky diode in parallel with low-side MOSFET Q2
with a forward voltage drop low enough to prevent the low-side
MOSFET Q2 body-diode from turning on during the dead time.
This also reduces the power loss in the high-side MOSFET
associated with the reverse recovery of the low-side MOSFET
Q2 body diode.
As a general rule, select a diode with DC current rating equal
to one-third of the load current. One option is to choose a
combined MOSFET with the Schottky diode in a single
package. The integrated packages may work better in practice
because there is less stray inductance due to a short
connection. This Schottky diode is optional and may be
removed if efficiency loss can be tolerated. In addition, ensure
that the required total gate drive current for the selected
MOSFETs is less than 24mA. So, the total gate charge for the
high-side and low-side MOSFETs is limited by Equation 25:
Where IGATE is the total gate drive current and should be less
than 24mA. Substituting IGATE = 24mA and fs= 300kHz into
Equation 25 yields that the total gate charge should be less
than 80nC. Therefore, the ISL6252 easily drives the battery
charge current up to 10A.
Snubber Design
ISL6252's buck regulator operates in discontinuous current
mode (DCM) when the load current is less than half the
peak-to-peak current in the inductor. After the low-side FET
turns off, the phase voltage rings due to the high impedance
with both FETs off. This can be seen in Figure 9. Adding a
snubber (resistor in series with a capacitor) from the phase
node to ground can greatly reduce the ringing. In some
situations a snubber can improve output ripple and regulation.
The snubber capacitor should be approximately twice the
parasitic capacitance on the phase node. This can be
estimated by operating at very low load current (100mA) and
measuring the ringing frequency.
PQ1 conduction
VOUT
VIN
----------------IBAT
2rDS ON
=(EQ. 22)
Q1 Switching
VINILVfsw
Qgd
Igsource
-------------------------
1
2
---VINILPfsw
Qgd
Igksin
-----------------
QrrVINfsw
++
=
(EQ. 23)
PQ2 1
VOUT
VIN
----------------
–
IBAT
2rDS ON
=(EQ. 24)
QGATE
1GATE
fsw
-------------------
(EQ. 25)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 18 of 25
Aug 25, 2010
CSNUB and RSNUB can be calculated from Equations 26 and
27:
Input Capacitor Selection
The input capacitor absorbs the ripple current from the
synchronous buck converter, which is given by Equation 28:
This RMS ripple current must be smaller than the rated RMS
current in the capacitor datasheet. Non-tantalum chemistries
(ceramic, aluminum, or OSCON) are preferred due to their
resistance to power-up surge currents when the AC adapter is
plugged into the battery charger. For Notebook battery charger
applications, it is recommended that ceramic capacitors or
polymer capacitors from Sanyo be used due to their small size
and reasonable cost.
Table 2 shows the component lists for the typical application
circuit in Figure 2.
Loop Compensation Design
ISL6252 has three closed loop control modes. One controls
the output voltage when the battery is fully charged or absent.
A second controls the current into the battery when charging
and the third limits current drawn from the adapter. The charge
current and input current control loops are compensated by a
single capacitor on the ICOMP pin. The voltage control loop is
compensated by a network on the VCOMP pin. Descriptions of
these control loops and guidelines for selecting compensation
components will be given in the following sections. Which loop
controls the output is determined by the minimum current
buffer and the minimum voltage buffer shown in Figure 1.
These three loops will be described separately.
TRANSCONDUCTANCE AMPLIFIERS GM1, GM2 AND GM3
The ISL6252 uses several transconductance amplifiers (also
known as gm amps). Most commercially available op amps are
voltage controlled voltage sources with gain expressed as
A=V
OUT/VIN. Transconductance amps are voltage controlled
current sources with gain expressed as gm = IOUT/VIN.
Transconductance gain (gm) will appear in some of the
equations for poles and zeros in the compensation.
PWM GAIN FM
The Pulse Width Modulator in the ISL6252 converts voltage at
VCOMP to a duty cycle by comparing VCOMP to a triangle
wave (duty = VCOMP/VP-P RAMP). The low-pass filter formed
by L and CO convert the duty cycle to a DC output voltage
(Vo = VDCIN*duty). In ISL6252, the triangle wave amplitude is
proportional to VDCIN. Making the ramp amplitude proportional
to DCIN makes the gain from VCOMP to the PHASE output a
constant 11 and is independent of DCIN. For small signal AC
analysis, the battery is modeled by it’s internal resistance. The
total output resistance is the sum of the sense resistor and the
internal resistance of the MOSFETs, inductor and capacitor.
Figure 18 shows the small signal model of the pulse width
modulator (PWM), power stage, output filter and battery.
TABLE 2. COMPONENT LIST
PARTS PART NUMBERS AND MANUFACTURER
C1, C10 10µF/25V ceramic capacitor, Taiyo Yuden
TMK325 MJ106MY X5R (3.2mmx2.5mmx1.9mm)
C2, C4, C80.1µF/50V ceramic capacitor
C3, C7, C91µF/10V ceramic capacitor, Taiyo Yuden
LMK212BJ105MG
C510nF ceramic capacitor
C66.8nF ceramic capacitor
C11 3300pF ceramic capacitor
D130V/3A Schottky diode, EC31QS03L (optional)
D2100mA/30V Schottky Diode, Central Semiconductor
L 10µH/3.8A/26m, Sumida, CDRH104R-100
Q1, Q230V/35m, FDS6912A, Fairchild
Q6Signal N-Channel MOSFET, 2N7002
R140m, ±1%, LRC-LR2512-01-R040-F, IRC
R220m, ±1%, LRC-LR2010-01-R020-F, IRC
R318, ±5%, (0805)
R42.2, ±5%, (0805)
R5100k, ±5%, (0805)
R64.7k, ±5%, (0805)
R7100, ±5%, (0805)
R8, R11 130k, ±1%, (0805)
CSNUB
2
2Fring
2L
-------------------------------------
=(EQ. 26)
RSNUB
2L
CSNUB
--------------------= (EQ. 27)
IRMS IBAT
VOUT VIN VOUT
–
VIN
-------------------------------------------------------------
=(EQ. 28)
R910.2k, ±1%, (0805)
R10 4.7, ±5%, (0805)
R12 20k, ±1%, (0805)
R13 1.87k, ±1%, (0805)
TABLE 2. COMPONENT LIST (Continued)
PARTS PART NUMBERS AND MANUFACTURER
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 19 of 25
Aug 25, 2010
In most cases the Battery resistance is very small (<200m)
resulting in a very low Q in the output filter. This results in a
frequency response from the input of the PWM to the inductor
current with a single pole at the frequency calculated in
Equation 29:
The output capacitor creates a pole at a very high frequency
due to the small resistance in parallel with it. The frequency of
this pole is calculated in Equation 30:
CHARGE CURRENT CONTROL LOOP
When the battery voltage is less than the fully charged voltage,
the voltage error amplifier goes to it’s maximum output (limited
to 1.2V above ICOMP) and the ICOMP voltage controls the
loop through the minimum voltage buffer. Figure 19 shows the
charge current control loop.
The compensation capacitor (CICOMP) gives the error amplifier
(GMI) a pole at a very low frequency (<<1Hz) and a a zero at
fZ1. fZ1 is created by the 0.25*CA2 output added to ICOMP. The
frequency of can be calculated from
Equation 31:
Placing this zero at a frequency equal to the pole calculated in
Equation 29 will result in maximum gain at low frequencies and
phase margin near 90°. If the zero is at a higher frequency
(smaller CICOMP), the DC gain will be higher but the phase
margin will be lower. Use a capacitor on ICOMP that is equal to
or greater than the value calculated in Equation 32:
A filter should be added between RS2 and CSOP and CSON to
reduce switching noise. The filter roll off frequency should be
between the crossover frequency and the switching frequency
(~100kHz). RF2 should be small (<10 to minimize offsets due
to leakage current into CSOP. The filter cut-off frequency is
calculated using Equation 33:
The crossover frequency is determined by the DC gain of the
modulator and output filter and the pole in Equation 29. The
DC gain is calculated in Equation 34 and the crossover
frequency is calculated with Equation 35.
FIGURE 18. SMALL SIGNAL AC MODEL
DRIVERS
RAMP GEN
VRAMP = VDD/11
VDD
-
+
11
PWM
INPUT
L
CO
L
RESR
CO
RSENSE
RBAT
RFET_rDS(ON)
PWM
INPUT
RL_DCR
PWM
GAIN = 11
fPOLE1
RSENSE rDS ON
RDCR RBAT
+++
2L
-------------------------------------------------------------------------------------------------------
=(EQ. 29)
fPOLE2
1
2CoRBAT
---------------------------------------
=(EQ. 30)
FIGURE 19. CHARGE CURRENT LIMIT LOOP
RS2
RBAT
ICOMP
CSON
PHASE
RESR
CO
11
+
-
CA2
20
CSOP
S
+
-
0.25
CHLIM
-
+
+
-
gm2
CF2
RF2
CICOMP
L
RFET_rDS(ON) RL_DCR
fZERO
4gm2
2CICOMP
---------------------------------------
=(EQ. 31)
gm2 50A
V
---------------
=
CICOMP
450AV
RS2 rDS ON
RDCR RBAT
+++
------------------------------------------------------------------------------------------
=(EQ. 32)
fFILTER
1
2CF2 RF2
-------------------------------------------
=(EQ. 33)
ADC
11 RS2
RS2 rDS ON
RDCR RBATTERY
+++
----------------------------------------------------------------------------------------------------------
=(EQ. 34)
fCO ADC fPOLE1
11 RS2
2L
----------------------
== (EQ. 35)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 20 of 25
Aug 25, 2010
The Bode plot of the loop gain, the compensator gain and the
power stage gain is shown in Figure 20:
Adapter Current Limit Control Loop
If the combined battery charge current and system load current
draws current that equals the adapter current limit set by the
ACLIM pin, ISL6252 will reduce the current to the battery
and/or reduce the output voltage to hold the adapter current at
the limit. Above the adapter current limit, the minimum current
buffer equals the output of gm3 and ICOMP controls the
charger output. Figure 21 shows the adapter current limit
control loop.
.
The loop response equations, Bode plots and the selection of
CICOMP are the same as the charge current control loop with
loop gain reduced by the duty cycle and the ratio of RS1/RS2.
In other words, if RS1= RS2 and the duty cycle D = 50%, the
loop gain will be 6dB lower than the loop gain in Figure 20.
This gives lower crossover frequency and higher phase margin
in this mode. If RS1/RS2 = 2 and the duty cycle is 50% then the
adapter current loop gain will be identical to the gain in Figure
20.
A filter should be added between RS1 and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the crossover frequency and the switching frequency
(~100kHz).
Voltage Control Loop
When the battery is charged to the voltage set by CELLS and
VADJ the voltage error amplifier (gm1) takes control of the
output (assuming that the adapter current is below the limit set
by ACLIM). The voltage error amplifier (gm1) discharges the
capacitor on VCOMP to limit the output voltage. The current to
the battery decreases as the cells charge to the fixed voltage
and the voltage across the internal battery resistance
decreases. As battery current decreases the 2 current error
amplifiers (gm2 and gm3) output their maximum current and
charge the capacitor on ICOMP to its maximum voltage (limited
to 1.2V above VCOMP). With high voltage on ICOMP, the
minimum voltage buffer output equals the voltage on VCOMP.
The voltage control loop is shown in Figure 22.
.
Output LC Filter Transfer Functions
The gain from the phase node to the system output and battery
depend entirely on external components. Typical output LC
filter response is shown in Figure 23. Transfer function ALC(s)
is shown in Equation 36:
-60
-40
-20
0
20
40
60
0.01k 0.1k 1k 10k 100k 1M
FREQUENCY (Hz)
GAIN (dB)
COMPENSATOR
MODULATOR
LOOP
fZERO
fPOLE1
fFILTER
fPOLE2
FIGURE 20. CHARGE CURRENT LOOP BODE PLOTS
CICOMP
ICOMP
PHASE
11
+
-
0.25
ACLIM
-
+
+
-
gm3
RS1
DCIN
CSIN
+
-
CA1
20
CSIP
CF1
RF1
R
CSON
+
-
CA2
20
CSOP
CF2
RF2
RESR
CO
L
RFET_rDS(ON) RL_DCR
FIGURE 21. ADAPTER CURRENT LIMIT LOOP
FIGURE 22. VOLTAGE CONTROL LOOP
VCOMP
CSON
PHASE
11
CSOP+
-
0.25
-
+
+
-
gm1
CVCOMP
RVCOMP 2.1V
R3
R4
+
-
CA2
20 RS2
RBAT
RESR
CO
CF2
RF2
L
RFET_rDS(ON)
RL_DCR
ALC
1s
ESR
---------------
–
s2
DP
------------s
LC Q
-------------------------1++
-----------------------------------------------------------
=(EQ. 36)
ESR
1
RESR Co
---------------------------------
=LC
1
LC
o
------------------------
=QR
o
L
Co
-------=
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 21 of 25
Aug 25, 2010
The resistance RO is a combination of MOSFET rDS(ON),
inductor DCR, RSENSE and the internal resistance of the
battery (normally between 50m and 200m). The worst case
for voltage mode control is when the battery is absent. This
results in the highest Q of the LC filter and the lowest phase
margin.
The compensation network consists of the voltage error
amplifier gm1 and the compensation network RVCOMP
,
CVCOMP
, which give the loop very high DC gain, a very low
frequency pole and a zero at fZERO1. Inductor current
information is added to the feedback to create a second zero,
fZERO2. The low pass filter RF2, CF2 between RSENSE and
ISL6252 add a pole at fFILTER. R3 and R4 are internal divider
resistors that set the DC output voltage. For a 3-cell battery,
R3= 320k and R4=64k. Equations 37, 38, 39, 40, 41 and
42 relate the compensation network’s poles, zeros and gain to
the components in Figure 22. Figure 24 shows an asymptotic
Bode plot of the DC/DC converter’s gain vs frequency. It is
strongly recommended that fZERO1 is approximately 30% of
fLC and fZERO2 is approximately 70% of fLC.
COMPENSATION BREAK FREQUENCY EQUATIONS
FIGURE 23. FREQUENCY RESPONSE OF THE LC OUTPUT
FILTER
PHASE (°) GAIN (dB)
FREQUENCY
-60
-50
-40
-30
-20
-10
0
10
20
100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 500k
-160
-140
-120
-100
-80
-60
-40
-20
NO BATTERY
RBATTERY = 50m
RBATTERY = 200m
-60
-40
-20
0
20
40
0.1k 1k 10k 100k 1M
FREQUENCY (Hz)
GAIN (dB)
COMPENSATOR
MODULATOR
LOOP
fLC fPOLE1
fZERO1 fZERO2
FESR
fFILTER
FIGURE 24. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
CONTROL LOOP GAIN
fZERO1
1
2CVCOMP R1COMP
-----------------------------------------------------------------------
=(EQ. 37)
fZERO2
RVCOMP
2RSENSE COUT
--------------------------------------------------------
R4
R4R3
+
---------------------
gm1
5
------------
=(EQ. 38)
fLC
1
2LC
o
-------------------------------
=(EQ. 39)
fFILTER
1
2RF2 CF2
-------------------------------------------
=(EQ. 40)
fPOLE1
1
2RSENSE Co
----------------------------------------------------
=(EQ. 41)
fESR
1
2CoRESR
--------------------------------------------
=(EQ. 42)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 22 of 25
Aug 25, 2010
Choose RVCOMP equal or lower than the value calculated from
Equation 43:
Next, choose CVCOMP equal or higher than the value
calculated from Equation 44:
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with signal layers on the
opposite side of the board. As an example, layer arrangement
on a 4-layer board is shown in the following:
1. Top Layer: signal lines, or half board for signal lines and the
other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other Power
traces
Separate the power voltage and current flowing path from the
control and logic level signal path. The controller IC will stay on
the signal layer, which is isolated by the signal ground to the
power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the gate
drive signal, the LGATE, UGATE, PHASE, and BOOT, traces
can be short.
Place the components in such a way that the area under the IC
has less noise traces with high dv/dt and di/dt, such as gate
signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used as
signal ground beneath the IC. The best tie-point between the
signal ground and the power ground is at the negative side of
the output capacitor on each side, where there is little noise; a
noisy trace beneath the IC is not recommended.
GND and VDD Pin
At least one high quality ceramic decoupling capacitor should
be used to cross these two pins. The decoupling capacitor can
be put close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND Pin
PGND pin should be laid out to the negative side of the
relevant output capacitor with separate traces.The negative
side of the output capacitor must be close to the source node
of the bottom MOSFET. This trace is the return path of LGATE.
PHASE Pin
This trace should be short, and positioned away from other
weak signal traces. This node has a very high dv/dt with a
voltage swing from the input voltage to ground. No trace
should be in parallel with it. This trace is also the return path for
UGATE. Connect this pin to the high-side MOSFET source.
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the top
MOSFET with high di/dt. This trace should be wide, short, and
away from other traces similar to the LGATE.
BOOT Pin
This pin’s di/dt is as high as the UGATE; therefore, this trace
should be as short as possible.
CSOP, CSON, CSIP and CSIN Pins
Accurate charge current and adapter current sensing is critical
for good performance. The current sense resistor connects to
the CSON and the CSOP pins through a low pass filter with the
filter capacitor very near the IC (see Figure 2). Traces from the
sense resistor should start at the pads of the sense resistor
and should be routed close together, throughout the low pass
filter and to the CSON and CSON pins (see Figure 25). The
CSON pin is also used as the battery voltage feedback. The
traces should be routed away from the high dv/dt and di/dt pins
like PHASE, BOOT pins. In general, the current sense resistor
should be close to the IC. These guidelines should also be
followed for the adapter current sense resistor and CSIP and
CSIN. Other layout arrangements should be adjusted
accordingly.
TABLE 3.
CELLS R3R4
2 288k48k
3 320k64k
4 336k96k
RVCOMP 0.7 fLC
2CoRSENSE
5
gm1
------------
R3R4
+
R4
---------------------
=
(EQ. 43)
CVCOMP
1
0.3 fLC
2RVCOMP
-------------------------------------------------------------------------
=(EQ. 44)
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 23 of 25
Aug 25, 2010
.
EN Pin
This pin stays high at enable mode and low at idle mode and is
relatively robust. Enable signals should refer to the signal
ground.
DCIN Pin
This pin connects to AC adapter output voltage, and should be
less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to
minimize ringing. It would be best to limit the size of the
PHASE node copper in strict accordance with the current and
thermal management of the application.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should
connect to the power ground. The other components should
connect to signal ground. Signal and power ground are tied
together at one point.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic capacitors be used closely
connected to the drain of the high-side MOSFET, and the
source of the low-side MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET.
HIGH
CURRENT
TRACE
HIGH
CURRENT
TRACE
KELVIN CONNECTION TRACES
TO THE LOW PASS FILTER
AND
CSOP AND CSON
SENSE
RESISTOR
FIGURE 25. CURRENT SENSE RESISTOR LAYOUT
RESISTOR
ISL6252, ISL6252A
FN6498 Rev 3.00 Page 24 of 25
Aug 25, 2010
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
BOTTOM VIEW
SIDE VIEW
5.00 A
5.00
B
INDEX AREA
PIN 1
6
(4X) 0.15
28X 0.55 ± 0.10 4
A
28X 0.25
M0.10 C B
14 8
4X
0.50
24X
3.0
6
PIN #1 INDEX AREA
3 .10 ± 0 . 15
0 . 90 ± 0.1
BASE PLANE
SEE DETAIL "X"
SEATING PLANE
0.10 C
C
0.08 C
0 . 2 REF
C
0 . 05 MAX.
0 . 00 MIN.
5
( 3. 10)
( 4. 65 TYP )
( 24X 0 . 50)
(28X 0 . 25 )
( 28X 0 . 75)
15
22
21
7
1
28
+ 0.05
- 0.07
FN6498 Rev 3.00 Page 25 of 25
Aug 25, 2010
ISL6252, ISL6252A
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
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modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Parameters with MIN and/or MAX limits are 100% tested
at +25°C, un less otherwise specified. Temperature
limits established by characterization and are not
production tested.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
INDEX
AREA
E
D
N
123
-B-
0.17(0.007) C AMBS
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
M24.15
24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
A2 - 0.061 - 1.54 -
B 0.008 0.012 0.20 0.30 9
C 0.007 0.010 0.18 0.25 -
D 0.337 0.344 8.55 8.74 3
E 0.150 0.157 3.81 3.98 4
e 0.025 BSC 0.635 BSC -
H 0.228 0.244 5.80 6.19 -
h 0.0099 0.0196 0.26 0.49 5
L 0.016 0.050 0.41 1.27 6
N24 247
0° 8° 0° 8° -
Rev. 2 6/04
