DATA SH EET
Product specification
Supersedes data of 2002 Oct 02 2003 Dec 08
INTEGRATED CIRCUITS
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
2003 Dec 08 2
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
FEATURES
•5 V tolerant inputs/outputs for interfacing with 5 V logic
•Wide supply voltage range from 1.2 to 3.6 V
•CMOS low power consumption
•MULTIBYTE flow-through standard pin-out architecture
•Low inductance multiple power and ground pins for
minimum noise and ground bounce
•Direct interface with TTL levels
•All data inputs have bushold (74LVCH16373A only)
•High-impedance when VCC =0V.
•Complies with JEDEC standard no. 8-1A
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One Latch Enable
(LE) input and one Output Enable (OE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices. In 3-state operation, outputs can handle 5 V.
These features allow the use of these devices in a mixed
3.3 and 5 V environment.
The 74LVC(H)16373A consists of 2 sections of eight
D-typetransparentlatcheswith3-statetrueoutputs.When
LE is HIGH, data at the Dn inputs enter the latches. In this
condition the latches are transparent, i.e., a latch output
will change each time its corresponding D-input changes.
WhenLEisLOWthelatches storetheinformationthat was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The 74LVCH16373A bushold data inputs eliminates the
need for external pull up resistors to hold unused inputs.
FUNCTION TABLE
Per section of eight bits; note 1
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
OPERATING MODES INPUT INTERNAL
LATCHE OUTPUT
nQ0tonQ7
nOE nLE nDn
Enable and read register (transparent mode) L H L L L
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable outputs H L l L Z
HLhHZ
2003 Dec 08 3
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
a) PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacity in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay Dn to Qn CL= 50 pF; VCC = 3.3 V 3.0 ns
propagation delay LE to Qn CL= 50 pF; VCC = 3.3 V 3.4 ns
tPZH/tPZL 3-state output enable time OE to Qn CL= 50 pF; VCC = 3.3 V 3.5 ns
tPHZ/tPLZ 3-state output disable time OE to Qn CL= 50 pF; VCC = 3.3 V 3.9 ns
CIinput capacitance 5.0 pF
CPD power dissipation per latch VCC = 3.3 V; notes 1 and 2
outputs enabled 15 pF
outputs disabled 11 pF
TYPE NUMBER TEMPERATURE RANGE PACKAGE
PINS PACKAGE MATERIAL CODE
74LVC16373ADGG −40 to +125 °C 48 TSSOP48 plastic SOT362-1
74LVCH16373ADGG −40 to +125 °C 48 TSSOP48 plastic SOT362-1
74LVC16373ADL −40 to +125 °C 48 SSOP48 plastic SOT370-1
74LVCH16373ADL −40 to +125 °C 48 SSOP48 plastic SOT370-1
2003 Dec 08 4
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
PINNING
SYMBOL PIN DESCRIPTION
1OE 1 output enable input
(active LOW)
1Q0 2 data output
1Q1 3 data output
GND 4, 10, 15, 21, 28,
34, 39, 45 ground (0 V)
1Q2 5 data output
1Q3 6 data output
VCC 7, 18, 31, 42 supply voltage
1Q4 8 data output
1Q5 9 data output
1Q6 11 data output
1Q7 12 data output
2Q0 13 data output
2Q1 14 data output
2Q2 16 data output
2Q3 17 data output
2Q4 19 data output
2Q5 20 data output
2Q6 22 data output
2Q7 23 data output
2OE 24 output enable input
(active LOW)
2LE 25 latch enable input
(active HIGH)
2D7 26 data input
2D6 27 data input
2D5 29 data input
2D4 30 data input
2D3 32 data input
2D2 33 data input
2D1 35 data input
2D0 36 data input
1D7 37 data input
1D6 38 data input
1D5 40 data input
1D4 41 data input
1D3 43 data input
1D2 44 data input
1D1 46 data input
1D0 47 data input
1LE 48 latch enable input
(active HIGH)
SYMBOL PIN DESCRIPTION
16373A
mgu767
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
VCC
2D4
2D5
GND
2D6
2D7
2LE
1OE 1LE
Fig.1 Pin configuration SSOP48 and TSSOP48.
2003 Dec 08 5
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
handbook, full pagewidth
MGU769
2LE
D
LATCH
9
Q
2OE
to 7 other channels
LE LE
2Q02D0
1LE
D
LATCH
1
Q
1OE
to 7 other channels
LE LE
1Q01D0
Fig.2 Logic diagram.
handbook, halfpage
MGU768
1Q0
1Q1
1LE 2LE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1OE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2OE
Fig.3 Logic symbol.
handbook, halfpage
23
MGU770
37 12
11
9
8
6
5
47
46
44
43
41
40
38
1D7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2
3
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q0
1Q1
26
22
20
19
17
16
36
35
33
32
30
29
27
2D5
2D0
2D1
2D2
2D3
2D4
13
14
2Q5
2Q4
2Q3
2Q2
2Q1
2Q0
24
25 2EN
1OE 11EN
1LE
2OE
2LE
48 C3
C4
3D 1
4D 2
2D7
2D6
2Q7
2Q6
Fig.4 Logic symbol (IEEE/IEC).
2003 Dec 08 6
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
handbook, halfpage
to internal circuit
MGU771
VCC
data input
Fig.5 Bushold circuit.
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of Ptot derate linearly with 5.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage output HIGH or LOW state 0 VCC V
output 3-state 0 5.5 V
Tamb operating ambient temperature in free-air −40 +125 °C
tr,t
finput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V
output 3-state; note 1 −0.5 +6.5 V
IOoutput source or sink current VO=0toV
CC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb =−40 to +125 °C; note 2 −500 mW
2003 Dec 08 7
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
DC CHARACTERISTICS
Al recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C; note 1
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
VIL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL:
IO=−100 µA 2.7 to 3.6 VCC −0.2 −−V
IO=−12 mA 2.7 VCC −0.5 −−V
IO=−18 mA 3.0 VCC −0.6 −−V
IO=−24 mA 3.0 VCC −0.8 −−V
VOL LOW-level output voltage VI=V
IH or VIL:
IO= 100 µA 2.7 to 3.6 −−0.20 V
IO= 12 mA 2.7 −−0.40 V
IO= 24 mA 3.0 −−0.55 V
ILI input leakage current VI= 5.5 Vor GND; note 3 3.6 −±0.1 ±5µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 Vor GND; note 3 3.6 −±0.1 ±5µA
Ioff power off leakage current VIor VO= 5.5 V 0 −±0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 3.6 −0.1 20 µA
∆ICC additional quiescent
supply current per input
pin
VI=V
CC −0.6 V; IO= 0 2.7 to 3.6 −5(2) 500 µA
IBHL bushold LOW sustaining
current VI= 0.8 V; notes 4 and 5 3.0 75 −−µA
IBHH bushold HIGH sustaining
current VI= 2.0 V; notes 4 and 5 3.0 −75 −−µA
IBHLO bushold LOW overdrive
current notes 4 and 6 3.6 500 −−µA
IBHHO bushold HIGH overdrive
current notes 4 and 6 3.6 −500 −−µA
2003 Dec 08 8
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
Notes
1. All typical values are measured at Tamb =25°C.
2. Measured at VCC = 3.3 V.
3. For bushold parts, the bushold circuit is switched off when VI>V
CC allowing 5.5 V on the input pin.
4. Valid for data inputs of bushold parts (LVCH16373A) only. For data inputs only; control inputs do not have a bushold
circuit.
5. The specified sustaining current at the data inputs holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
Tamb =−40 to +125 °C
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
VIL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL:
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
IO=−12 mA 2.7 VCC −0.65 −−V
IO=−18 mA 3.0 VCC −0.75 −−V
IO=−24 mA 3.0 VCC −1−−V
VOL LOW-level output voltage VI=V
IH or VIL:
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO= 12 mA 2.7 −−0.6 V
IO= 24 mA 3.0 −−0.8 V
ILI input leakage current VI= 5.5 Vor GND; note 3 3.6 −−±20 µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 Vor GND; note 3 3.6 −−±20 µA
Ioff power off leakage current VIor VO= 5.5 V 0 −−±20 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 3.6 −−80 µA
∆ICC additional quiescent
supply current per input
pin
VI=V
CC −0.6 V; IO= 0 2.7 to 3.6 −−5000 µA
IBHL bushold LOW sustaining
current VI= 0.8 V; notes 4 and 5 3.0 60 −−µA
IBHH bushold HIGH sustaining
current VI= 2.0 V; notes 4 and 5 3.0 −60 −−µA
IBHLO bushold LOW overdrive
current notes 4 and 6 3.6 500 −−µA
IBHHO bushold HIGH overdrive
current notes 4 and 6 3.6 −500 −−µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
2003 Dec 08 9
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns; CL= 50 pF; RL= 500 Ω.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 to +85 °C; note1
tPHL/tPLH propagation delay Dn to Qn see Fig 6 and 10 1.2 −12 −ns
2.7 1.5 −4.9 ns
3.0 to 3.6 1.0 3.0(2) 4.4 ns
propagation delay LE to Qn see Fig 7 and 10 1.2 −14 −ns
2.7 1.5 −5.3 ns
3.0 to 3.6 1.5 3.4(2) 4.8 ns
tPZH/tPZL 3-state output enable time OE to Qn see Fig 8 and 10 1.2 −18 −ns
2.7 1.5 −5.7 ns
3.0 to 3.6 1.0 3.5(2) 4.9 ns
tPHZ/tPLZ 3-state output disable time OE to Qn see Fig 8 and 10 1.2 −11 −ns
2.7 1.5 −6.3 ns
3.0 to 3.6 1.5 3.9(2) 5.4 ns
tWLE pulse width HIGH see Fig 7 1.2 −−−ns
2.7 3.0 −−ns
3.0 to 3.6 3.0 2.0(2) −ns
tsu set-up time Dn to LE see Fig 9 1.2 −−−ns
2.7 2.0 −−ns
3.0 to 3.6 2.0 1.0(2) −ns
thhold time Dn to LE see Fig 9 1.2 −−−ns
2.7 0.9 −−ns
3.0 to 3.6 0.9 −1.0(2) −ns
tsk(0) skew note 3 3.0 to 3.6 −−1.0 ns
2003 Dec 08 10
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
Notes
1. All typical values are measured at Tamb =25°C.
2. Measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction.
This parameter is guaranteed by design.
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay Dn to Qn see Fig 6 and 10 1.2 −−−ns
2.7 1.5 −6.5 ns
3.0 to 3.6 1.0 −5.5 ns
propagation delay LE to Qn see Fig 7 and 10 1.2 −−−ns
2.7 1.5 −7.0 ns
3.0 to 3.6 1.5 −6.0 ns
tPZH/tPZL 3-state output enable time OE to Qn see Fig 8 and 10 1.2 −−−ns
2.7 1.5 −7.5 ns
3.0 to 3.6 1.0 −6.5 ns
tPHZ/tPLZ 3-state output disable time OE to Qn see Fig 8 and 10 1.2 −−−ns
2.7 1.5 −8.0 ns
3.0 to 3.6 1.5 −7.0 ns
tWLE pulse width HIGH see Fig 7 1.2 −−−ns
2.7 3.0 −−ns
3.0 to 3.6 3.0 −−ns
tsu set-up time Dn to LE see Fig 9 1.2 −−−ns
2.7 2.0 −−ns
3.0 to 3.6 2.0 −−ns
thhold time Dn to LE see Fig 9 1.2 −−−ns
2.7 0.9 −−ns
3.0 to 3.6 0.9 −−ns
tsk(0) skew note 3 3.0 to 3.6 −−1.5 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
2003 Dec 08 11
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
AC WAVEFORMS
handbook, halfpage
MGU772
Dn input
Qn output
tPHL tPLH
GND
VI
VM
VMVM
VOH
VOL
Fig.6 Input (Dn) to output (Qn) propagation delays.
VOL and VOH are the typical output voltage drop that occur with the output load.
VCC VMINPUT
VItr=t
f
1.2 V 0.5 ×VCC VCC ≤2.5 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
handbook, halfpage
MGU773
LE input
Qn output
tPHL tPLH
tW
VMVM
VOH
VI
GND
VOL
VMVMVM
Fig.7 Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays.
VOL and VOH are the typical output voltage drop that occur with the output load.
VCC VMINPUT
VItr=t
f
1.2 V 0.5 ×VCC VCC ≤2.5 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
2003 Dec 08 12
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
mgu775
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VMVM
GND
GND
tPZL
tPZH
VM
VM
Fig.8 3-state enable and disable times.
VX=V
OL + 0.3 V at VCC ≥2.7 V.
VX=V
OL + 0.1VCC at VCC < 2.7 V.
VY=V
OH −0.3 V at VCC ≥2.7 V.
VY=V
OH −0.1VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VCC VMINPUT
VItr=t
f
1.2 V 0.5 ×VCC VCC ≤2.5 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
handbook, full pagewidth
MGU774
thth
tsu
tsu
VM
VM
VI
GND
VI
GND
LE input
Dn input
Fig.9 Data set-up and hold times for the Dn input to the LE input.
The shaded areas indicate when the input is permitted to change
for predictable performance.
VCC VMINPUT
VItr=t
f
1.2 V 0.5 ×VCC VCC ≤2.5 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
2003 Dec 08 13
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
handbook, full pagewidth
VEXT
VCC
VIVO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.10 Load circuitry for switching times.
Definitions for test circuits:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
Note
1. The circuit performs better when RL= 1000 Ω.
VCC VICLRLVEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.2 V VCC 50 pF 500 Ω(1) open GND 2 ×VCC
2.7 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC
3.0 to 3.6 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC
2003 Dec 08 14
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
PACKAGE OUTLINES
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
w
M
θ
A
A
1
A
2
D
L
p
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
Ev
M
A
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
2003 Dec 08 15
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
48 25
MO-118
24
1
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
2003 Dec 08 16
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC16373A;
74LVCH16373A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyother conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation orwarrantythatsuch applicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomers usingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R20/06/pp17 Date of release: 2003 Dec 08 Document order number: 9397 750 12347
