Rev.1.0, Jul 06, 2004, page 1 of 28
HD49351BP/HBP
CDS/PGA & 10-bit A/D TG Converter REJ03F0110-0100Z
Rev.1.0
Jul 06, 2004
Description
The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digita l s ign al proce ss ing systems toge the r with a 10-bi t A/D c onve rte r and tim ing gene ra to r in a sing le ch ip. HD49351
has deleted the stripe mode, pd_mix m ode, a nd added the 5 – 6 pulse and H_msk2 - 4 as contra sted with HD49335.
There are address map and ti ming ge nerator charts be sides this specification. May be contacted to our sales department
if examining the details.
Functions
• Correlated double sampling
• PGA
• 10-bit ADC
• Timing gener a tor
• Operates using only the 3 V voltage
• Corresponds to switching mode of power consumption and operating frequency
220 mW (Typ), maximum f requency: 36 MHz (HD 49351 HBP)
150 mW (Typ), maximum f requency: 25 MHz (HD 49351 BP)
• ADC direct inp ut mode
• FBGA 65-pin pa ckage
Features
• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S /N ratio and a wide dynamic range provided by a PG amplifier.
• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 10-bi t-resolution A/D converte r.
• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solar ization
(wave pattern). It is patented by Renesas.
• Timing gener ator generates the all of pulse which are nee ded for CCD dr iving.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 2 of 28
Pin Arrangement
(Top view)
32
XV3
31
XV2
30
XV1
29
DVdd3
26
H2
24
DVss4
22
H1
19
RG
17
VD_i/o
16
HD_i/o
10
A
K
Notes: 1.
2.
3.
Pin 41 outputs the STROB, pin 39 outputs the SUB_SW when pin 61 is Low.
Pin 41 inputs the Vgate, pin 39 inputs the ADCK when pin 61 is High.
1/2 and 4clk output terminal becomes 1/3 and 1/6clk output respectively,
when operating TG in 3 divided mode.
J
H
G
F
E
D
C
B
98765432 1
33
XV4
34
CH1
28
DVdd4
27
1/4clk
25
DVss4
23
1/2clk
21
DVdd4
20
DVdd3
18
Reset
15
CLK_in
48
VRM
46
VRB
45
Bias
42
DVss3
40
SUB_PD
38
XSUB
35
CH2
44
ADC_in
43
AVss
41
Strob
39
SUB_SW
37
CH4
36
CH3
5
D2
7
D4
9
D6
10
D7
12
D9
14
DVss3
14
DVss3
3
D0
4
D1
6
D3
8
D5
11
D8
13
DVdd2
49
AVdd
52
AVdd
55
AVss
56
test2
57
test1
59
DVdd1
61
41cont
62
CDS_CS
2
DVss1,2
47
VRT
50
BLKC
51
CDS_in
53
BLKFB
54
BLKSH
58
DLLC
60
MON
63
Sdata
64
SCK
1
ID
Pin Description
BGA
Pin No. PAD
No.
Symbol
Description
I/O Analog(A) or
Digital(D)
Remarks
K1 1 ID Odd/even number line detect ing pulse output pin O D 2 mA/10 pF
J1 2 DVss1, 2 CDS Digital ground + ADC output buffer ground (0V) — D
H1 to D2 3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB) O D 2 mA/10 pF
C1 13 DVdd2 ADC output buffer power supply (3 V) — D
C2, C3 14 Dvss3 General ground for TG (0V) — D
B1 15 CLK_in CLK input (max 72 MHz) I D
A1 16 HD_in HD input I D
A2 17 VD_in VD input I D
B2 18 Reset Hardware reset (for DLL reset) I D Schmitt trigger
A3 19 RG Reset gate pulse output O D 3 mA/10 pF
B3 20 DVdd3 General power supply for TG (3V) — D
B4 21 DVdd4 H1,2 buffer power supply (3 V) — D
A4 22 H1 H.CCD transfer pulse output-1 O D 30 mA/165 pF
B5 23 1/2clk_o CLK_in 2 divided output. 3 divided output at 3 divided mode O D 2 mA/10 pF
A5 24 Dvss4 H1,2 buffer ground (0 V) — D
B6 25 Dvss4 H1,2 buffer ground (0 V) — D
A6 26 H2 H.CCD transfer pulse output-2 O D 30 mA/165 pF
B7 27 1/4clk_o CLK_in 4 divided output. 6 divided output at 3 divided mode O D 2 mA/10 pF
B8 28 DVdd4 H1,2 buffer power supply (3 V) — D
A7 29 DVdd3 General power supply for TG (3 V) — D
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 3 of 28
Pin Description (cont.)
BGA
Pin No. PAD
No.
Symbol
Description
I/O Analog(A) or
Digital(D)
Remarks
A8 30 XV1 V.CCD transfer pulse output-1 O D 2 mA/10 pF
A9 31 XV2 V.CCD transfer pulse output-2 O D 2 mA/10 pF
A10 32 XV3 V.CCD transfer pulse output-3 O D 2 mA/10 pF
B10 33 XV4 V.CCD transfer pulse output-4 O D 2 mA/10 pF
B9 34 CH1 Read out pulse output-1 O D 2 mA/10 pF
C10 35 CH2 Read out pulse output-2 O D 2 mA/10 pF
C9 36 CH3 Read out pulse output-3 O D 2 mA/10 pF
D9 37 CH4 Read out pulse output-4 O D 2 mA/10 pF
D10 38 XSUB Pulse output for electr onic shutter O D 2 mA/10 pF
E9 39 SUB_SW SUB voltage control output-1. Input the ADCK when 61 pin
is Hi I/O D 2 mA/10 pF
E10 40 SUB_ PD SUB voltage control output-2 O D 2 mA/10 pF
F9 41 STROB Flash control output. Input Vgate at Hi of 61pin I/O D 2 mA/10 pF
F10 42 DVss3 General ground for TG (0 V) — D
G9 43 AVss Analog ground (0 V) — A
H9 44 ADC_in A/D converter input pin I A
G10 45 BIAS Bi as standard resistance (33 kΩ for Gnd) — A
H10 46 VRB ADC bottom standard voltage (0.1 µF for Gnd) — A
K10 47 VRT ADC top standard voltage (0.1 µF for Gnd) — A
J10 48 VRM ADC middle standard voltage (0.1 µF for Gnd) — A
J9 49 Avdd Analog power supply (3 V) — A
K9 50 BLK_C Black level C pin (1000pF for Gnd) — A
K8 51 CDS_in CDS input pin I A
J8 52 AVdd Analog power supply (3 V) — A
K7 53 BLKFB Black level FB pin (1 µF betw een BLKFB and BLKSH) I A
K6 54 BLKSH Black level S/H pin O A
J7 55 AVss Analog ground (0 V) — A
J6 56 Test2 H: Normal operation, L: CDS single operation mode
Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,
Input 39; ADCLK, Input 40; SP2, Input 4 1; SP1
I D
J5 57 Test1 L: Slave mode, H: Master mode I D
K5 58 DLL_C Analog delay DLL external C pin (100 pF for Gnd) O A
J4 59 Dvdd1 Digital power supply (3 V) CDS, PAG, ADC part — D
K4 60 MON Pulse monitor (SP1, SP2, ADCLK, OBP, CPDM, PBLK
output) O D 2 mA/10 pF
J3 61 41cont Input STROB = pin 41, Input SUB_SW = pin 39 at Low
Input Vgate = pin 41, Input ADCK = pin 39 at Hi I D
J2 62 CDS_CS Serial data CS at CDS part I D
K3 63 SDATA Input serial data I D
K2 64 SCK Input serial clock I D
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 4 of 28
Input/Output Equiva lent Circuit
Pin Name Equiv alent Circuit
Digi tal output D0 to D9, RG, H1A to H2B ,
XV1 to X V 4, CH1 to CH4,
XSUB, SUB_SW, SUB_PD,
STROB, MON
DIN
DV
DD
STBY
Digital
output
Digital input ADCLK, OBP, CPDM, SP1,2,
PBLK, CS, SCK, SDATA,
CLK_in, HD_in, VD_in
Digital
input
DVDD
CDS_in
CDS_in
AVDD
Internally
connected
to VRT
ADC_in
A
DC_in
AV
DD
Internally
connected
to VRM
BLKSH, BLKFB, BLKC
BLKFB
AV
DD
BLKSH
BLKC
−
+
VRT , VRM, VRB
−
+
−
+
VRT VRM VRB AV
DD
Analog
BIAS
BIAS
AV
DD
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 5 of 28
Block Diagr am
10bit
ADC
AVss
VRB
VRM
VRT
CDS_in CDS
BLKSH
BLKC
ADC_in
SUB_SW
SUB_PD
STROB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
DVss1 to 4
BLKFB
CDS_CS
SDATA
SCK
DLL_C
MON
ID
BIAS
Timing
generator
VD_in
HD_in
CLK_in
XSUB
CH4
CH3
CH2
CH1
XV4
XV3
PBLK
CPDM
OBP
ADCLK
SP2
SP1
XV2
XV1
1/4clk_o
H2A
1/2clk_o
H1A
RG
AVdd
DVdd1 to 4
PGA
DLL
Output latch circuit
DC offset
compensation
circuit
Serial
interface
Bias
generator
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 6 of 28
Internal Funct ions
Functional Description
• CDS input
CCD low-frequency noise is suppressed by CDS ( correlated double sampling).
The signal level is clamped at 14 LSB to 76 LSB (set by resister: 5 bit 2 LSB step controls) during the OB
period. *1
Gain can be adjusted using 8 bits of register (0.132 dB steps) within th e range from –2.36 dB to 31.40 dB. *2
• ADC input
The center level of the input signal is clamped at 512 LSB (Typ).
Gai n c an be adju st e d us in g 8 bits of registe r (0.01 784 times st e ps, re gister settin gs) within the ra nge fr om 0.5 7
times (–4.86 dB) to 5.14 times (14.22 dB). *2
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
Digita l outpu t is fixed at clam p level
• Digital outputs enable function
Note: 1. It is not covered by warranty when 14 LSB settings
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 show s CDS/PGA + ADC function b loc k.
DAC
C3
CDS
AMP
PG
AMP
CDS_in
BLKFB BLKSH
SH
AMP
C2
C1
VRT
SP1 SP1
SP2 10bit
ADC
D0 to D9
BLKC
C4
OBP
ADC_in
Offset
calibration
logic
DC offset
feedback
logic
Gain setting
(register) Clamp data
(register)
Current
DAC
Figure 1 CDS/PGA Functional Block Diagram
1. CDS (Correla ted Double Sampling) Circu it
The CDS circuit extracts the voltage differential between the black level and a sign al including the black level. The
black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly samp led at C2 by using the SP2 pulse, and then provided to C DSAM P (see figur e 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.
2. PGA Circuit
The PGAMP is the programma ble gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.
In CDSIN mode: Gain = (–2.36 dB + 0.132 dB) × N (LOG linear).
In ADCIN mode : Gain = (0.57 times + 0.001784 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 7 of 28
3. Automatic Offset C a libra tion Func tion and Black-Level Clamp Data Set tings
The DAC DC voltage ad de d to the out put of t h e PGA amplifier is adju st e d by aut omatic offs et cali b r ation.
The data, wh ich cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates a fter 40, 000 cloc k cyc les (when f clk = 40. 0 MHz, 1.0 ms, fc lk = 20. 0 MHz, 2.0 ms).
4. DC Offset Compensation Feedback Function
Feedback is done to set the black signal level input duri ng the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the AD C output is calculated during the OB period, and SHAMP feedback capacitor C3 is ch arged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.07 8 / (f cl k × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: W hen fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0. 003 9
DC offset compensation per 1 H (LSB) = 0.0039 × Offset error (LSB) Note)
Note: There is a maximum value in the above-mentioned amount of offset errors.
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is incre ased by a multiple of N. Loop ga in multiplication factor N ca n be se lected f rom 4 time s, 8 times, 16
tim e s, or 32 tim es b y changi ng t h e register setti n gs ( s e e table 1) . Not e that th e ope n -loop differ ential gain
(∆Gain/∆H) must be o ne or lo wer. If it is two or more, oscillation occ urs.
The time from the termination of high-spee d lead-in operation to the return of n ormal loop ga in operation can be
selected fr om 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the hig h-speed lead-in operation continues,
and when the of fset error is 16 LS B or less, the operation r eturns t o the normal loop-gain operat ion after 1 H, 2 H, 4
H, or 8 H de pen d ing on the reg is ter sett ings . (Refer to table 2.)
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation
Table 2 High-Speed Lead-In Operation
Cancellation Time
HGain-Nsel
(register settings) Multiplication
Factor N
HGstop-Hsel
(register settings) Cancellation
Time
[0]
L
H
L
H
[1]
L
H
H
L
× 4
× 32
× 16
× 8
[0]
L
H
L
H
[1]
L
H
H
L
1 H
8 H
4 H
2 H
5. Pre-Blanking Function
During the PBLK input period, the CDS inp ut operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp d ata (14 to 76 LS B).
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 8 of 28
6. ADC Digital Output Control Funct ion
The ADC digital outp ut includes the functions output ena ble, code convers ion, and test mode . Tables 3, 4 and 5
show the output function s and the codes.
Table 3 ADC Digital Output Functions
H
L
H
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
X
X
L
L
L
L
H
L
L
L
L
H
X
X
X
X
X
X
L
H
L
H
X
L
H
L
H
X
L
H
L
H
X
X
L
L
H
H
X
L
L
H
H
X
L
L
H
H
X
X
L
H
X
X
X
L
H
H
L
STBY
D9
TEST0
D0D1D2D3D4D5D6D7D8
PBLK
MINV
TEST1
LINV
Hi-Z
Hi-Z
Same as in table 4.
D9 is inverted in table 4.
D8 to D0 are inverted in table 4.
D9 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D9 is inverted in table 5.
D8 to D0 are inverted in table 5.
D9 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
Low-power wait state
Output Hi-Z
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
Operating Mode
ADC Digital Output
Note: 1. STBY, TEST, LINV, and MINV are set by register.
Table 4 ADC Output Code (Binary)
Output Pin
Output
codes
Steps
0
1
2
3
4
5
6
511
512
1020
1021
1022
1023
D1
L
L
H
H
L
L
H
H
L
L
L
H
H
D0
L
H
L
H
L
H
L
H
L
L
H
L
H
D2
L
L
L
L
H
H
H
H
L
H
H
H
H
D7
L
L
L
L
L
L
L
H
L
H
H
H
H
D5
L
L
L
L
L
L
L
H
L
H
H
H
H
D4
L
L
L
L
L
L
L
H
L
H
H
H
H
D3
L
L
L
L
L
L
L
H
L
H
H
H
H
D6
L
L
L
L
L
L
L
H
L
H
H
H
H
D8
L
L
L
L
L
L
L
H
L
H
H
H
H
D9
L
L
L
L
L
L
L
L
H
H
H
H
H
Table 5 ADC Output Code (Gray)
Output Pin
Output
codes
Steps
0
1
2
3
4
5
6
511
512
1020
1021
1022
1023
D1
L
L
H
H
H
H
L
L
L
H
H
L
L
D0
L
H
H
L
L
H
H
L
L
L
H
H
L
D2
L
L
L
L
H
H
H
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
L
L
L
L
L
L
D3
L
L
L
L
L
L
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
L
L
L
L
L
L
D8
L
L
L
L
L
L
L
H
H
L
L
L
L
D9
L
L
L
L
L
L
L
L
H
H
H
H
H
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 9 of 28
7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level ca n be adjusted by changing the
register setting s, as shown in table 6.
Table 6 SHSW CR Time Consta nt Setting
31
BLKC
C
Recommendation value of C is 1000 pF
The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.
8.
2.20 nsec
(72 MHz)
2.30 nsec
(69 MHz)
2.51 nsec
(63 MHz)
2.64 nsec
(60 MHz)
2.93 nsec
(54 MHz)
3.11 nsec
(51 MHz)
3.52 nsec
(45 MHz)
3.77 nsec
(42 MHz)
L
[3]
L
[0]
L
[0]
4.40 nsec
(36 MHz)
4.80 nsec
(33 MHz)
L
[1]
L
[1]
L
[2]
L
[2]
5.87 nsec
(27 MHz)
6.60 nsec
(24 MHz)
8.80 nsec
(18 MHz)
10.6 nsec
(15 MHz)
17.6 nsec
(9 MHz)
26.4 nsec
(6 MHz)
L
[3]
H
[3]
H
[0]
H
[0]
L
[1]
L
[1]
L
[2]
L
[2]
L
[3]
H
[3]
L
[0]
L
[0]
H
[1]
H
[1]
L
[2]
L
[2]
L
[3]
H
[3]
H
[0]
H
[0]
H
[1]
H
[1]
L
[2]
L
[2]
L
[3]
H
[3]
L
[0]
L
[0]
L
[1]
L
[1]
H
[2]
H
[2]
L
[3]
H
[3]
H
[0]
H
[0]
L
[1]
L
[1]
H
[2]
H
[2]
L
[3]
H
[3]
L
[0]
L
[0]
H
[1]
H
[1]
H
[2]
H
[2]
L
[3]
H
[3]
H
[0]
H
[0]
H
[1]
H
[1]
H
[2]
H
[2]
H
[3]
SHSW-fsel (Register setting)
SHSW-fsel (Register setting)
CR Time Constant (Typ)
(cutoff frequency conversion)
CR Time Constant (Typ)
(cutoff frequency conversion)
Table 7 SHAMP Frequency Characteristics Setting
230 MHz
6800 pF
(240 pF)
56 MHz
18000 pF
(360 pF)
116 MHz
10000 pF
(270 pF)
100 MHz
10000 pF
(560 pF)
"Lo"
"Hi" 24 MHz
27000 pF
(820 pF)
75 MHz
13000 pF
(300 pF)
32 MHz
22000 pF
(750 pF)
49 MHz
15000 pF
(620 pF)
L
[0]
H
[0]
L
[1]
L
[1]
L
[0]
H
[1]
H
[0]
H
[1]
SHA-fsel (Register setting)
LoPwr
(Register setting)
Note: Upper line
Middle line
Lower line
: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 10 of 28
Timing Char t
Figur e 2 shows the timing chart whe n CDS_in and ADC_in input modes are used .
012 91011
N+1 N+2 N+9 N+10 N+11N
CDS_in
SP1
SP2
ADCLK
D0 to D9
N+2
N+8 N+9
N+10 N+11
N−8N−9N−1
ADC_in
ADCLK
D0 to D9
NN+1
NN+1
N−9N−8N−1 NN−10
• When CDS_in input mode is used
• When ADC_in input mode is used
~
Figure 2 Outpu t Timing Chart when CDS_in and ADC_in Input Mod es are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten cloc k cycles when CDS_in is used and nine when ADC_in is use d.
• In ADC_ in input mode, the input sign al is sampled at the ri sing edge of the ADCL K.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 11 of 28
Detailed Timing Specifications
Detailed Timing Specifications when CDS_in Input Mode is Used
Figure 3 shows the detailed timing spec ifications when the CDS_in input mode is used, and table 8 shows each timing
specification.
CDS_in
SP1 Vth
(2) (3)
SP2
A
DCLK
(7)
Vth
Vth
(8)
(9)
(10)
(4)
(1)
(5)
(6)
D0 to D9
Black
level
Signal
level
Figure 3 Detailed Timing Chart when CDS_in Input Mode is U sed
Table 8 Timing Specifications when the CDS_in Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Black-level signal fetch time tCDS1 — (1.5) — ns
(2) SP1 ‘H i’ period tCDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(3) Signal-level fetch time tCDS3 — (1.5) — ns
(4) SP2 ‘H i’ period tCDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(5) SP1 falling to SP2 fall i ng ti m e tCDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
(6) SP1 falling to ADCLK ri sing inhibit time tCDS6 — (5) — ns
(7), (8) ADCLK tWH mi n./tWL min tCDS7, 8 11 — — ns
(9) ADCLK risi ng to digital output holding time t
CHLD9 — (7) — ns
(10) ADCLK rising to di gital output delay time tCOD10 — (16) — ns
OBP Detailed Timing Specifications
Figur e 4 show s the OBP deta il ed tim ing sp ec ific a tions.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
CDS_in
OBP
NN+1 N+5 N+12 N+13
Note:
OB pulse > 2 clock cycles
OB period *1
1. Shifts ±1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 12 of 28
Detailed Timing Specifications at Pre- Blanking
Figur e 5 shows the pre- blanking deta iled t iming spe ci fica t io ns.
Digital output
(D0 to D9)
ADC
data Clamp Level ADC
data
PBLK
ADCLK × 2 clock ADCLK × 10 clock
Vth
V
OL
V
OH
Figure 5 Detailed Timing Specifications at Pre-B lanking
Detailed Timing Specifications when ADC_in Input Mode is Used
Figure 6 shows the detailed timing chart when ADC_in input mode is used, and table 9 shows each timing specification.
A
DC_in
(1)
A
DCLK
D0 to D9
(2)
Vth
V
DD
/2
(3)
(5)
(4)
Figure 6 Detailed Timing Chart when ADC_in Input Mode is Used
Table 9 Timing Specifications when ADC_in Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Signal fetch time tADC1 — (6) — ns
(2), (3) ADCLK tWH min./tWL min. tADC2, 3 Typ × 0.85 1/2fADCLK Typ × 1.1 5 ns
(4) ADCLK rising to digital output hold time tAHLD4 — (14.5) — ns
(5) ADCLK rising to digit a l output delay tim e tAOD5 — (23.5) — ns
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 13 of 28
Dummy Clamp
It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it
woks with the OB clamp, however when black le vel is out of the range caused by hightlight enter to OB part, it changes
to clamp processing by dummy bit level. Resister settings are follows.
D12, D11, D10 (Dummy CP) of address H'F7
0, 0, 0 ; OFF
0, 0, 1 ; +32
0, 1, 0 ; +64
0, 1, 1 ; +96
:
:
1, 1, 1 ; +224
The amount of offset are changes automatically
depends on PGA gain in the LSI.
D8, D9 (DMCG) of address H'F7
The amount of feed back current can be
reduced with only dummy clamp.
Data = 0:1/4
1:1/8
2:1/16
3:1/32
D10 to D12 of address H'F7
Note: OB/Dummy switching part has 1/8 hysteresis of threshold value.
D8 to D9 of address H'F7
Digital output
CDS
AGC
CDS_in
BLKFB BLKSH
SH
AMP
VRT
SP1
SP2
SP1
on/off
Clamp level
+
−
−
+
+
(+)
(−)
ADC
OB
DET
Current
cell
Dummy
DET
Detect 4clk
from CPDM edge
Detect 8clk
from OBP edge
Figure 7 Internal Bias Circ uitry
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 14 of 28
Absolute Maximum Ratin gs
(Ta = 25°C)
Item Symbol Ratings Unit
Power supply voltage Vdd(max) 4.1 V
Power dissipation Pt(max) 500 mW
Operating pow er supply voltage Vo pr 2.70 to 3.45 V
Analog input voltage VIN(max) –0.3 to AVd d +0.3 V
Digital input voltage VI(max) –0.3 to DVdd +0.3 V
Operati ng temperature Topr –10 to +75 °C
Storage t emper a ture Tstg –55 to +125 ° C
Note: AVdd, AVss are analog power source systems of CDS, PGA, and ADC.
DVdd1, DVss1 are digital power source syst ems of CDS, PGA and AD C.
DVdd2, DVss2 are buffer powe r source systems of ADC output.
DVdd3, DVss3 ar e gener al digi tal power sour ce sy ste ms of TG.
DVdd4, DVss4 are buffer powe r source systems of H1 and H2.
• Pin 2 multi bonds th e DVss 1 and DVss 2
• When pin 64 is set t o Low, pin 41 = STROB output, pi n 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCLK input
Electrical Characteristics (Unless specifie d, Ta = 25° C, AV dd = 3.0 V, DVdd = 3.0 V, and RBIAS = 33 kΩ)
• Items Common to CDS_in and ADC_in Input Modes
Item Symbol Min Typ Max Unit Test Conditions Remarks
Power supply voltage
range Vdd 2.70 3.00 3.45 V
fCLK hi 20 — 36 MHz LoPwr = low *1 HD49351HBP Conversion frequency fCLK low 5.5 — 25 MHz LoPwr = high HD49351BP
VIH2
DVdd
3.0
2.25 ×
— DVdd V
Digital input voltage
VIL2 0 —
DVdd
3.0
0.6 ×
V
All of digital input
pin
VOH DVdd –0.5 — — V IOH = –1 mA Digital output voltage VOL — — 0.5 V IOL = +1 mA
IIH — — 50 µA DVdd = VIH = 3.0 V Digital input current IIL –50 — — µA VIL = 0 V
IOZH — — 50 µA VOH = Vdd Digital output current IOZL –50 — — µA VOL = 0 V
ADC resolution RES — 10 — bit
ADC integral linearity INL — (2) — LSBp-p fCLK = 20 MHz
ADC differential linearity DNL — (±0.3) — LSB fCLK = 20 MHz *2
Sleep current ISLP –100 0 100 µA Fix digital input pin
to 0 V, output pin
should open
Standby current ISTBY — 3 5 mA Fix digital I/O pin to
0 V
tHZ — — 100 ns
tLZ — — 100 ns
tZH — — 100 ns
Digital output Hi-Z delay
time
tZL — — 100 ns
RL = 2 kΩ,
CL = 10 pF Refer to figure 7
Notes: 1. It is expressing on the fr equenc y in an a nalog circuit part. Please keep i n your mind tha t TG part has 2
divi ded, 3 divided mode.
2. Differential linearity is the calculated differen ce in linearity errors between adjacent codes.
3. Values within parentheses ( ) are for refer ence.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 15 of 28
Electrical Characteristics (cont.)
(Unless specified, Ta = 25°C, AVdd = 3.0 V, DVdd = 3.0 V, and RBIAS = 33 kΩ)
• Items for CDS_in Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumption current (1) IDD1 — (65) — mA fCLK = 36 MHz CDS_in mode
LoPwr = low
Consumption current (2) IDD2 — (50) — mA fCLK = 20 MHz CDS_in mode
LoPwr = high
CCD offset tolerance range VCCD (–150) — (150) mV
Timing specifications (1) tCDS1 — (1.5) — ns
Timing specifications (2) tCDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (3) tCDS3 — (1.5) — ns
Timing specifications (4) tCDS4 Typ
× 0.8 1/4fCLK Typ
× 1.2 ns
Timing specifications (5) tCDS5 Typ
× 0.85 1/2fCLK Typ
× 1.15 ns
Timing specifications (6) tCDS6 — (5) — ns
Timing specifications (7) tCDS7 11 — — ns
Timing specifications (8) tCDS8 11 — — ns
Timing specifications (9) tCHLD9 — (7) — ns CL = 10 pF
Timing specifi cations (10) tCOD10 — (16) — ns CL = 10 pF
Refer to table 8
CLP(00) — (14) — LSB
CLP(09) — (32) — LSB
Clamp level
CLP(31) — (76) — LSB
PGA(0) –4.4 –2.4 –0.4 dB
PGA(63) 4.1 6.1 8.1 dB
PGA(127) 12.5 14.5 16.5 dB
PGA(191) 21.0 23.0 25.0 dB
PGA gain at CDS input
PGA(255) 29.4 31.4 33.4 dB
Note: Values within parentheses ( ) are for reference.
• Items for ADC_in In put Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumption current (3) IDD3 — (35) — mA fCLK = 36 MHz ADC_in mode
LoPwr = low
Consumption current (4) IDD4 — (20) — mA fCLK = 25 MHz ADC_in mode
LoPwr = high
Timing specifications (11) tADC1 — (6) — ns
Timing specifications (12) tADC2 Typ
× 0.85 1/2fADCLK Typ
× 1.15 ns
Timing specifications (13) tADC3 Typ
× 0.85 1/2fADCLK Typ
× 1.15 ns
Timing specifications (14) tAHLD4 — (14.5) — ns CL = 10 pF
Timing specifications (15) tAOD5 — (23.5) — ns CL = 10 pF
Refer to table 9
Input current at ADC input IINCIN –110 — 110 µA VIN = 1.0 to 2.0 V
Clamp level at ADC input OF2 462 512 562 LSB
GSL(0) 0.45 0.57 0.72 Times
GSL(63) 1.36 1.71 2.16 Times
GSL(127) 2.27 2.86 3.60 Times
GSL(191) 3.18 4.00 5.04 Times
PGA gain at ADC input
GSL(255) 4.08 5.14 6.47 Times
Note : Values within parentheses ( ) are for re ference.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 16 of 28
Serial Interface Specifications
Timing Specifications
SDATA
STD2(Upper data) STD1(Lower data) address(address)
SCK
CS
f
SCK
D9D8 D11D10 D13D12 D15D14 D1D0 D3D2 D5D4 D7D6 D0 D2D1 D4D3 D6D5 D7
t
INT1
t
INT2
t
su
t
ho
Latches SDATA
at SCK rising edge
Data is determined
at CS rising edge
Figure 8 Serial Interface Timing Specifications
Item Min Max
fSCK — 5 MHz
tINT1,2 50 ns —
tsu 50 ns —
tho 50 ns —
Notes: 1. 3 byte continuous communications.
2. Input S CK with 24 cl ock when CS is Low.
3. It becomes invali d when data com munications are stopped o n the way .
4. Data becomes a default with hardware reset.
5. Input more than double frequency of SCK to the CLK_in when transfer
the serial data.
The Kind of Data
Data address has 256 ty pe. H’00 to H ’F F
H’00
:
:
H’EF
Data at timing generator part
H’F0
:
:
H’FF
Data at CDS part
Addres s map of eac h data ref e rred to othe r shee t.
Det a ils of timing gener ator refer to the timing chart on the other shee t toge t h er with this speci fication.
This spec if ica ti on only ex plai ns abou t the da ta of CDS part.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 17 of 28
Exp lanation of Ser ial Data of CDS Part
Serial data of CDS part ar e assigned to address H’F0 to H’F8. Functions are follows.
Address STD1[7:0] (L)
PGA gain
STD2[15:8] (H)
1 1 1 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
test_I1
• PGA gain (D0 to D7 of addr ess H’F0)
Details are referred to page 6 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (cor respond 2.36 dB), and then
PGA outputs the 2 V f ull-range, and also AD C outputs the full code (1023) .
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB a dd
on.
(1) Level dia explain
CDS PGA
0 dB when set N = 18 which correspond to 2.36 dB
ADC
(2) Level dia on the circuit
CDS PGA
3.64 dB + 0.132 dB × N
(CDS = 0 dB)
ADC
2 V 1023
(1.0 V)
(1.0 V) (2.0 V) (1023)
Figure 9 Level Dia of PGA
• Test_I1 (D13 to D15 of address H’ F0)
It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally.
When data = 0, 50% current val ue with default
When data = 4, default
When data = 7, 150% current value with default
Address STD1[7:0] (L) STD2[15:8] (H)
1 1 1 1 0 0 0 1 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
SHA_fseltest_I2 SHSW_fsel
test0
MINV
LINV
STBY
SLP
• SLP and STBY (D0, D1 of address H’F1)
SLP: Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 18 of 28
• Output mode (D2 to D4 of address H’F1 and address H’F4 of D6)
It is a test mode. Combination details are page 8. Normally set to all 0.
• SHA-fsel (D8 to D9 of addre ss H’F1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the
double cut off frequency point with using.
• SHS W-fsel (D10 to D13 of address H’F1)
It is a time constant which sa mpling the black level of SH amplifier. Frequency characteristics are referred to page
9. To ge t rough idea, set the d ouble cut off frequency point with u sing. S/N changes by this data, so find the
appropriate point with set data to up/down.
• Test_I2 (D14 to D15 of address H’ F1)
Curre nt of ADC analog part can be set minutely. Norma lly use data = 0.
0: Default (100%)
1: 150%
2: 50%
3: 80%
Address STD1[7:0] (L)
HGain-Nsel
STD2[15:8] (H)
1 1 1 1 0 0 1 0 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
Clamp level
Reset
AD_sel
CDS_buff
Low_pwr
HGstop-Hsel
• Clamp (D0 to D4 o f address H’F2)
Determine the OB part level with digital code of ADC output.
Clamp level = setti ng data × 2 + 14
Default data is 9 = 32 LSB.
• HGstop-Hsel, HGain-Nsel (D8 to D11 of address H ’ F2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode .
• Low_PWR (D12 of address H’F2)
Switch circuit current and frequency characteristic.
Data = 0: 40 MHz guarantee
Data = 1: 25 MHz guarantee
• ADSEL (D 14 of address H’F2 )
Data = 0: Select CDS_in
Data = 1 : S el e ct ADC_in
• Reset (D15 of address H’F2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be do ne when starting up with usin g this bi t. Details are referred to page 23.
Address STD1[7:0] (L) STD2[15:8] (H)
11110011 D4D3D2D7 D6 D5 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
• Address H'F3 are all testing data.
Normally set to all 0., or do not transfer the data.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 19 of 28
Address STD1[7:0] (L) STD2[15:8] (H)
11110100 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8
Gray_test
VD latch MON
Gray code
H12_Buff
• MON (D0 to D2 of a ddres s H’F4)
Select the pulse which output to pin MON (pin 60).
When D0 to D2: 0, Fi x to Lo w When 1, ADCLK
W hen 2, SP1 When 3, SP2
W hen 4, OBP W hen 5, PBLK
W hen 6, CPDM When 7, DLL_test
• H12Baff (D3 to D6 of addr ess H’F4)
Select the buffer size which output to pin H1A, H2A (pin 22, 26).
D3: 2 mA buf fer
D4: 4 mA buff er
D5: 10 mA buffer
D6: 14 mA buffer
Above data ca n be on/off individually. Default is D6 can be on only. (18 mA buffer)
• VD latch (D7 of address H’F4)
Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD rising
• Gray (D8 to D9 of address H’F4)
ADC output code can be change to following ty pes. Diffe rent ial co de is mentioned to next pag e.
Gra y Code [1] Gra y Code [0] Output Code
0 0 Binary code
0 1 Gray code
1 0 Differential encoded binary
1 1 Differential encoded gray
• Gray_test (D10 to D12 of address H’F4)
Data which de te rmine the differential code and sta ndard phase of gray code.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 20 of 28
• Gray code (D8 to D12 of address H ’F 4)
ADC out p ut co de c an b e change t o following t ype by dif ferential code gray SW (D9, D8) .
Binary code at D8: 0, Gray code at D8: 1
Normal at D9: 0, differential code at D9: 1
Differential code and gray code are recommended for this countermeasure. Figure 10 indicates circuit block. When
luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily
to reduce the ripple using this function. This function is espe cially effe ctive for l onger the se ttings of sensor more
than clk = 30 MHz, and ADC output.
Figure 12 indicates the timing specifications.
Standard
Phase (D10) Standard
Phase (D11) St andard Da ta Output timing at
Selecting the Differential Code
0 0 Third and fourth
1 0 Fourth and fifth
0 1 Fifth and sixth
1 1 Sixth and seventh
• adck pha se (D 12): ADCK polar to OBP
When 0: Select positive edge
When 1: Select negative edge
Note: Color filter is different1 in the number of pixels with odd number
and even number therefore first 2 pixcels should be standard.
ADC
10
10
Differential SW(D9)
Carry bit
rounding
+
−
Gray SW(D8)
Standard data
control signal
(D10, D11)
Standard
data
selector
Output
2clk_DL Convert
Gray→Binary
Figure 10 Differential Code and Gray Code Circuit
1
OBP
(In case of select the positive polar)
Digital output
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
(In case of select the positive edge of ADCLK with D12)
Differential data Standard
data
Differential data
A
DCLK
2345678
Figure 11 Timing Specification of Differ ential Code
(1) Complex differential coded
From ADC
Standard data
control signal
Carry bit
rounding
Standard
data
selector
D11 D11
D10
D9
D0
D10
D9
D0
(2) Convert Gray → Binary
Convert
Gray→Binary
2clk
delay
Figure 12 Complex Circuit Example at the DS P Side
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 21 of 28
Address STD1[7:0] (L) STD2[15:8] (H)
11110101 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8
P_SP1P_SP2P_ADCLKP_RG DLL
steps
DLL
current
2,3 divided
select
Address STD1[7:0] (L) STD2[15:8] (H)
11111000 D4 D2D6 D5 D1 D0 D12 D10D15 D14 D13 D9 D8
P_SP2 P_SP1 P_ADCLKP_RG
• Address H’F5 sets the DLL delay time and sele cts the 1/4 phase . Details are on the next page. And D15 of a ddres s
H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.
D15 of address H’F8 = 0 D15 of address H’F8 = 1
Divi ded mode Select the 2 divided, 1/4 phas e Select the 3 divided, 1/6 phase
D0 to D7 of addre ss H’F5 Valid Inva lid
D0 to D1 4 of ad dress H’F8 Invalid Valid
• Phase settings of high speed pulse (address H’F5 to H’F8)
(1) Select the 1 /4 phase from fig ure 13 at 2 divided mode (D15 = 0 of address H’F8) .
Select the 1/6 phase from figure 14 a t 3 divided mode (D 15 = 1 of address H’F8).
·····P_SP1, P_SP2, P_ADCLK, P_RG
(2) Then select the necessary delay time from figure 15.
·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.
H1
Data = 0
Data = 1
Data = 3
Data = 2
P_SP1
P_SP2
H1
Data = 0
Data = 1
Data = 3
Data = 2
P_ADCLK
P_RG
Fig ure 13 2 Divided Mo d e, 1/4 Phase Select (Valid at D15 = 0 of address H’F8)
H1
Data = 5
Data = 2
Data = 3
Data = 4
Data = 1
Data = 0
P_SP1
P_SP2
H1
Data = 0
Data = 3
Data = 4
Data = 5
Data = 2
Data = 1
P_ADCLK
P_RG
Fig ure 14 3 Divided Mo d e, 1/6 Phase Select (Valid at D15 = 1 of address H’F8)
Default Value of Each Phases
P_SP1 P_SP2 P_ADCLK P_RG
2 divided mode 1 2 1 0
3 divided mode 0 3 1 5
Note: 50% of duty pulse mak es tr, tf of RG by DLL.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 22 of 28
Address STD1[7:0] (L) STD2[15:8] (H)
11110110 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8
DL_SP2 DL_SP1
DL_RG_f DL_RG_r
DL_ADCLK
CDS_test
Address STD1[7:0] (L) STD2[15:8] (H)
11110111 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8
Dummy
clamp th
Dummy
clamp current
(3) Setting method of DLL
28140
1.
2.
3.
42
∗Default
56
10
H1
DLL step decides the how many divide the 1
cycle of sensor CLK. For reference,
set 1 ns(when 2 ns DLL_current bit = 0,
when 1 set to 1 ns)
Can be set 16 to 64 steps by 4 steps.
Steps = 4 + (4 × N); possible to set N = 3 to 15
Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps)
when 14 to 22MHz: H'09(40 steps)
when 22 to 50MHz: H'1E(60 steps)
when 50 to 72MHz: H'19(40 steps)
Can be change each 4 type of pulse 0 to 15 steps with
1 step. (1 ns or 2 ns divide)
Select the 2 ns divide when sensor CLK is less than
15 MHz.
DL_RG
DL_SP1
DL_ADCLK
DL_SP2
DL_ADCLK
DLL_C
Control voltage
P_ADCLK
AND
PC
DLL = 64 steps
ADCLK(0)
(In phase with H1)
DLL = 15 steps
DL_SP1
P_SP1 DLL = 15 steps
DL_SP2
(Falling)
(Rising)
P_SP2 DLL = 15 steps
ADCLK
(0, 0)
DL_RG
DLL = 15 steps
Figure 15 Analog Delay (DLL) Circ uit Bl o c k.
• CDS _test (D12 of address H’F6)
It is testing data. Normally set to 0.
• Dummy clamp current (D9 to 8 of address H ’F7)
Data = When 0, 1/4 W hen 1, 1/8
When 2, 1/ 16 When 3, 1/32
Details are refer to page 13.
• Dummy cla mp threshold (D12 to 10 of address H’F 7)
Data = When 0, off W hen 1, +32
When 2, +64 When 3, +96
When 4, +128 When 5, +160
When 6, +192 When 7, +224
Details are refer to page 13.
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 23 of 28
Operation Sequence at Power On
V
DD
(1) Resistor transfer of TG part
(2) DLL data transfer of CDS part
(3) Reset=L of CDS part
(4) Reset=H of CDS part
(5) Other data of CDS part
: Wait more than 6clk after release the hardware Reset and then transfer
the necessary data to TG part.
: Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part.
: Transfer Reset bit = 0 of address H'F2.
: Transfer Reset bit = 1 of address H'F2. (Reset release)
: Transfer the SH_SW_fsel and other PGA.
CLK_in
Hardware
Reset
3clk or more
6clk or more
(1)
2ms or more
(Charge of external C)
40,000ADCLK or more
(offset calibration)
(2) (3) (4)
CDS_Reset = Low
(5)
Note: At 2 divided mode: ADCLK = 1/2CLK_in
At 3 divided mode: ADCLK = 1/3CLK_in
SP1
SP2
ADCLK
OBP
etc.
RESET bit
Automatic adjustment taking
40,000ADCLK period after
Reset cancellation
∗Before transfer the Reset bit = 0, TG series pulse need to be settled, so address
H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance.
HD49351
serial data transfer
Must be stable within the operating
power supply voltage range
Start control
of TG and
camera DSP
A
utomatic offset
calibration
The following describes the above serial data transfer. For details of resistor settings are referred to serial data
function table.
Figure 16 Operation Sequence at Power On
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 24 of 28
Timing Specifications of High Speed Pulse
two
twhtr
twl
twl
tf
50%
50%
t
H1DL
90%
10%
90%
10%
H2
RG
• H1, H2, RG waveform
H1
tftwhtr
Item
H1/H2
RG
XV1 to 4
CH1 to 4
XSUB/SUB_SW
min
14
7
—
—
—
typ
20
10
—
—
—
twh
max
—
—
—
—
—
min
14
—
—
—
—
typ
20
37
—
—
—
twl
max
—
—
—
—
—
min
—
—
—
—
—
typ
8.0
4.0
20
20
20
tr
max
14
—
—
—
—
min
—
—
—
—
—
typ
8.0
4.0
20
20
20
tf
max
14
—
—
—
—
165 pF
15 pF
15 pF
15 pF
15 pF
Load
capacitance
Unit
ns
ns
ns
ns
ns
Item
H1/H2 overlap
min
12
typ
20
two Power supply specification of H1, H2, RG are 3.0 V to 3.3 V.
Values are sensor CLK = when 18 MHz.
max
—
Unit
ns
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 25 of 28
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity .
2. This product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to
prevent latchup, a c eramic capacitor of 0.1 µF or more and a n electrolytic capa citor of 10 µF or more should be
inserted betw e en the groun d and powe r supply.
4. Common conne ction of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise fi lter,
the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure
below.
HD49351
AV
SS
DV
SS
AV
DD
DV
DD
1 to 4
Noise filter
A
nalog
+3.0V
HD49351
DV
SS
AV
SS
DV
DD
1 to 4 AV
DD
100 µH
0.01 µF
Noise filter Example of noise filte
r
Digital
+3.0V
0.01 µF
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system
set grounds, connec t to the analog system.
7. When VDD is spec ified in the data sheet, this indic ates AVDD and DVDD.
8. No Connection (NC) pins are not con nected inside the IC, but it is rec ommended that they be con nected to power
supply or ground pins or l eft open to prevent crosstalk in adjacent analog pins.
9. To ensure low therma l resistance of the package, a Cu-type lead material is used. As this material is less tolerant of
bending than Fe-type lead material, careful handling is necessary.
10. The infrared refl ow soldering method should be used to mount the chip. Note that general heating methods such as
solder dipping cannot be used.
11. Serial communication should not be performed during the effective video period, since this will result in degraded
picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD4 9330AF. If ports are to be share d with another IC, picture quality should first be thoroughly ch ecked.
12. At power-on, automatic adjustment of the offset v oltage generated from PGA, ADC, etc., must be implemented in
accordance with the power-on operating sequence (see page 23).
13. Ripple noise of DC/D C converter which gener ates the voltage of ana log part should set under –50 d B with power
supply voltage .
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 26 of 28
Example of Recommended External Circuit
• Slave mode
Pin 57(Test1 = Low)
31
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
33
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
24 23 22 21 20 19 18 1725262728293032
50 57 58 59 60 61 62 63 6456555453525149
HD49351
1µ
1µ0.147/6 47/6
1000p 100p
+
XV4
CH1
CH2
CH3
CH4
XSUB
SUB_SW/ADCK_in
SUB_PD
STROB/Vgate
DV
SS
3
AV
SS
ADC_in
BIAS
VRB
VRT
VRM
HD_in
CLK_in
DV
SS
3
DV
DD
2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DV
SS
1,2
ID
XV2
XV1
DV
DD
3
DV
DD
4
1/4clk_o
H2A
DV
SS
4
DV
SS
4
1/2clk_o
H1A
DV
DD
4
DV
DD
3
RG
Reset
BLKC
CDS_in
AV
DD
BLKFB
BLKSH
AV
SS
Test2
Test1
DLL_C
DV
DD
1
MON
41pin_cont
CS
Sdata
XV3 VD_in
AV
DD
SCK
0.147/6
0.1
0.1
0.1
0.1
3.0V Reset(Normally Hi)
Reset(Normally Hi)
to CCD
+
+
0.1
33k
to CCD
to CCD
ID pulse
ID pulse
to V.Baff
47µ
47µ
47µ
• Master mode
Pin 57(Test1 = Hi)
31
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
33
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
24 23 22 21 20 19 18 1725262728293032
50 57 58 59 60 61 62 63 6456555453525149
HD49351
1µ
1µ0.147/6 47/6
1000p 100p
+
XV4
CH1
CH2
CH3
CH4
XSUB
SUB_SW/ADCK_in
SUB_PD
STROB/Vgate
DV
SS
3
AV
SS
ADC_in
BIAS
VRB
VRT
VRM
HD_in
CLK_in
DV
SS
3
DV
DD
2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DV
SS
1,2
ID
XV2
XV1
DV
DD
3
DV
DD
4
1/4clk_o
H2A
DV
SS
4
DV
SS
4
1/2clk_o
H1A
DV
DD
4
DV
DD
3
RG
Reset
BLKC
CDS_in
AV
DD
BLKFB
BLKSH
AV
SS
Test2
Test1
DLL_C
DV
DD
1
MON
41pin_cont
CS
Sdata
Unit: R: Ω
C: F
XV3 VD_in
AV
DD
SCK
0.147/6
0.1
0.1
0.1
0.1
CCD signal input
CCD signal input
3.0V
to CCD
+
+
0.1
33k
∗ Pin 61 = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
Pin 61 = Hi: Pin 41 is Vgate output
Pin 39 is Hiz
∗ Pin 61 = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
Pin 61 = Hi: Pin 41 is Vgate output
Pin 39 is Hiz
to V.Baff
47µ
47µ
47µ
∗ Pin 56 = Low: TESTIN mode. Please do not use.
Low
Hi
Pin 57
Slave mode
Master mode
Mode
CLK, HD, VD input from SSG.
HD, VD output
Specification
Serial data input
Serial data input
from
Pulse generator
from
Pulse generator
to
Camera
signal
processor
to
Camera
signal
processor
to
Camera
signal
processor
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 27 of 28
• CDS single operating mode
Pin 56(Test2 = Low) ∗Pin 57 is "Don't care" in this mode.
Serial data when CDS single operation mode are following resister specifications.
(Latch timing specification is same as normal mode)
31
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
33
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
24 23 22 21 20 19 18 1725262728293032
50 57 58 59 60 61 62 63 6456555453525149
HD49351
1µ
1µ0.147/6 47/6
1000p 100p
+
PBLK
OBP
CP_DM
ADCK
SP2
SP1
DV
SS
3
AV
SS
ADC_in
BIAS
VRB
VRT
VRM
DV
SS
3
DV
DD
2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DV
SS
1,2
DV
DD
3
DV
DD
4
DV
SS
4
DV
SS
4
DV
DD
4
DV
DD
3
Reset
BLKC
CDS_in
AV
DD
BLKFB
BLKSH
AV
SS
Test2
Test1
DLL_C
DV
DD
1
MON
41pin_cont
CS
Sdata
Unit: R: Ω
C: F
AV
DD
SCK
0.147/6
0.1
0.1
0.1
0.1
3.0V Reset(Normally Hi)
+
+
0.1
33k
∗
Pin changes are not effective with pin 61.
ADC_in
47µ
47µ
47µ
tINT2
fsck
tsu
CS
SCK
tho
tINT1
SDATA
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
D00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
1
1
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
D01
Low
Low
Low
High
Low
Low
Low
High
Low
X
High
High
Low
Low
Low
High
High
Low
High
Low
High
High
High
High
High
Resister 4Resister 3Resister 0 Resister 1 Resister 7Resister 5 Resister 6Resister 2
D02
Test_I1 (0)
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15 Test_I1 (2)
Test_I1 (1)
PGA(0) LSB
X
SLP
Reset
ADSEL
Low:CDSin
High:ADin
LoPwr
STBY
PGA(1)
X
PGA(2)
PGA(3)
PGA(4)
PGA(5)
PGA(6)
PGA(7) MSB
SHSW-fsel(3)
Test_I2 (1)
Test_I2 (0)
Output mode(LINV)
Output mode(MINV)
Output mode(Test0)
SHA-fsel(0)
SHA-fsel(1)
SHSW-fsel(0)
SHSW-fsel(1)
SHSW-fsel(2)
MON(0)
MON(1)
Gray_ts(0)
Gray_ts(2)
Gray_ts(1)
MON(2)
H12Baff(0)
H12Baff(1)
H12Baff(2)
H12Baff(3)
VD latch
Gray1
Gray2
P_SP1(0)
P_SP1(1)
DLL_CK(2)
DLL_current
DLL_CK(3)
P_SP2(0)
P_SP2(1)
P_ADCLK(0)
P_ADCLK(1)
P_RG(0)
P_RG(1)
DLL_CK(0)
DLL_CK(1)
DL_SP1(0)
DL_SP1(1)
DL_ADCLK(2)
CDS_test
DL_ADCLK(3)
DL_SP1(2)
DL_SP1(3)
DL_SP2(0)
DL_SP2(1)
DL_SP2(2)
DL_SP2(3)
DL_ADCLK(0)
DL_ADCLK(1)
DL_RG_r(0)
DL_RG_r(1)
Dummy CP(0)
Dummy CP(2)
Dummy CP(1)
DL_RG_r(2)
DL_RG_r(3)
DL_RG_f(0)
DL_RG_f(1)
DL_RG_f(2)
DL_RG_f(3)
DMCG(0)
DMCG(1)
Clamp(0)
Clamp(1)
Clamp(2)
Clamp(3)
Clamp(4)
HGstop-Hsel(0)
HGstop-Hsel(1)
HGain-Nsel(0)
HGain-Nsel(1)
test
CCD signal input
Serial data input
to
Camera
signal
processor
Low: Normal
High: Sleep
Low: Normal
High: Standby
Low: Normal
High: Low power
Low: Reset
High: Normal
HD49351BP/HBP
Rev.1.0, Jul 06, 2004, page 28 of 28
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
TFBGA0606-65
—
—
0.056 g
Unit: mm
6.00
6.00
Details of the part A
0.20 S
0.20 S A
0.20 S B
0.75
0.75
B
0.50 × 9 = 4.50
0.50 × 9 = 4.50
0.50
A
0.25 ± 0.05
0.08 S
1.20 Max
S
0.15
×4
A area
Index Pin
K
J
H
G
F
E
D
C
B
A
S
φ0.05 AB
65 – φ0.30 ± 0.05
M
2345768910 1
0.50
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