DM9370N - Fairchild Semiconductor

October 1988

Revised March 2000

DM9370 7-Segment Decoder/Driver/Latch with Open-Collector Outputs

DM9370

7-Segment Decoder/Driver/Latch

with Open-Collector Outputs

General Descript ion

The DM9370 is a 7-segment decoder driver incorporating

input lat ches and o utput cir cuits to di rectly drive incandes-

cent di splays. It c an also be use d to driv e common anode

LED displays in either a multiplexed mode or directly with

the aid of external current limiting resistors.

Ordering Code:

Connection Diagram Logic Symbol

VCC = Pin 16

GND = Pin 8

Pin Descriptions

Order Number Package Number Package Description

DM9370 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

A0–A3 Address Inputs

LE Latch Enable Input (Active LOW)

RBI Ripple Blanking Input (Active LOW)

RBO Ripple Blanking as Output (Active LOW)

as Input (Active LOW)

a–g Segment Outputs (Active LOW)

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DM9370

Truth Table

*The RBI will blank the dis play on ly if b inary zero is st ored in th e lat c hes.

**RBO used as an input ov erdrives all ot her input conditions.

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Immaterial

Functional Description

The DM9370 has active LOW outputs capable of sinking in

excess of 25 mA which allows it to drive a wide variety of 7-

segment incandescent displays directly. It may also be

used to drive common anode LED d isplays, multiplex ed or

directly with the aid of suitable current limiting resistors.

This device accepts a 4-b it binary code a nd produces ou t-

put drive to the appropriate segments of the 7-segment dis-

play. It has a hexadecimal decode format which produces

numeric codes “0” through “9” and alpha codes “A” through

“F” using upper and lower case fonts.

Latches on the fo ur dat a input s are c ontr olled b y an ac tive

LOW latch enable LE. When the LE is LOW, the state of

the outp uts is determined by the input data. When the LE

goes HIGH, the last data present at the inputs is stored in

the latches and the outputs remain stable. The LE pulse

width necessary to accept and store data is typically 30 ns

which allows data to be strobed into the DM9370 at normal

TTL speeds. This feature means that data can be routed

directly from high speed counters and frequency dividers

into the display without slowing down the system clock or

providing intermediate data storage.

The latch/decoder combination is a simple system which

drives incandescent displays with multiplexed data inputs

from MOS time clocks, DVMs, calculator chips, etc. Data

inputs are multiplexed while the displays are in static mode.

This lowers component and insertion costs since several

circuits—seven diodes per display, strobe drive rs, a sepa-

rate display voltage source, and clock failure detect cir-

cuits—traditionally found in incandescent multiplexed

display sys tems are elim inated. It also al lows low strob ing

rates to be used without display flicker.

Another DM9370 feature is the reduced loading on the

data inputs when the Latch Enable is HIGH (only 10 µA

typ). This allows many DM9370s to be driven from a MOS

device in multiplex mode without the need for drivers on

the data lines. The DM9370 also provides automatic blank-

ing of the leading and/or trailing-edge zeroes in a multidigit

decimal number, resulting in an easily readable decimal

display co nforming to no rmal writing p ractice. In an 8- digit

mixed integer fraction decimal representation, using the

automatic blanking capability, 0060.0300 would be dis-

played as 60.03. Leading-edge zero suppression is

obtaine d by connecting the Ripple Blan king Output (R BO)

of a decoder t o t he Rippl e Blan king Input (RBI) of the next

lower stage device. The most significant decoder stage

should have the RBI input grounded; and since suppres-

sion of th e least signif icant intege r zero in a n umber is not

usually desired, the RBI input of this deco der stag e should

be lef t o pen . A similar pro ced ur e for the fracti ona l p art of a

display will provide automatic suppression of trailing-edge

zeroes. The RBO termina l of the decoder can be OR-tied

with a modulating signal via an isolating buffer to achieve

pulse duration intensity modulation. A suitable signal can

be generated for this purpose by forming a variable fre-

quency multivibrator with a cross coupled pair of TTL or

DTL gates.

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DM9370

Numerical Designation

Logic Diagram

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DM9370

Absolute Maximum Ratings(No te 1) Note 1: The “A bsolute Maxim um Ratings ” are those valu es beyond w hich

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not gua rant eed at the absolute maximum rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typic als are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time.

Switching Characteri stics

VCC = +5.0V, TA = +25°C

Supply Voltage 7V

Input Voltag e 5.5 V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −80 µA

IOL LOW Level Output Current 3.2 mA

TAFree Air Operating Temperature 0 70 °C

tS (H) Setup Time HIGH or LOW 30 ns

tS (L) An to LE 20

tH (H) Hold Time HIGH or LOW 0 ns

tH (L) An to LE 0

tW (L) LE Puls e Wid th LOW 45 ns

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II = −12 mA −1.5 V

VOH HIGH Level VCC = Min, I OH = Max 2.4 3.4 V

Output Voltage VIL = Max

VOL LOW Level VCC = Min, IOL = Max 0.2 0.4 V

Output Voltage VIH = Min

IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 m A

IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −70 mA

VOH Output HIGH Voltage RBO VCC = Min, I OH −80 µA2.4 V

VOL Output LOW Voltage RBO IOL = 3.2 mA VCC = Min 0.4 V

a–g IOL = 25 mA 0.4

IOH Output HIGH Current, a–g 250 µA

ICC Powe r Supply Cu rre nt VCC = Max 105 µA

A1, A2, A3, LE = GND 105

VCC = Max, Outputs OPEN

A0, A1, A2, LE = GND 94

VCC = Max, Outputs OPEN

Symbol Parameter CL = 15 PF, RL = 500ΩUnits

Min Max

tPLH Propagation Delay 75 ns

tPHL An to a–g 50

tPLH Propagation Delay 90 ns

tPHL LE to a–g 70

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DM9370 7-Segment Decoder/Driver/Latch with Open-Collector Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described , no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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