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Features

• Configuration one-time prog rammabl e (O TP) read-only

memory designed to store configuration bitstreams of

Xilinx FP GA d evice s

• Simple interface to the FPGA ; requires only one user

I/O p i n

• Cascadable for storing longer or multiple bitstreams

• Programmable reset pola rity (active High or active

Low) for c om patibility with different FPGA solutions

• Supports XQR4000 XL/Virtex fast configuration mod e

(15.0 MHz) (XQR1701L and XQR1704L)

• Supports XQ4000EX /XL fast configuration mode

(15.0 MHz) (XQ17 01L and XQ1704L)

• Fabricated on Epi taxial Silicon to improve latch

perfor m ance (parts are immune to Single Event

Latch-up) (XQR1 701L and XQR1704L)

•QML certified

• Single Event Bit Upset immune (XQR1701 L and

XQR1704L)

• Total Dose tolerance in excess of 50K rads(Si)

(XQR1701L and XQR1704L)

• All lots subjected to TID Lot Qualification in accordance

with method 1019 (dose rate ~9.0 rads(S i)/sec)

(XQR1701L and XQR1704L)

• Available in 44-pin cera mi c LCC (M grade ) package

• Available in 44-pin plastic chip ca rr ier package

(XQ1704L only)

• Available in 20-pin SOIC package (XQ1701L onl y)

• Programming support by leading programmer

manufacturers.

• Design support using the Xilinx Alliance and

Found ation ser ies software packages.

Description

The QPRO™ series XQ1701L and XQ1704L are Xilinx

3.3V high-density configuration PROMs. The XQR1701L

and XQ R1704L are radiation hardened. These devices are

manufactured on Xilinx QML certified manufacturing lines

utilizing epitaxial substrates and TID lot qualification (per

method 1019).

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

DATA output pin that is connected to the FPGA DIN pin. The

FP GA generate s the ap propri ate number of clock pulses to

complete the configuration. Once configured, it disabl es the

PROM. When the FPGA is in Slav e Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

Figure 1 shows a simplied block diagra m.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded wit h other members of the family.

Fo r device programmi ng, either the Xilinx Alliance or Foun-

dation series development system compiles the FPGA

design f ile into a s tan dard Hex for mat, which is then trans-

ferred to most commerc ial PROM programmers.

0QPRO Series Configuration

PROMs (XQ) including

Radiation -Hardened Series (XQR)

DS062 (v2.0) June 1, 2000 02Advance Product Specification

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

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1-800-255-7778 Advance Product Specification

Pin Description

DATA

Data output is in a high-impedance state when either CE or

OE are inactive. Dur ing programming, the DATA pin is I/O.

Note that OE can be progr ammed to be ei ther active Hi gh or

active Low.

CLK

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

RESET/OE

When High, t his input hol ds the ad dress counter res et and

puts the DATA output in a high-impedanc e state. The polar-

ity of this input pin is progr ammable as either RESET/OE or

OE/RESET. To avoid confusion, this document describes

th e pin as RESET/OE, although the opposite polarity is pos-

sible on all devices. When RESET is active, the address

counter is held at "0", and puts the DATA output in a

high-impedanc e sta te. The polarity of this input is program-

mable. The default is active High RESET, but the preferred

option is active Low RE SET, because it can be driven by the

FPGA s INIT pin.

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx

HW-130 Programmer. Third-party programmers have differ-

ent methods to invert this pin.

When High, this pin disables the internal address counter,

puts the DATA output in a high-impedance state, and f orces

the device into low-ICC standby mode.

CEO

Chip Enable output, to b e con nected to the CE input of the

next PROM i n the daisy chain. This out put is Low when the

CE and OE inputs are both active AND the inte rnal address

counter has been incremented beyond its Terminal Count

(TC) value. In other words: when the PROM has been read,

CEO wi ll follo w CE as lon g as OE is acti ve. When OE goes

i n a c tive , C EO sta ys High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

VPP

Programming voltage. No overshoot above the specified

max voltage is per m it ted on this pin. For norma l read oper-

ation, this pin must be connected to VCC. Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debug ging. Do not le ave

VPP floating!

VCC and GND

Positive su pply and groun d pins.

Figure 1: Simplified Block Diagram (does not show program ming circuit)

EPROM

Cell

Matrix

Address Counter

DATA

Output

CLK

VCC VPP GND

DS027_01_021500

RESET/

OE/

RESET

or CEO

QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)

DS062 (v2.0) June 1, 2000 www.xilinx.com 3

Advance Product Specification 1-800-255-7778

PROM Pinouts

Capacity

Xilinx FPGAs and Compatible PROMs.

Controlling PROMs

Connecting the FPGA device with the PROM.

•The DATA output(s) of the of the PROM(s) drives the

DIN input of the lead FPGA device.

•The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s).

•The CEO o utput of a PROM dr ives the CE input of t he

next PROM in a daisy chain (if any).

•The RESET/OE input of all PROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration, even

when a reconfiguration is initiated by a VCC glitch.

Other methods—suc h as dr iving RESET /O E fr om LD C

or system reset—assume the PROM internal

power-on-reset is always in step with the FPGAs

internal power-on-reset. This may not be a safe

assumption.

•The PROM CE input can be driven from either the LDC

or DONE pins. Using LDC avoids potential contention

on the DIN pin.

•The CE input of the lead (or only) PROM is driven by

the DONE output of the lead FPGA device, provided

that DONE is not permanently grounded. Otherwise,

LDC can be used to drive CE, but must then be

unconditionally High during user operation. CE can

also be pe rmane ntly tied Low, but this keeps the DATA

output active and causes an unnecessary supply

current of 10 mA maximum.

FPGA Master Serial Mode Summary

The I /O and logic func tions of the Configurable Log ic Block

(CLB) and their associated interconnections are established

by a configuration program. The program is loaded either

automatically upon power up, or on command, depending

on the stat e of the three F PG A mode pins. In Master Seria l

mode, the FPGA automatically loads the configuration pro-

gram from an external memory. The Xilinx PROMs have

been designed for compatibility with the Master Serial

mode.

Upon power-up or reconfiguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA

mode-select pins are Low (M0=0, M1=0, M2=0). Data is

read from the PROM sequentially on a single data line. Syn-

chronization is provided by the rising edge of the temporary

signal CCLK, which is generated during configuration.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line and two control lines are

required to configure an FPGA. Data from the PROM is

read sequenti ally, accessed via the internal address and bit

coun ters which a re incremented on ever y valid risin g edge

of CCLK.

If the user-programmable, dual-function DIN pin on the

FPGA is used only for configuration, it m ust still be held at a

defined level during normal operation. The Xilinx FPGA

families take care of this automatically with an on-chip

default pull-up resistor.

Pin Name 44-Pin CLCC

DATA 2

CLK 5

RESET/OE (OE/RESET)19

CE 21

GND 3, 24

CEO 27

VPP 41

VCC 44

Devices Co nf i gu ra ti on B i ts

XQR1704L 4,194,304

XQR1701L 1,048,576

XQ1704L 4,194,304

XQ1701L 1,048,576

Device Configuration Bits PROM

XQR4013XL 393,632 XQ1701L

XQR4036XL 832,528 XQ1701L

XQR4062XL 1,433,864 XQ1704L

XQR4013XL 393,632 XQR1701L

XQR4036XL 832,528 XQR1701L

XQR4062XL 1,433,864 XQR1704L

XQVR300 1,751,840 XQR1704L

XQVR600 3,608,000 XQR1704L

XQVR1000 6,127,776 XQR1704L x 2

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

4www.xilinx.com DS062 (v2. 0) June 1, 2000

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Programming the FPGA With Counters

Unchanged Upon Completion

When multiple FPGA-configurations for a single FPGA are

stored in a PROM, the OE pin should be tied Low. Upon

power-up, the inter nal address counters are reset and con-

figuration begins with the first program stored in memory.

Since the OE pin is held Low, the address c oun ters are left

unchanged after configuration is complete. Therefore, to

reprogram the FPGA with another program , the DONE l ine

is pulled Low and configuration begins at the last value of

the address counters.

This method f ails if a user applies RESET during the FPGA

configuration process. The FPGA aborts the configuration

and then re star ts a new configuration, as intended , but the

PROM does not reset its address counter, since it never

saw a High level on its OE input. The new configuration,

therefore, reads the rema ining data in the PROM and inter-

prets it as preamble, length count etc. Since the FPGA is

the master , it issues the necessary number of CCLK pulses,

up to 16 million (224) and DONE goes High. However, the

FPGA configuration will be completely wrong, with potential

contentions inside the FPGA and on its output pins. This

method must, therefore, never be used when there is any

chance of external reset during configuration.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or for

future FPGAs requiring larger configuration memories, cas-

cade d PROM s provide additiona l memory. After the last bit

from the first PROM is read, the next clock signal to the

PROM asserts its CEO output Low and disables its DATA

line. The second PROM recognizes the Low level on its CE

input and enables its DATA output. See Figure 2.

After configuration is complete, the address counters of all

cascaded PROMs are reset if the FPGA RESET pin goes

Low, assuming the PROM reset polarity option has been

inverted.

To reprogram the FPGA with another program, the DONE

line g oes Low and c onfiguration begins where the address

counters had stopped. In this case, avoid contention

between DATA and the configured I/O use of DIN.

QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)

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Advance Product Specification 1-800-255-7778

Figure 2: Master Serial Mode. The one-time-programmable PR OM supports automatic loading of configuration programs.

Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK

cycle before the FPGA I/Os become a ctive.

DIN

DOUT

CCLK

INIT

DONE

PROM

DATA

CLK

CE CE

FPGA

(Low Resets the Address Pointer)

* For mode pin connections,

refer to the appropriate FPGA data sheet.

Vcc

VCC

OPTIONAL

Daisy-chained

FPGAs with

Different

configurations

OPTIONAL

Slave FPGAs

with Identical

Configurations

RESET RESET

DS027_02_060100

CCLK

(Output)

DIN

DOUT

(Output)

OE/RESET

MODES*

VPP

Cascaded

Serial

Memory

DATA

CLK

CEO

OE/RESET

3.3V

4.7K

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

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Standby M ode

The PROM enters a low-pow er standby mode whenev er CE

is asser ted High. The output remains in a high-impedance

state regardless of the state of the OE input.

Programming

The devices ca n be programmed on programm ers supplied

by Xilinx or qualified third-party vendors. The user must

ensure that the appropriate programming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently dam age the device.

Radiation Characteristics (XQR1701L and XQR1704L only)

Table 1: Truth Table for Control Inputs

Cont r ol Inputs

Internal Address

Outputs

RESET CE DATA CEO ICC

Inactive Low If address < TC(1): increment

If address > TC(1): don’t change Active

High-Z High

Low Active

Reduced

Active L ow He ld reset High-Z High Active

Inactive High Not changing High-Z High Standby

Active H igh Held reset High-Z High Standby

Notes:

1. The XC1700 RESET input has programm able pola rit y

1. TC = Termina l Count = highest addres s value. TC + 1 = address 0.

Symbol Description Min Max Units

TID To tal ionizing dose, Method 1019 50K rads(Si)

SEL Single event latc h-up.

Heavy ion saturation cross section, LET1 > 120 MeV cm2/mg 0(cm

2/Device)

SEU Sing le event bit up se t.

Heavy ion sa tura tion cross secti o n

LET > 120 MeV cm2/mg

0(cm

2/Bit)

SEFI2Single event fun ction al interupt,

Heavy ion saturation cross section,

10% saturated intercept at LET = 6.0 MeV cm2/mg

1.2e-5 (cm2/Device)

Notes:

1. Single Event Effects testing was perform ed with heavy ion to a m aximum LET of 120 MeV-cm2/mg.

2. For more information on Single Event Effects and mitigation methods refer to Xilinx Application Note XAPP185 “Space Application

Design techniques for the XQR1700L QPRO Series Radiation Hardened Serial PROMs.”

QPRO Series Configuratio n PROMs (XQ) including Radiation-Hardened Series (XQR)

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Absolute Maximum Ratings

Operating Conditions

DC Char ac te ri sti cs Ove r Op er at ing Con ditio n

Symbol Description Conditions Units

VCC Suppl y voltage relative to GND –0.5 to +4.0 V

VPP Supply volt age relative to GND –0 .5 to +12.5 V

VIN Input voltage relativ e to GND –0.5 to VCC +0.5 V

VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Max imum solder ing tempe rature (10s @ 1/16 in.) +260 °C

Notes:

1. Stresses beyond those l isted under Abs olute Maximum Ratings may cause permanent damage to the device. These are s tr ess

ratings onl y, and functional operation of the devi ce at these or any other conditions bey ond those list ed under Operating Conditions

is not imp lied. Exposure to Absolute Maxim um Ratings conditions for extended periods of time may affec t device reliab il ity.

Symbol Description Min Max Units

VCC(1) Supply voltage relative to GND

ceramic package (TC = –55°C to +125°C) Military 3.0 3.6 V

Notes:

1. During normal read operatio n VPP MUST be connect t o VCC.

Symbol Description Min Max Units

VIH High-level input voltage 2 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-lev el output voltage (IOH = –3 mA) 2.4 - V

VOL Lo w-le vel output voltage (IOL = +3 m A) - 0.4 V

ICCA Supply current, active mode (a t maximum frequen cy) - 10 mA

ICCS Supply current, standby mode (XQ1701L, XQ1704 L) - 100 µA

ICCS(1) Supply c urrent, standby mode

(XQR1701L and XQR 1704L) Pre-rad (TID) - 300 µA

Post-rad (TID) - 3 mA

ILInput or outp ut leakage current –10 10 µA

CIN Input capacitance (VIN = GND, f = 1.0 MHz) - 10 pF

COUT O utput capaci tance (V IN = GND, f = 1.0 MH z) - 10 pF

Notes:

1. ICCS, Standby Current is measured at +125°C f or pre-radiation specifications and at room temperatur e for post-rad iation

specifications.

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

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AC Characteristics Over Operating Condition

Symbol Description

XQR1701L XQ1701L,

XQR1704L

UnitsMin Max Min Max

TOE OE to data delay - 25 - 30 ns

TCE CE to data delay - 45 - 45 ns

TCAC CLK to data d elay - 45 - 45 ns

TDF CE or O E to data float delay(2,3) - 50 - 50 ns

TOH Data hold from CE , OE, or C L K(3) 0-0-ns

TCYC Clock periods 67 - 67 - ns

TLC CLK Low time (3) 20 - 25 - ns

THC CLK High time(3) 20 - 25 - ns

TSCE CE setup time to CLK (to guarantee proper counting) 20 - 25 - ns

THCE CE hold tim e to CLK (to guarantee proper counting) 0 - 0 - ns

THOE OE hold time (guarantees counte rs are reset) 20 - 25 - ns

Notes:

1. A C test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measur ed wit h VIL = 0.0V and VIH = 3.0V.

RESET/OE

CLK

DATA TCE

TOE

TLC

TSCE TSCE THCE

THOE

TCAC TOH TDF

TOH

THC

DS027_03_021500

TCYC

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AC Characteristics Over Operating Condition When Cascading

Symbol Description Min Max Units

TCDF CLK to data float delay(2,3) -50 ns

TOCK CLK to CEO delay(3) -30 ns

TOCE CE to CE O delay(3) -35 ns

TOOE RESET/OE to CEO delay(3) -30 ns

Notes:

1. A C test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measur ed wit h VIL = 0.0V and VIH = 3.0V.

RESET/OE

CLK

DATA

TOOE

CEO

First Bit Last Bit

TOCE

TOCK

TCDF

DS027_04_021500

TOCE

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Ordering Information

Valid Ordering Combinations

Revision History

The following table shows the revision histor y for this document .

XQR1704LCC44M XQR1701LCC44M XQ1701LCC44M XQ1704LCC44M

XQ1701LCC44B XQ1704LCC44B

XQ1701LSO20N XQ1704LPC44N

XQR1701L CC44 M

Opera t ing Range/ P rocessing

B = Military(TC = –55° to +1 25°C)

QML certified to MIL-PRF-38535

M = Military (TC = –55° to +12 5 °C)

QML certified to MIL-PRF-38535

N = Military Plastic (TJ = –55° to +125°C)

Dev ice Num ber

XQ1704L

XQ1701L

XQR1704L

XQR1701L

Package T ype

CC44 = 44-pin Ceramic Chip Carrier

SO20 = 20-pin Plastic Small Outline Package

PC44 = 44-pin Plastic Chip Carrier

Date Version Revision

04/20/00 1.0 Initial Release

06/01/00 2.0 Com bined XQR17 00L Rad-Hard and X Q1701 L devices, added XQ1704L and updat ed

format.