5345A–HIREL–11/03
Features
•3000 Dhrystone 2.1 MIPS at 1.3 GHz
•Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
•13 Selectable Core-to-L3 Frequency Divisors
•Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
•Selectable L3 Interface of 1.8V or 2.5V
•PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating
Conditions
•Nap, Doze and Sleep Modes for Power Saving
•Superscalar (Four Instructions Fetched Per Clock Cycle)
•4 GB Direct Addressing Range
•Virtual Memory: 4 Hexabytes (252)
•64-bit Data and 32-bit Address Bus Interface
•Integrated L1: 32 KB Instruction and 32 KB Data Cache
•Integrated L2: 512 KB
•11 Independent Exec ution Units and Three Register Files
•Write-back and Write-thro ugh Operations
•fINT Max = 1 GHz (1.3 GHz to be Confirmed)
•fBUS Max = 133 MHz/166 MHz
Description
This document is primarily concer ned with the PowerPC™ PC7457; however, unless
otherwise noted, all information here also applies to the PC7447. The PC7457 and
PC7447 are implementations of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the PC7457.
The PC7457 is the four th implementation of the four th generation (G4) microproces-
sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and
is targeted at networking and computing systems applications. The PC7457 consists
of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup-
por t a glueless backside L3 cache through a dedicated high-bandwidth interface. The
PC7447 is identical to the PC7457 except it does not support the L3 cache interface.
The core is a high-perfor mance superscalar design suppor ting a double-precision
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-
por ts the MPX bus interface to main memory and other system resources. The L3
interface suppor ts 1, 2, or 4M bytes of external SRAM for L3 cache and/or private
memor y data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes
may be used as cache; the remaining 2M bytes must be privat e memory.
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455
application if the core power supply is 1.3V.
PowerPC 7457
RISC
Microprocessor
PC7457/47
Preliminary
Specification
α-site
Rev. 5345A–HIREL–11/03
2PC7457/47 [Preliminary] 5345A–HIREL–11/03
Screening
• CBGA Upscreenings Based on Atmel Standards
• Full Military Temperature Rang e (T j = -55°C, +125°C),
Industrial Temperature Range (Tj = -40°C, +110°C)
• CBGA Package, HiTCE Package for the 7447 TBC
G suffix
CBGA 360
Ceramic Ball Grid Array
GH suffix
HITCE 360
Ceramic Ball Grid Array (TBC)
CBGA 483
3
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Block Diagram
Figure 1. PC7457 Microprocessor Block Diagram
+
Integer
Reservation
Station
Unit 2
+
Integer
Reservation
Station
Unit 2
Additional Features
- Time Base Counter/Decrementer
- Clock Multiplier
- JTAG/COP Interface
- Thermal/Power Management
- Performance Monitor
PA
Instruction Unit Instruction Queue
(12-Word)
96-Bit (3 Instructions)
Reservation
128-Bit (4 Instructions)
32-Bit
FPSCR
FPSCR
+ x ÷
Floating-
Point Unit
64-Bit
Reservation
32-Bit
Completion Unit
Completion Queue
(16-Entry)
32-Kbyte
D Cache
36-Bit 64-Bit
Stations (2)
Station
Reservationv
Stations (2) FPR File
16 Rename
Buffers
Stations (2-Entry)
GPR File
16 Rename
Buffers
Reservation
Station
VR File
16 Rename
Buffers
64-Bit
128-Bit
Completes up
Instruction MMU
SRs 128-Entry
IBAT Array
ITLB Tags 32-Kbyte
I Cache
Vector
Touch
Queue
VR Issue FPR Issue
Branch Processing Unit
CTR
LR
BTIC (128-Entry)
BHT (2048-Entry)
Fetcher
GPR Issue
(6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue)
Dispatch
Unit Data MMU
SRs
(Original) 128-Entry
DBAT Array
DTLB
32-Bit
EA
Status
L2 Store Queue (L2SQ)
Vector
FPU
Reservation
Station
Reservationv
Station
Reservation
Station
Vector
Integerer
Unit 1
Vector
Integerer
Unit 2
Vector
Permute
Unit
Line
Tags Block 0 (32-Byte) Status
Block 1 (32-Byte)
Memory Subsystem
Snoop Push/
Interventions
L1 Castouts
Bus Accumulator
(4)
x ÷
Integer
Unit 2
to three
per clock
instructions
L1 Load Queue (LLQ)
L1 Load Miss (5)
Cacheable Store Request(1)
L1 Service
L1 Store Queue
(LSQ)
L3 Cache Controller(1)
L3CR
StatusTags
Bus Accumulator
Block 0/1
Line
System Bus Interface
L2 Prefetch (3)
64-Bit Data
(8-Bit Parity)
External SRAM Address Bus Data Bus
Queues
Castout
Bus Store Queue
Push
Load
Queue (11)
Queue (9)/
Queue (10)(2)
Notes: 1. The L3 cache interface is not implemented on the PC7447.
2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
512-Kbyte UniÞed L2 Cache Controller
19-Bit Address
(1, 2, or 4 Mbytes)
Tags
Instruction Fetch (2)
128-Bit
Reservation
(Shadow)
+
Load/Store Unit
(EA Calculation)
Finished
Completed
Stores
Stores
Load Miss
L1 Castout
L1 Push
Vector Touch Engine
+
Integer
(3)
Unit 1
4PC7457/47 [Preliminary] 5345A–HIREL–11/03
General Parameters Table 1 provides a summary of the general parameters of the PC7457.
Features This section summarizes features of the PC7457 implementation of the PowerPC archi-
tecture. Major features of the PC7457 are as follows:
• High-performance, superscalar microprocessor
– As many as 4 instructions can be f et ched from the instruction cache at a ti me
– As many as 3 instructions can be dispatched to t he issue queues at a time
– As many as 12 instructions can be in the instruction queue (IQ)
– As many as 16 instructions can be at some stage of execution
simultaneously
– Single-cycle execution for most instructions
– One instruction per clock cycle throughput for most instructions
– Seven-stage pipeline control
• Eleven independent execu tion units and three register files
– Branch processing unit (BPU) features static and dynamic branch prediction
128-entry (32-set, four-way set-associative) branch target instruction cache
(BTIC), a cache of branch instructions that have been encountered in
branch/loop code sequences. If a target instruction is in the BTIC, it is
fetched into the instruction queue a cycle sooner than it can be made
available from the instruction cache. Typically, a fetch that hits the BTIC
provides the first four instructions in the ta rget stream
2048-entry branch history table (B HT) with two b its per entry for four le v els of
prediction – not-taken, strongly not-taken, taken, and strongly taken
Up to three ou tst an d i ng spe c u lative branches
Branch instructions that don’t update the count register (CTR) or link register
(LR) are often removed from the instruction stream
Eight-entry link register stack to predict the target address of Branch
Conditional to Link Register (BCLR) instructions
Table 1. Device Parameters
Parameter Description
Technology 0.13 µm CMOS, nine-layer metal
Die size 9.1 mm × 10.8 mm
Transistor count 58 million
Logic design Fully-static
Packages PC7447: surface mount 360 ceramic ball grid arra y (CBGA)
PC7457: surface mount 483 ceramic ball grid array (CBGA)
Core po wer supply 1.3V ±500 mV DC nominal or 1.1V ±50 mV (nominal, see Table 3 on
page 12
I/O power supply 1.8V ±5% DC, or 2.5V ±5% for recommended operating conditions
5
PC7457/47 [Preliminary]
5345A–HIREL–11/03
– Four integer units (IUs) that share 32 GPRs for integer operands
Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer
instructions except multiply, divide, and move to/from special-purpose
register instructions
IU2 execut es misce lla ne ou s ins tructions inclu din g the CR log i ca l operations,
integer multiplication and division instructions, and move to/from special-
purpose register instructions
– Five-stage FPU and a 32-entry FPR file
Fully IEEE 754-1985-compliant FPU for both single- and double-precision
operations
Supports non-IEEE mode f or time-critical operations
Hardware support for denormalized numbers
Thirty-two 64-bit FPRs for single- or double-precision oper ands
– Four vector units and 32-entry v ector register file (VRs)
Vector permute unit (VPU)
Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer
instructions, such as vector add instructions (vaddsbs, vaddshs, and
vaddsws, for example)
Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer
instructions, such as vector multiply add instructions (vmhaddshs,
vmhraddshs, and vmladduhm, for example)
Vector floating-point unit (VFPU)
– Three-stage load/store unit (LSU)
Supports integer, floating-point, and vector instruction load/store tr affic
Four-entry vector touch queue (VTQ) supports all four architected AltiVec
data stream operations
Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector)
with one-cycle throughput
Four-cycle FPR load latency (single, double) with one-cycle throughput
No additional delay for misaligned access within double-word boundary
Dedicated adder calculates effective addresses (EAs)
Supports store gathering
6PC7457/47 [Preliminary] 5345A–HIREL–11/03
Performs alignment, normalization, and precision conversion for floating-
point data
Executes cache control and TLB instr uc tio ns
Performs alignment, zero padding, an d sign extension for integer data
Supports hits under misses (multiple outstanding misses)
Supports both big- and little-e ndian mo des , includ ing misaligned litt le-endian
accesses
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three
instructions, respectively, in a cycle. Instruction dispatch requires the following:
– Instructions can be dispatched only from the three lowest IQ entries – IQ0,
IQ1, and IQ2
– A maximum of three instructions can be dispatched to the issue queues per
clock cycle
– Space must be available in the CQ for an instruction to dispatch (this
includes instructions that are assigned a space in the CQ but not in an issue
queue)
• Rename buffers
– 16 GPR rename buffers
– 16 FPR rename b uffers
– 16 VR rename buffers
• Dispatch un it
– Decode/dispatch stage fully decodes each instruction
• Completion unit
– The completion unit retires an instruction from the 16-entry completion
queue (CQ) when all instructions ahead of it have been completed, the
instruction has finished execution, and no e xceptions are pending
– Guarantees sequential programming model (precise exception model)
– Monitors all dispatched instructions and retires them in order
– Tracks unresolved branches and flushes instructions after a mispredicted
branch
– Retires as many as three instructions per clock cycle
• Separate on-chip L1 Instruction and data caches (Harvard Arch itecture)
– 32 Kbyte, eight-way set-associative instruction and data caches
– Pseudo least-recently-used (PLRU) replacement algorithm
– 32-byte (eight-word) L1 cache block
– Physically indexed/physical tags
– Cache write-back or write-thr ough ope r ation prog r amma b le on a per -page or
per-block basis
– Instruction cache can provide four instructions per clock cycle; data cache
can provide four words per clock cycle
– Caches can be disabled in softwar e
– Caches can be locked in software
7
PC7457/47 [Preliminary]
5345A–HIREL–11/03
– MESI data cache cohe rency maintained in hard ware
– Separate copy of data cache tags for efficient snooping
– Parity support on cache and tags
– No snooping of instruction cache except for icbi instruction
– Data cache supports AltiVec LRU and transient instructions
– Critical double- and/or quad-word forwarding is performed as needed.
Critical quad-word forwarding is used for AltiVec loads and instruction
fetches. Other accesses use critical double-word forwarding
• Level 2 (L2) cache interface
– On-chip, 512 Kbyte, eight-way set-associative unified instruction and data
cache
– Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
– A total nine-cycle load latency for an L1 data cache miss that hits in L2
– PLRU replacement algorithm
– Cache write-back or write-thr ough ope r ation prog r amma b le on a per -page or
per-block basis
– 64-byte, two-sectored line size
– Parity support on cache
• Level 3 (L3) cache interface (not implemented on PC7447)
– Provides critical double-word forwarding to the requesting unit
– Internal L3 cache controller and tags
– External data SRAMs
– Suppor t for 1, 2, and 4M bytes (MB) total SRAM space
– Suppor t for 1 or 2 MB of cache space
– Cache write-back or write-thr ough ope r ation prog r amma b le on a per -page or
per-block basis
– 64-byte (1 MB) or 128-byte (2 MB) sectored line size
– Private memory capability for half (1 MB minimum) or all of the L3 SRAM
space for a total of 1-, 2-, or 4-MB of private memory
– Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2
pipelined synchronous Burst SRAMs, and pipelined (register-register) Late
Write synchronous Burst SRAMs
– Supports parity on cache and tags
– Configurable core-to-L3 frequency divisors
– 64-bit external L3 data bus sustains 64-bit per L3 cloc k cycle
• Separat e memory management units (MMUs) for Instructions and data
– 52-bit virtual address; 32- or 36-bit physical address
– Address translation for 4 Kbyte pages, variable-sized blocks, and
256M bytes segments
– Memory programmable as write-back/write-through, caching-
inhibited/caching-allowed, and memory coherency enforced/memory
coherency not enforced on a page or block basis
– Separate I BATs and DBATs (eight each) also defined as SPRs
8PC7457/47 [Preliminary] 5345A–HIREL–11/03
– Separate inst ruction and data translation lookaside buffers (TLBs)
Both TLBs are 128-entry, two-way set-associative, and use LRU
replacement algorithm
TLBs are hardware- or software-reloadable (that is, on a TLB miss a page
table search is performed in hardware or by system software)
• Efficient data flow
– Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows
up to 256 bits
– The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the
VRs
– L2 cache is fully pipelined to provide 256 bits per processor clock cycle to
the L1 cache
– As many as eight outstanding, out-of-order, cache misses are allowed
between the L1 data cache and L2/L3 bus
– As many as 16 out-of-order transactions can be present on the MPX bus
– Store merging for multiple store misses to the same line. Only coherency
action taken (address-only) for store misses merged to all 32 bytes of a
cache block (no data tenu re needed)
– Three-entry finished store queue and five-entry completed store queue
between the LSU and the L1 data cache
– Separate additional queues for efficient buffering of outbound data (such as
castouts and write-through stores) from the L1 data cache and L2 cache
• Multiprocessing support features include the following:
– Hardware-enforced, MESI cache coherency protocols for data cache
– Load/store with reservation instruction pair for atomic memory references,
semaphores, and other multiprocessor operations
• Power and thermal management
– 1.6V processor core
– The followin g three power-saving modes are available to the system:
Nap—Instruction fetching is halted. Only those clocks for the time base,
decrementer, and JTAG logic remain running. The part goes into the doze
state to snoop memory operations on the bus and then back to nap using a
QREQ/QACK processor-system handshake protocol
Sleep—Power consumption is further reduced by disabling bus snooping,
leaving only the PLL in a locked and running state. All internal functional
units are disabled
Deep sleep— When the part is in the sleep state, the syst em can disable the
PLL. The system can then disable the SYSCLK source for greater system
power savings. Power-on reset procedures for restarting and relocking the
PLL must be followed on exiting the deep sleep state
9
PC7457/47 [Preliminary]
5345A–HIREL–11/03
– Thermal management facility provides software-controllable thermal
management. Thermal management is performed through the use of three
supervisor-level registers and a PC7457-specific thermal management
exception
– Instruction cache throttling provides control of instruction fetching to limit
pow er consumption
• Performance monitor can be use d to help debug system designs and improv e
software efficiency
• In-system testability and debugging features through JTAG boundary-scan
capability
• Testability
– LSSD scan design
– IEEE 1149.1 JTAG interface
– Array built-in self test (ABIST) – factory test only
• Reliability and serviceability
– Parity checking on syst em bus and L3 cache bus
– Parity checking on the L2 and L3 cache tag arrays
10 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Signal Description
Figure 2. PC7457 Microprocessor Signal Gr oups
Notes: 1. For the PC7457, there are 19 L3_ADDR signals, (L3_ADDR[0:18].
2. For the PC7447 and PM7457, there ar e 5 PLL_CFG signals, (PLL_CFG[0:4].
18
64
8
1
2
4
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
4
1
1
1
1
1
1
1
1
PC7457
L3_ADDR[17:0](1)
L3-DATA[0:63]
L3_DP[0:7]
L3_VSEL
L3_CLK[0:1]
L3_ECHO_CLK[0:3]
L3_CNTL[0:1]
INT
SMI
MCP
SRESET
HRESET
CKSTP_IN
CKSTP_OUT
TBEN
QREQ
QACK
BVSEL
BMODE[0:1]
PMON_IN
PMON_OUT
SYSCLK
PLL_CFG[0:3](2)
PLL_EXT
EXT_QUAL
CLK_OUT
TCK
TDI
TDO
TMS
TRST
BR
BG
A[0:35]
AP[0:4]
TS
TT[0:4]
TBST
TSIZ[0:2]
GBL
WT
CI
AACK
ARTRY
SHD0/SHD1
HIT
DBG
DTI[0:3]
DRDY
D[0:63]
DP[0:7]
TA
TEA
1
1
36
5
1
5
1
3
1
1
1
1
1
2
1
1
4
1
64
8
1
1
Address
Arbitration
Address
Transfer
Address
Transfer
Attributes
Address
Transfer
Termination
Data
Arbitration
Data
Transfer
Data
Transfer
Termination
L3 Cache
Address/Data
L3 Cache
Clock/Control
Interrupts/Resets
Processor
Status/Control
Clock Control
Test Interface
(JTAG)
AVDD
GND
VDD
OVDD
GVDD
Note: L3 cache interface is not supported
in the PC7441, PC7445, or the PC7447
11
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Detailed
Specification
Scope This specification describes the specif ic req uireme nts for th e micro processor PC7457 in
compliance with Atmel standard screening.
Applicable
Documents 1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: Appendix A: General specifications for microcircuits
Requirements
General The microcircuits are in accordance with the applicable documents and as specified
herein.
Design and Construction
Terminal Connections Depending on the package, the terminal connections are as shown in Table 16, Table 3
and Figure 2.
Absolute Maximum
Ratings
Notes: 1. Functional and tested operating conditions are given in Table 3 on page 12. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresse s beyond those listed may affect device reliability
or cause permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1V during normal operation; this limit may be exceeded for a
maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceede d for a
maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
6. This mode is not supported on current PC7457 devices.
Table 2. Absolute Maximum Ratings(1)
Symbol Characteristic Maximum Value Unit
VDD(2) Core supply voltage TBD V
AVDD(2) PLL supply voltage TBD V
OVDD(3)(4) Processor bus supply voltage BVSEL = 0 TBD V
OVDD(3)(5) BVSEL = HRESET or OVDD TBD V
GVDD(3)(6)
L3 bus supply voltage
L3VSEL = ¬HRESET Not Supported V
GVDD(3)(7) L3VSEL = 0 TBD V
GVDD(3)(8) L3VSEL = HRESET or GVDD TBD V
VIN(9)(10)
Input voltage
Processor bu s TBD V
VIN(9)(10) L3 bus TBD V
VIN JTAG signals TBD V
TSTG Storage temperature range TBD °C
12 PC7457/47 [Preliminary] 5345A–HIREL–11/03
7. L3VSEL must be set to 0, such that the bus is in 1.8V mode.
8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
9. Caution: VIN must not exceed OVDD or GVDD by more than 0.3V at any time including during power-on reset.
10.VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
Recommended
Operating Conditions
Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
2. This voltage is the i nput to the filter discussed in Section “IEEE 1149.1 AC Timing Specifications” and not necessarily the
voltage at the AVDD pin which may be reduced from VDD by the filter.
3. Operation of the L3 interface in this mode is not supported for current PC7457 devices.
Figure 3. Overshoot/Undershoot Voltage
Table 3. Recommended Operating Conditions(1)
Symbol Characteristic
Recommended Value
UnitMin Max
VDD Core supply voltage 1.3V ±50 mV or 1.1V ±50 mV V
AVDD(2) PLL supply voltage 1.3V ±50 mV or 1.1V ±50 mV V
OVDD Processor bus supply voltage BVSEL = 0 1.8V ±5% V
OVDD BVSEL = HRESET or OVDD 2.5V ±5% V
GVDD
L3 bus supply voltage
L3VSEL = 0 1.8V ±5% V
GVDD L3VSEL = HRESET or GVDD 2.5V ±5% V
GVDD(3) L3VSEL = ¬HRESET Not Supported V
VIN
Input voltage
Processor bus GND OVDD V
VIN L3 bus GND GVDD V
VIN JTAG signals GND OVDD V
TjDie-junction temperature -55 125 °C
GND
GND – 0.3 V
GND – 0.7 V
Not to exceed 10% of tSYSCLK
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD/GVDD
VIH
VIL
13
PC7457/47 [Preliminary]
5345A–HIREL–11/03
The PC7457 provides several I/O voltages to support both compatibility with existing
systems and migratio n to futur e systems. Th e PC7457 core volta ge must a lways be pro-
vided at nominal 1.3V (see Table 3 for actual recommended core voltage). Voltage to
the L3 I/Os and processor interface I/Os are provided through separate sets of supply
pins and may be provided at the voltages shown in Table 4. The input voltage threshold
for each bus is select ed by sampling th e state of the volt age select pin s at the negation
of the signal HRESET. The output voltage will swing from GND to the maximum voltage
applied to the OVDD or GVDD power pins.
Notes: 1. Not implemented on PC7447.
2. Caution: The input threshold selecti on must agree with the OVDD/GVDD voltages sup-
plied. See notes in Table 2.
3. If used, pull-down resistors should be less than 250Ω
4. ¬HRESET is the inverse of HRESET. Operation of the processor bus or L3 interface
in this mode is not supported for current PC7457 devices.
Thermal Characteristics
Package Characteristics
Notes: 1. See “Thermal Management Information” on page 15 for more details about thermal management.
2. J unction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-
ture, ambient temperature, airflow, pow er dissipation of other components on the board, and board ther mal resistance.
3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
4. Per JEDEC JESD51-6 with the board horizontal.
5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W.
Table 4. Input Threshold Voltage Setting
BVSEL
Signal Processor Bus Inpu t
Threshold is Relati ve to: L3VSEL
Signal(1) L3 Bus Input Threshold
is Relative to: Notes
01.8V 01.8 (2)(3)
¬HRESET Not available ¬HRESET Not available (2)(4)
HRESET 2.5V HRESET 2.5V (2)
12.5V 12.5V (2)
Table 5. Package Thermal Characteristics(1)
Symbol Characteristic
Value
UnitPC7447 PC7457
RθJA(2)(3) Junction-to-ambient thermal resistance, natural convection 22 20 °C/W
RθJMA(2)(4) Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board 14 14 °C/W
RθJMA(2)(4) Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board 16 15 °C/W
RθJMA(2)(4) Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board 11 11 °C/W
RθJB(5) Junction-to-board thermal resistance 6 6 °C/W
RθJC(6) Junction-to-case thermal resistance < 0.1 < 0.1 °C/W
14 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Internal Package Conduction
Resistance For the exposed-die packaging technology, shown in Table 4 on page 13, the intrinsic
conduction thermal resistance pa ths are as follows:
• The die junction-to-case (actually top-of-die since silicon die is exposed) thermal
resistance
• The die junction-to-ball thermal resistance
Figure 33 on page 57 depicts the primary heat transfer path for a package with an
attached heat sink mounted to a printed-circuit board.
Figure 4. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Note the internal versus external package resistance.
Heat generated on the active side of the chip is conducted through the silicon, then
through the heat sink attach material (or thermal interface ma terial), and finally to the
heat sink where it is re moved by forced-air convect ion.
Because the silicon thermal resistance is quite small, for a first-order analy sis, the tem-
perature drop in the silicon may be neglected. Thus, the thermal interface material and
the heat sink conducti on/convective thermal resistances are the dominant terms.
External Resistance
External Resistance
Internal Resistance
Radiation Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Printed-Circuit Board
Radiation Convection
15
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Thermal Management
Information This section provides thermal management information for the ceramic ball grid array
(CBGA) package for air-cooled applications. Proper thermal control design is primarily
dependent on the system-leve l design – the heat sink, airflow, and thermal interface
material. To reduce the die-junction temperature, heat sinks may be attached to the
package by sev eral methods – spr ing clip to holes in the pr inted-circuit board or p ack-
age, and mounting clip and screw assembly (see Figure 32 on page 54); however, due
to the potentia l large mass of the heat sink, attachment t hrough the printed-circuit board
is suggested. If a spring clip is used, the spring force should not exceed 10 pounds.
Figure 5. Package Exploded Cross-sectional View with Several Heat Sink Options
Printed-Circuit Board
Thermal Interface
Material
Heat Sink
Clip
Heat Sink CBGA Package
16 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to
minimize the thermal contact resistance. For those applications where the heat sink is
attached by spring clip mecha nism, Figure 5 shows the thermal performa nce of three
thin-sheet thermal-interface ma terials (silicone, graphite/oil, floroether oil), a bare joint,
and a joint with ther mal grease as a function of contact pressure.
The use of thermal gre ase significantly reduces t he interface therma l resistance. That is,
the bare joint results in a th er mal resist an ce appr oxima tel y seven times gr ea te r than the
thermal grease joint.
Often, heat sinks are attached to the package by means of a spring clip to holes in the
printed-circuit board (see Figure 32 on page 54). Therefore, the synthetic grease offers
the best thermal performance, considering the low interface pressure and is recom-
mended due to the high power dissipation of the PC7457. Of course, the selection of
any thermal interface material depends on many factors – thermal performance require-
ments, manufacturability, service temperature, dielectric properties, cost, etc.
Figure 6. Thermal Performance of Select Thermal Interf ace Material
Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as
follows:
Tj = TI + Tr + (RθJC + Rθint + Rθsa) × Pd
where:
Tj is the die-junction temperature
TI is the inlet cabinet ambient temperature
Tr is the air temperature rise within the computer cabinet
0
0.5
1
1.5
2
010 20304050607080
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Contact Pressure (psi)
Specific Thermal Resistance (K-in.2/W)
17
PC7457/47 [Preliminary]
5345A–HIREL–11/03
RθJC is the junction-to-case thermal resistance
Rθint is the adhesive or interface material thermal resistance
Rθsa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained less than the
value specified in Table 3 on page 12. The temperature of air cooling the component
greatly depends on the ambient inlet air temperature and the air temperature rise within
the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from
30° to 40°C. The air temperature r ise within a cabinet (Tr) may be in the range of 5° to
10°C.
The thermal resistance of the thermal interface material (Rθint) is typically about
1.5°C/W. For exam ple, assuming a Ta of 30°C, a Tr of 5°C, a CBGA package RθJC =
0.1, and a typical power consumption (Pd) of 18.7W, the following expre ssion for Tj is
obtained:
Die-junction temperature: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7W
For this example, a R θsa value of 2.1°C/W or less is required to maintain the die junction
temperature below the maximum value of Table 3 on page 12.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances
are a common figu re-of-merit used for com paring the thermal performa nce of various
microelectronic packaging technologies, one should exercise caution when only using
this metric in determining thermal management because no single parameter can ade-
quately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power
consumption, a number of factors affect the final operating die-junction temperature –
airflow, board population (local heat flux of adjacent components), heat sink efficiency,
heat sink attach, heat sink placement, next-level interconnect technology, system air
temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for
today's microelectronic equipme nt, the combined effects of the heat transfe r mecha-
nisms (radiation, convection, and conduction) may vary widely. For these reasons, we
recommend using conjugate heat transfer models for the board, as well as system-level
designs.
For system thermal modeling, the PC7447 and PC7457 thermal model is shown in Fig-
ure 4 on page 14. Four volumes will be used to represent this device. Two of the
volumes, solder ball, and air and substrate, are modeled using the package outline size
of the package. The other two, die, and bump and underfill, have the same size as the
die. The silicon die should be modeled 9.64 × 1 1 × 0.74 mm with th e heat source ap plied
as a uniform source at the bottom of the volume. The bump and underfill layer is mod-
eled as 9.64 × 11 × 0.69 mm (or as a collapsed volume) with orthotropic material
properties: 0.6W/(m × K) in the xy-plane and 2W/(m × K) in the direction of the z-axis.
The substrate volu me is 25 × 25 × 1.2 mm (PC7447) or 29 × 29 × 1.2 mm (PC7457), and
this volume has 18W/(m × K) isotropic co nductivit y. The so lder ball and a ir layer is mo d-
eled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can
also be modeled as a collapsed volume using orthotropic material properties:
0.034W/(m × K) in the xy-plane direction and 3.8W/(m × K) in the direction of the z-axis.
18 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Figure 7. Recommended Thermal Model of PC7447 and PC7457
Power Consumption .
Notes: 1. These values apply for all valid processor bus and L3 bus ratios. The values don’t
include I/O supply power (OVDD and GVDD) or PLL supply power (AVDD). OVDD and
GVDD power is system dependent, but is typically <5% of VDD power. Worst case
power consumption for AVDD < 3 mW.
Bump and Underfill
Die
Substrate
Solder and Air
Die
Substrate
Side View of Model (Not to Scale)
Side View of Model (Not to Scale)
x
y
z
Conductivity Value Unit
Bump and Underfill
kx0.6 W/(m x K)
ky0.6
kz2
Substrate
k18
Solder Ball and Air
kx0.034
ky0.034
kz3.8
Table 6. Power Consumption for PC7457
Core Power Supply
Processor (CPU) Frequency
Unit
867 MHz 1 GHz 1.3 GHz (TBC)
1.1 1.3 1.1 1.3 1.3
Full-Power Mode
Typical(1)(2) TBD 14.8 8.3 15.8 18.7 W
Maximum(1)(3) TBD 21 11.5 22 26 W
Doze Mode
Typical(4) TBD –TBD – – W
Nap Mode
Typical(1)(2) TBD 5.2 TBD 5.2 5.2 W
Sleep Mode
Typical(1)(2) TBD 5.1 TBD 5.1 5.1 W
Deep Sleep Mode (PLL Disabled)
Typical(1)(2) TBD 5 2 5 5 W
19
PC7457/47 [Preliminary]
5345A–HIREL–11/03
2. Typical power is an average value measured at the nominal recommended VDD (see
Table 3 on page 12) and 65°C while running the Dhrystone 2.1 benchmark and
achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the average measured at nominal VDD and maximum operating
junction temperature (see Table 3 o n page 12) while running an entirely cache-resi-
dent, contrived sequence of instructions which keep all the execution units maximally
busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-
power and either nap or sleep mode. As a result, pow er consumption for this mode is
not tested.
Electrical
Characteristics
Static Characteristics
Table 7 provides the DC electrical characteristics for the PC7457.
Notes: 1. Nominal voltages; see Table 3 on page 12 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. The leakage is measured for nominal OVDD/GVDD and VDD, or both O VDD/GVDD and VDD must vary in the same direction (for
example, both OVDD and VDD vary by either +5% or -5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. This mode is not supported on current PC7457 devices.
Table 7. DC Electrical Specifications (see Table 3 on page 12 for Recommended Operating Conditions)
Symbol Characteristic Nominal Bus
Voltage(1) Min Max Unit
VIH(2)
Input high voltage (all inputs except SYSCLK)(2)
1.5 Not supported V
VIH 1.8 OVDD/GVDD × 0.65 OVDD/GVDD + 0.3 V
VIH 2.5 1.7 OVDD/GVDD + 0.3 V
VIL(2)(6)
Input low voltage (all inputs except SYSCLK)(2)
1.5 Not supported V
VIL 1.8 -0.35 OVDD/GVDD × 0.35 V
VIL 2.5 -0.3 0.7 V
CVIH SYSCLK input high voltage –1.4 OVDD + 0. 3 V
CVIL SYSCLK input low voltage –-0.3 0.4 V
IIN(2)(3) Input leakage current, VIN = GVDD/OVDD – – 30 µA
ITSI(2)(3)(4) High-impedance (off-state)
Leakage current, VIN = GVDD/OVDD – – 30 µA
VOH Output high voltage, IOH = -5 mA 1.8 OVDD/GVDD – 0.45 – V
VOH 2.5 1.7 – V
VOL Output low voltage, IOL = 5 mA 1.8 –0.45 V
VOL 2.5 –0.7 V
CIN Capacitance,
VIN = 0V, f = 1 MHz L3 interface(5) ––9.5 pF
All other inputs(5) – 8 pF
20 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Dynamic Characteristics This section provides the AC electrical characteristics for the PC7457. After fabrication,
functional parts are so rted by maximum processor core frequency as shown in section
“Clock AC Specifications” and tested for conformance to the AC specifications for that
frequency. The pr ocessor core frequ ency is determined by the bus ( SYSCLK) frequency
and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor
core frequency; See “Ordering Information” on page 59.
Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 8 and repre-
sents the tested operating frequencies of the devices. The maximum system bus
frequency, fSYSCLK, given in Table 8 is considered a practical maximum in a typical sin-
gle-processor system. The actual maximum SYSCLK frequency for any application of
the PC7457 will be a function of the AC timings of the PC7457, the AC timings for the
system controller, bus loading, printed-circuit board topology, trace lengths, and so
forth, and may be less than the value given in Table 8.
Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, CPU (core) frequency and PLL (VCO) frequency don’t exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in “PLL Configuration” on page 50 for valid PLL_CFG[0:4]
settings
2. Assumes lightly-loaded, single-processor system.
3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow
cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Table 8. Clock AC Timing Specifications (See Table 3 on page 12 for Recommended Operating Conditions)
Symbol Characteristic
Maximum Processor Core Frequency
Unit
867 MHz 1 GHz 1.3 GHz
Min Max Min Max Min Max
fCORE(1) Processor frequency 600 867 600 1000 600 1300 MHz
fVCO(1) VCO frequency 1200 1733 1200 2000 1200 2600 MHz
fSYSCLK(1)(2) SYSCLK frequency 33 167 33 167 33 167 MHz
tSYSCLK(2) SYSCLK cycle time 630 630 630 ns
tKR & tKF(3) SYSCLK rise and fall time – 1 – 1 – 1 ns
tKHKL/tSYSCLK(4) SYSCLK duty cycle measured at OVDD/2 40 60 40 60 40 60 %
SYSCLK jitter(5)(6) –±150 –±150 –±150 ps
Internal PLL relock time(7) –100 –100 –100 µs
21
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Figure 8 provides the SYSCLK input timing diagram.
Figure 8. SYSCLK Input Timing Diagram
VM = Midpoint Voltage (OVDD/2)
Processor Bus AC
Specifications Table 9 provides the processor bus AC timing specifications for the PC7457 as defined
in Figure 17 on page 33 and Figure 9 on page 22. Timing specifications for the L3 bus
are provided in section “L3 Clock AC Specifica tions” on page 23.
SYSCLK VMVMVM
tKHKL
tSYSCLK
CVIL
CVIH
tKR tKF
Table 9. Processor Bus AC Timing Specifications(1) (at Recommended Operating Conditions, see Figure 3 on page 12.)
Symbol(2) Parameter
All Speed Grades
UnitMin Max
tMVRH(3)(4)(5)(6) Mode select input setup to HRESET 8 tSYSCLK
tMXRH(3)(6) HRESET to mode select input hold 0ns
tAVKH
tDVKH
tIVKH
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2],
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]
1.8
1.8
1.8
–
–
–ns
tAXKH
tDXKH
tIXKH
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2],
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]
0
0
0
–
–
–ns
tKHAV
tKHDV
tKHOV
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2],
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]
–
–
–
2
2
2ns
tKHAX
tKHDX
tKHOX
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2],
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]
0.5
0.5
0.5
–
–
–ns
tKHOE SYSCLK to Output Enable 0.5 –ns
tKHOZ SYSCLK to output high impedance (all except TS, ARTRY, SHD0, SHD1) – 3.5 ns
tKHTSPZ(5)(7)(8) SYSCLK to TS high impedance after precharge – 1 tSYSCLK
tKHARP(5)(8)(9)(10) Maximum delay to AR TRY/SHD0/SHD1 precharge – 1 tSYSCLK
tKHARPZ(5)(8)(9)(10) SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge – 2 tSYSCLK
22 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications a re measured from the midpoi nt of the r ising edg e of SYSCLK to the mi dpoint of the sig-
nal in question. All output timings assume a purely resistive 50Ω load (see Figure 17 on page 33). Input and output ti mings
are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) f or outputs. F or e xample , tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to
the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK (K)
going high (H) until outputs (O) are v alid (V) or output valid time . Input hold time can be read as the time that the input signal
(I) went invalid (X) with respe ct to the r ising clock edge (KH) (note the po sition o f the reference and its state for inputs) and
output hold time can be read as the time from the rising edge (KH) until th e output went invalid (OX).
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 9 on page 22).
4. This specification is for configuration mode select only.
5. tSYSCLK is the period of the external clock ( SYSCLK) in ns. The n umbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
6. Mode select signals are BVSEL, L3VSEL, PLL_CFG[0:4], BMODE[0:1].
7. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high
before returning to high imped ance as shown in Figure 10. The nominal prech arge width for TS is 0.5 × tSYSCLK, that is, less
than the minimum tSYSCLK period, to ensure that another master asserting TS on the f ollo wing cloc k will not contend with the
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The
high-impedance behavior is guaranteed by design.
8. Guaranteed by design and not tested .
9. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK will then go to high impe dance for one clock before precharging it high dur ing the second
cycle after the asser tion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high imped-
ance as shown in Figure 10 before the first oppor tunity for another master to assert ARTRY. Output valid and output hold
timing is tested for the signal asserted. The high-impedance behavior is guaranteed by design.
10.According to the MPX bus protocol, SHD0 and SHD1 can be driven by m ultiple bus masters beginning the cycle of TS. Tim-
ing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is
1.0 tSYSCLK. The edges of the precharge vary depen ding on the programmed ratio of core to bus (PLL config urations).
Figure 9. Mode Input Timing Diagram
tMVRH tMXRH
HRESET
Mode Signals
VM
23
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Figure 10 provides the input/output timing diagra m for the PC7457.
Figure 10. Input/Out pu t Tim in g Dia gr am
Note: VM = Midpoint Voltage (OVDD/2)
L3 Clock AC Specifications The L3_CLK frequ ency is programmed by the L3 configuration register (L3CR[6:8])
core-to-L3 divisor ratio. See Table 18 on page 50 for example core and L3 frequencies
at various divisors. Table 10 provides the potential range of L3_CLK output AC timing
specifications as defined in Figure 11.
The maximum L3_ CLK frequency is the core frequency divided by two. Given the high
core frequencies available in the PC7457, however, most SRAM designs will be not be
able to operate in this mode using current technology and, as a result, will select a
greater core-to-L3 divisor to provide a longer L3_CLK period for read and write access
to the L3 SRAM s. Therefore, the max imum L3_CLK frequen cy shown in Table 10 is
considered to be the practical maximum in a typical system. The maximum L3_CLK fre-
quency for any application of the PC7457 will be a function of the AC timings of the
PC7457, the AC timings for the SRAM, bus loading, and printed-circuit board trace
length, and may be greater or less than the value given in Tabl e 10.
SYSCLK
All Inputs
VM
All Outputs
VM
(Except TS,
All Outputs
TS
VM
tKHOE
ARTRY, SHD0, SHD1)
(Except TS,
ARTRY, SHD0, SHD1)
ARTRY,
SHD0,
SHD1
tAVKH
tKHAV
tIVKH
tAXKH
tIXKH
tKHDV
tKHOV
tKHAX
tKHDX
tKHOX
tKHOZ
tKHTSPZ
tKHTSX
tKHTSV
tKHTSV
tKHARV tKHARP
tKHARX
tKHARPZ
24 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Motorola is similarly limited by system constraints and cannot perform tests of the L3
interface on a socketed part on a functional tester at the maximum frequencies of Table
10. Therefore, functional operation and AC timing information are tested at core-to-L3
divisors which result in L3 frequencies at 200 MHz or less.
Notes: 1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependen t. See “L3 Clock AC Specifica-
tions” on page 23 for an explanation that this maximum frequency is not functionally tested at speed by Motorola. The
minimum L3 clock frequency and period are fSYSCLK and tSYSCLK, respectively.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals
which are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or
Late Wr ite SR AM. Th is paramete r is cr i tical to the w r ite data sign als which are separately latched onto each SRAM pa rt by
these pairs of signals.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address/data/control
signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the L3 tim-
ing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage noise or
thermal effects. This must be accounted for, along with clock skew, in any L3 timing analysis.
Figure 11. L3_CLK_OUT Output Timing Diagram
Table 10. L3_CLK Output AC Timing Specifications at Recommended Operating Conditions (see Table 3 on page 12)
Symbol Parameter
All Speed Grades
UnitMin Max
fL3_CLK(1) L3 clock frequency –200 MHz
tL3_CLK(1) L3 clock cycle time 5 – ns
tCHCL/tL3_CLK(2) L3 clock duty cycle 50 %
tL3CSKW1(3) L3 clock output-to-output skew (L1_CLK0 to L1_CLK1) –100 ps
tL3CSKW2(4) L3 clock output-to-output skew (L1_CLK[0:1] to L1_ECHO_CLK[2:3]) –TBD ps
L3 clock jitter(5) –TBD ps
L3_CLK0 VM
tL3CR tL3CF
VM
VMVM
L3_CLK1
VM
VM
tL3_CLK
tCHCL
VM
L3_ECHO_CLK1
L3_ECHO_CLK3 VMVM VM VM
VMVM VM VM
For PB2 or Late Write:
tL3CSKW1
tL3CSKW2
tL3CSKW2
25
PC7457/47 [Preliminary]
5345A–HIREL–11/03
L3 Bus AC Specifications The PC7457 L3 interface supports three different types of SRAM: source-synchronous,
double data rate (DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2)
SRAMs. Each requires a different protocol on the L3 interface and a different routing of
the L3 clock signals. Th e ty pe of SRAM is pr ogram med in L 3CR[22: 23] and the PC7 457
then follows the appr opria te proto col fo r th at type . Th e desig ner must connect and rou te
the L3 signals appropriately for each type of SRAM. Following are some observations
about the L3 interface.
• The routing for the point-to-point signals (L3_CLK[0:1], L3 DATA[0:63], L3DP[0:7],
and L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched
• For 1M byte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)
• For 2M bytes of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)
• No pull-up resistors are required for the L3 interface
• F or high speed ope r ations, L3 interface ad dress and con trol signals should be a "T"
with minimal stubs to the two loads; data and clock signals should be point-to-point
to their single load. Figure 12 shows the AC test load for the L3 interface.
Figure 12. AC Test Load for the L3 Interface
In general, if routing is short, delay-matched, and designed for incident wave reception
and minimal reflection, there is a high probability that the AC timing of the PC7457 L3
interface will meet the maximum frequency operation of appropriately chosen SRAMs.
This is despite the pessimistic, guard-banded AC specifications (see Table 12 on page
27, Table 13 on page 28, and Table 14 on page 31), the limitations of functional testers
described in Section “L3 Clock AC Specifications” on page 23 and the uncertainty of
clocks and signals which inevitably make worst-case critical path timing analysis
pessimistic.
More specifically, certain signals within groups should be delay-matched with others in
the same group while interg roup routing is less crit ical. Only the address and contr ol sig-
nals are common to both SRAMs and additional timing margin is available for these
signals. The double-clocked data signals are grouped with individual clocks as shown in
Figure 13 on page 29 or Figure 15 on page 32, depending on the type of SRAM. For
example, for the MSUG2 DDR SRAM (see Figure 13); L3DATA[0:31], L3DP[0:3], and
L3_CLK[0] form a closely coupled group of outputs from the PC7457; while
L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0] form a closely coupled group of
inputs.
The PC7450 RISC Micropr ocessor Family User ’s Manual refers to logical settings called
"sample points" u sed in the synchronizat ion of read s from the re ceive FIFO. Th e compu-
tation of the correct value fo r this setting is system-dependent and is describ ed in the
PC7450 RISC Microprocessor Family User’s Manual.
Three specifications are used in this calculation and are given in Table 11 on pa ge 26. It
is essential that all three specifications are included in the calculations to determine the
sample points as incorrect settings can result in errors and unpredictable behavior. For
more informat ion, see the PC7450 RISC Microprocessor Family User’s Manual.
Z0 = 50Ω
RL = 50Ω
OVDD/
2
Output
26 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Notes: 1. This specification describe s a logical offset between the inter nal clock edge used to
launch the L3 address and control signals (thi s clock edge is phase-aligned wi th the
processor clock edge) and the inte rnal clock edge used to launch th e L3 _CLK[n] sig-
nals. With proper board routing, this offset ensures that the L3_CLK[n] edge will
arrive at the SRAM within a valid address window and provide adequate setup and
hold time. This offset is reflected in the L3 bus interface AC timing specifications, but
must also be separately accounted for in the calculation of sample points and, thus, is
specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK
signal to the corresponding rising or falling edge at the L3CLK[n] pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to
data valid and ready to be sampled from the FIFO.
Effects of L3OHCR Settings on
L3 Bus AC Specifications The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control
Register (L3OCHR).
Each field controls the timing for a group of signals. The AC timing specifications pre-
sented herein represent the AC timing when the register conta ins the default value of
0x0000_0000. Incrementing a field delays the associated signals, increasing the output
valid time and hold time of the affected signals. In the special case of delaying an
L3_CLK signal, the net effect is to decrease the output valid and output hold times of all
signals being latched relative to that clock signa l. The amount of delay add ed is summa-
rized in Table 12 on page 27.
Note that these settings affect output timing parameters only and don’t impact input tim-
ing parameters of the L3 bus in any way.
Table 11. Sample Points Calculation Parameters
Symbol Parameter Max Unit
tAC Delay from processor clock to internal_L3_CLK(1) 3/4 tL3_CLK
tCO Delay from internal_L3_CLK to L3_C LK[n] output pins(2) 3ns
tECI Delay from L3_ECHO_CLK[n] to receive latch(3) 3ns
27
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Notes: 1. Refer to the PC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
2. See Table 13 on page 28 and Table 14 on page 31 for more information.
3. Guaranteed by design; not teste d or characterized.
4. Default value.
5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of
all signals latched relative to that clock signal by the SRAM; see Figure 13 on page 29 and Figure 15 on page 32.
L3 Bus AC Specifications for
DDR MSUG2 SRAMs When using DDR MSUG2 SRAMs at th e L3 inter f ace, the par ts should be co nn ected as
shown in Figure 13.
Outputs from the PC7457 are actually lau nched on the edge s of an interna l clock phase-
aligned to SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and
L3_CLK1 are this internal clock output with 90° phase delay, so outputs are shown syn-
chronous to L3_CLK0 and L3_CLK1. Output valid times are typically negative when
referenced to L3_CLKn because the data is launched one-quarter period before
L3_CLKn to provide ad equate setup time at the SRAM afte r the delay-matched address,
control, data, and L3_CLKn signals have propagated across the printed-wiring board.
Inputs to the PC7457 are source-synchronous with the CQ clock generated by the DDR
MSUG2 SRAMs.
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
Field name(1) Affected Signals Value
Output Valid Time Output Hold Time
Unit Notes
Parameter
Symbol(2) Change(3) Parameter
Symbol(2) Change(3)
L3AOH L3_ADDR[18:0],
L3_CNTL[0:1]
0b00
tL3CHOV
0
tL3CHOX
0
ps
(4)
0b01 +50 +50
0b10 +100 +100
0b11 +150 +150
L3CLKn_OH
All signals latched
by SRAM
connected to
L3_CLKn
0b000
tL3CHOV
tL3CHDV
tL3CLDV
0
tL3CHOX
tL3CHDX
tL3CLDX
0(4)
0b001 -50 -50 (5)
0b010 -100 -100 (5)
0b011 -150 -150 (5)
0b100 -200 -200 (5)
0b101 -250 -250 (5)
0b110 -300 -300 (5)
0b111 -350 -350 (5)
L3DOHn L3_DATA[n:n + 7],
L3_DP[n/8]
0b000
tL3CHDV
tL3CLDV
0
tL3CHDX
tL3CLDX
0(4)
0b001 +50 +50
0b010 +100 +100
0b011 +150 +150
0b100 +200 +200
0b101 +250 +250
0b111 +350 +350
0b111 +350 +350
28 PC7457/47 [Preliminary] 5345A–HIREL–11/03
These CQ clocks are received on the L3_ECHO_CLKn inputs of the PC7457. An inter-
nal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within
the valid data wind ow at the internal receiving latch es. This delayed clock is used to
capture the data in to th ese latche s which comp rise the receive FIFO. This clock is asyn-
chronous to all other pr ocessor clo cks. This latch ed dat a is su bseq uen tly rea d o ut of the
FIFO synchronously to the processor clock. The time between writing and reading the
data is set by using the sample point settings defined in the L3CR register.
Table 13 provides the L3 bus interface AC timing specifications for the configuration as
shown in Figure 13, assuming the timing relationships shown in Figure 14 and the load-
ing shown in Figure 12 on page 25.
Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoi nt of the si gnal in questio n to the midpoi nt voltage of the ris-
ing or falling edge of the input L3_ECHO_CLKn (see Figure 14 on page 30). Input timings are measured at the pins.
3. For DDR, the input data will typ ically follow the edge of L3_ECHO_CLKn as shown in Figure 14. For consistency with other
input setup time specifications, this will be treated as negative input setup time.
4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the PC7457 can latch an input signal that is
valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising)
edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the f alling) edge of
L3_CLK to the midpoint of the signa l in questi on. The output timings are mea sured at the pi ns. All outp ut ti mings a ssu me a
purely resistive 50Ω load (see Figure 12 on page 25).
6. For DDR, the output data wi ll typically lead the edge of L3_CLKn as shown in Figure 14 on page 30. For consistency with
other output valid time specifications, this will be treated as negative output valid time.
7. tL3_CLK/4 is one-four th the per io d of L3_CLKn. This p arameter ind icates that the specified output signal is actually launch ed
by an internal clock delayed in phase by 90°. Therefore, there is a frequency comp onent to the output valid and output hold
times such that the specified output signal will be valid f or appro ximately one L3_CLK period starting three-f ourths of a clock
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
8. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 26 for more
information.
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions
(see Table 3 on page 12)
Symbol Parameter
All Speed Grades
UnitMin Max
tL3CR, tL3CF L3_CLK rise and fall time(1) –0.75 ns
tL3DVEH, tL3DVEL Setup times: Data and parity(2)(3)(4) -0.35 –ns
tL3DXEH, tL3DXEL Input hold times: Data and parity(2)(4) 2.1 –ns
tL3CHDV, tL3CLDV Valid times: Data and parity(5)(6)(7)(8) –(-tL3CLK/4) + 0.60 ns
tL3CHOV Valid times: All other outputs(5)(7)(8) –(tL3CLK/4) + 0.65 ns
tL3CHDX, tL3CLDX Output hold times: Data and parity(5)(6)(7)(8) (tL3CLK/4) - 0.60 –ns
tL3CHOX Output hold times: All other outputs(5)(7)(8) (tL3CLK/4) - 0.50 –ns
tL3CLDZ L3_CLK to high impedance : Data and parity –TBD ns
tL3CHOZ L3_CLK to high impedance: Data and parity –TBD ns
29
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Figure 13 show s the ty pical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs.
Figure 13. Typical Source Synchronous 4M bytes L3 Cache DDR Interface
Note: 1. Or as recommended by SRAM manufacturer for single-ended clocking.
{L3DATA[0:15], L3DP[0:1]}
{L3DATA[16:31], L3DP[2:3]}
{L3DATA[32:47], L3DP[4:5]}
L3ADDR[18:0]
L3_CNTL[0]
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3ECHO_CLK[2]
L3_ECHO_CLK[3]
{L3DATA[48:63], L3DP[6:7]}
CQ
SA[18:0]
CK
B1
B2
SRAM 0
SRAM 1
CQ
D[0:17]
D[18:35]
CQ
SA[18:0]
CK
B1
B2
CQ
D[0:17]
D[18:35]
L3_CNTL[1]
NC
NC
GND
GND
GND
NC
NC
GND
GND
GND
PC7457
Denotes
Receive (SRAM
to PC7457)
Aligned Signals
Denotes
Transmit
(PC7457 to SRAM)
Aligned Signals
(1)
CQ
CK
B3
G
CQ
LBO
CQ
CK
B3
G
CQ
LBO
GVDD/2
(1)
GVDD/2
30 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Figure 14 shows the L3 bus timing diagrams for the PC7457 interfaced to MSUG2 SRAMs.
Figure 14. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
Note: tL3CHDV and tL3CLDV as drawn here will be nega tive numbers, that is, output valid time will be time before the clock edge.
Notes: 1. tL3DVEH and tL3DVEL as drawn here will be negative numbers, that is, input setup time will be time after the clock edge.
2. VM = Midpoint Voltage (GVDD/2)
L3_CLK[0,1]
ADDR, L3CNTL
VM
tL3CHOV tL3CHOX
VM
tL3CHOZ
VM VM VM
tL3CHDV
tL3CHDX
Outputs
tL3CLDV
tL3CLDX
tL3CLDZ
L3DATA WRITE
L3_ECHO_CLK[0,1,2,3]
L3 Data and Data
Parity Inputs
VM VM VM VMVM
Inputs
tL3DVEH
tL3DXEL
tL3DVEL
tL3DXEH
31
PC7457/47 [Preliminary]
5345A–HIREL–11/03
L3 Bus AC Specifications for
PB2 and Late Write SRAMs When using PB2 or Late Write SRAMs at the L3 interface, the parts should be con-
nected as shown in Figure 15 on page 32. These SRAMs are synchronous to the
PC7457; one L3_CLKn signal is ou tput to each SRAM to latch address, control, and
write data. Read data is launched by the SRAM synch ronous to the delayed L3_CL Kn
signal it received. T he PC7457 needs a copy of that delayed clock which launched the
SRAM read data to know when the returning data will be valid. Therefore,
L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and then
returned to the PC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively.
Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock
received at the SRAMs. The PC7457 will latch the incoming data on the rising edg e of
L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14 provides the L3 bus interface AC timing specificatio ns for the configuration
shown in Figure 15, assuming the timing relationships of Figure 16 and the loading of
Figure 12 on page 25.
Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are mea s ured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLKn (see Figure 14 on page 30). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal
in question. The output timings ar e meas ured at the p ins. All output timings assume a p urely resistive 50Ω load (see Fi gure
14).
5. tL3_CLK/4 is one-four th the per io d of L3_CLKn. This p arameter ind icates that the specified output signal is actually launch ed
by an internal clock delayed in phase by 90°. Therefore, there is a frequency comp onent to the output valid and output hold
times such that the specified output signal will be valid f or appro ximately one L3_CLK period starting three-f ourths of a clock
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
6. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 26 for more
information.
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating Condi-
tions (see Table 3 on page 12)
Symbol Parameter
All Speed Grades
UnitMin Max
tL3CR, tL3CF L3_CLK rise and fall time(1)(2) –0.75 ns
tL3DVEH Setup times: Data and parity(2)(3) TBD –ns
tL3DXEH Input hold times: Data and parity(2)(3) –TBD ns
tL3CHDV Valid times: Data and parity(2)(4)(5)(6) –TBD ns
tL3CHOV Valid times: All other outputs (5)(6) –TBD ns
tL3CHDX Output hold times: Data and parity(2)(4)(5)(6) TBD –ns
tL3CHOX Output hold time s: Al l ot he r ou tp u ts (2)(5)(6) TBD –ns
tL3CHDZ L3_CLK to high impedance: Data and par ity(2) –TBD ns
tL3CHOZ L3_CLK to high impedance: All other outputs(2) –TBD ns
32 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Figure 15 shows the typical connection diagram for the PC7457 interfaced to PB2 SRAMs or Late Write SRAMs.
Figure 15. Typical Synchronous 1M Byte L3 Cache Late Write or PB2 Interface
Note: 1. Or as recommended by SRAM manufacturer for single-ended clocking.
L3_ADDR[16:0]
L3_CNTL[0] SA[16:0]
K
K
SS
SW
ZZ
G
SRAM 0
DQ[0:17]
DQ[18:36 ]
L3_CNTL[1]
GVDD/2/2 (1)
GVDD/2 (1)
GND
GND
SRAM 1
GND
GND
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
PC7457
L3_ECHO_CLK[3]
SA[16:0]
K
K
SS
SW
ZZ
G
DQ[0:17]
DQ[18:36]
Denotes
Receive (SRAM
to PC7457)
Aligned Signals
Denotes
Transmit
(PC7457 to SRAM)
Aligned Signals
{L3_DATA[0:15], L3_DP[0:1]}
{L3_DATA[16:31], L3_DP[2:3]}
{L3_DATA[32:47], L3_DP[4:5]}
{L3_DATA[48:63], L3_DP[6:7]}
33
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Figure 16 shows the L3 bus timing diagrams for the PC7457 interfaced to PB2 or Late Write SRAMs.
Figure 16. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
Note: VM = Midpoint Voltage (GVDD/2)
Figure 17. AC Test Load
L3_ECHO_CLK[0,2] VM
tL3DVEH
tL3DXEH
L3_CLK[0,1]
ADDR, L3_CNTL
VM
tL3CHOV tL3CHOX
VM
tL3CHDZ
Outputs
Inputs
L3_ECHO_CLK[1,3]
tL3CHDV tL3CHDX
tL3CHOZ
L3DATA WRITE
Parity Inputs
L3 Data and Data
Z0 = 50Ω
RL = 50Ω
OVDD/
2
Output
34 PC7457/47 [Preliminary] 5345A–HIREL–11/03
IEEE 1149.1 AC Timing
Specifications Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure
19 through Figure 22 on page 36.
Notes: 1. All outputs are measured from the mi dpoint voltage of the falling/r ising edge of TCLK to the midpoint of the si gnal in ques-
tion. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (see Figure 18).
Time-of-flight dela ys must be added for trace lengths, vias and connectors in the system.
2. TRST is an asynchro nous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization
Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC7457.
Figure 18. Alternate AC Test Load for the JTAG Interface
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK)(1)at Recommended Operating Conditions
(see Table 3 on page 12)
Symbol Parameter Min Max Unit
fTCLK TCK frequency of operation 033.3 MHz
tTCLK TCK cycle time 30 –ns
tJHJL TCK clock pulse width measured at 1.4V 15 –ns
tJR and tJF TCK rise and fall times 0 2 ns
tTRST(2) TRST assert time 25 –ns
tDVJH(3)
tIVJH
Input Setup Times:
Boundary-scan data
TMS, TDI 4
0–
–ns
tDXJH(3)
tIXJH
Input Hold Times:
Boundary-scan data
TMS, TDI 20
25 –
–ns
tJLDV(4)
tJLOV
Valid Times:
Boundary-scan data
TDO 4
420
25 ns
tJLDX(4)
tJLOX
Output hold times:
Boundary-scan data
TDO
TBD
TBD TBD
TBD
tJLDZ(4)(5)
tJLOZ
TCK to output high impedance:
Boundary-scan data
TDO 3
319
9ns
Output Z0 = 50Ω
RL = 50Ω
OVDD/2
35
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Figure 19. JTAG Clock Input Timing Diagram
Note: VM = Midpoint Voltage (OVDD/2)
Figure 20. TRST Timing Diagram
Note: VM = Midpoint Voltage (OVDD/2)
Figure 21. Boundary-scan Timing Diagram
Note: VM = Midpoint Voltage (OVDD/2)
VMVMVM
tTCLK
tJR tJF
tJHJL
TCLK
TRST
t
TRST
VM
VM
VMTCK
Boundary
Data Inputs
Boundary
Data Outputs
Boundary
Data Outputs
tDXJH
tDVJH
tJLDV
tJLDZ
Output Data Valid
tJLDX
VM
Input
Data Valid
Output Data Valid
36 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Figure 22. Test Access Port Timing Diagram
Note: VM = Midpoint Voltage (OVDD/2)
Preparation for
Delivery
Handling MOS devices must be handled with certain precautions to avoid damage due to accu-
mulation of static charge. Input protection devices have been designed in the chip to
minimize the effect of static buildup. However, the following handling practices are
recommended:
• Devices should be handled on benches with conductive and grounded surfaces.
• Ground test equipment, tools and operator.
• Do not handle devices by the leads.
• Store devices in conductive foam or carriers.
• Avoid use of plastic, rubber or silk in MOS areas.
• Maintain relative humidity above 50% if practical.
tJLOX
Input Data
Valid
tIVJH tIXJH
tJLOV
tJLOZ
Output Data Valid
Output Data Valid
VM
TCK
TDI, TMS
TDO
TDO
VM
37
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Package Mechanical
Data The following sections provide the package parameters and mechanical dimensions for
the CBGA package.
Package Parameters for
the PC7447, 360 CBGA The package parameters are as p rovided in the following list. The package type is
25 × 25 mm, 360-lead ceramic ball grid array (CBGA).
Package outline 25 mm × 25 mm
Interconnects 360 (19 × 19 ball array - 1)
Pitch 1.27 mm (50 mil)
Minimum module height 2.72 mm
Maximum module height 3.24 mm
Ball diameter 0.89 mm (35 mil)
38 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Pin Assignment Figure 23 shows the pinout of the PC7447, 360 CBGA package as viewed from the top
surface.
Figure 24 shows the side profile of the CBGA package to indicate the direction of the top
surface view .
Figure 23. Pinout of the PC7 447 , 360 CBG A Package as Viewe d fro m the Top Sur face
Figure 24. Side View of the CBGA Package
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
321456 16 17 18 19
U
V
W
151413121110987
Substrate Assembly
Encapsulant
View Die
39
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Pinout Listings Table 16 provides the pinout listing for the PC7447, 360 CBGA package. Table 15 pro-
vides the pinout listing for the PC7457, 483 CBGA package.
Note: This pinout is not compatible with the PC750, PC7400, or PC7410 360 BGA package.
Table 16. Pinout Listing for the PC7447, 360 CBGA Package
Signal Name Pin Number Active I/O I/F Select(1)
A[0:35](2) E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4,
V1, J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1,
B12, C4, G10, B11 High I/O BVSEL
AACK R1 Low Input BVSEL
AP[0:4] C1, E3, H6, F5, G7 High I/O BVSEL
ARTRY(3) N2 Low I/O BVSEL
AVDD A8 –Input BVSEL
BG M1 Low Input BVSEL
BMODE0(4) G9 Low Input BVSEL
BMODE1(5) F8 Low Input BVSEL
BR D2 Low Output BVSEL
BVSEL(1)(6) B7 High Input BVSEL
CI(3) J1 Low Output BVSEL
CKSTP_IN A3 Low Input BVSEL
CKSTP_OUT B1 Low Output BVSEL
CLK_OUT H2 High Output BVSEL
D[0:63]
R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14,
W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9,
P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17,
R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17,
W3, V17, U4, U8, U7, R7, P6, R8, W8, T8
High I/O BVSEL
DBG M2 Low Input BVSEL
DP[0:7] T3, W4, T4, W9, M6, V3, N8, W6 High I/O BVSEL
DRDY(7) R3 Low Output BVSEL
DTI[0:3](8) G1, K1, P1, N1 High Input BVSEL
EXT_QUAL(9) A11 High Input BVSEL
GBL E2 Low I/O BVSEL
GND
B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10,
J12, K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13,
N7, P3, P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11,
V15
– – N/A
HIT(7) B2 Low Output BVSEL
HRESET D8 Low Input BVSEL
INT D4 Low Input BVSEL
L1_TSTCLK(9) G8 High Input BVSEL
L2_TSTCLK(10) B3 High Input BVSEL
40 PC7457/47 [Preliminary] 5345A–HIREL–11/03
No Connect(11)
A6, A13, A14, A15, A16, A17, A18, A19, B13, B14, B15, B16, B17,
B18, B19, C13, C14, C15, C16, C17, C18, C19, D14, D15, D16, D17,
D18, D19, E12, E13, E14, E15, E16, E19, F12, F13, F14, F15, F16,
F17, F18, F19, G11, G12, G13, G14, G15, G16, G19, H14, H15, H16,
H17, H18, H19, J14, J15, J16, J17, J18, J19, K15, K16, K17, K18,
K19, L14, L15, L16, L17, L18, L19, M14, M15, M16, M17, M18, M19,
N12, N13, N14, N15, N16, N17, N18, N19, P15, P16, P18, P19
– – –
LSSD_MODE(6)(12) E8 Low Input BVSEL
MCP C9 Low Input BVSEL
OVDD B4, C2, C12, D5, E18, F2, G18, H3, J5, K2, L5, M3, N6, P2, P8, P11,
R4, R13, R16, T6, T9, U2, U12, U16, V4, V7, V10, V14 – – N/A
PLL_CFG[0:4] B8, C8, C7, D7, A7 High Input BVSEL
PMON_IN(13) D9 Low Input BVSEL
PMON_OUT A9 Low Output BVSEL
QACK G5 Low Input BVSEL
QREQ P4 Low Output BVSEL
SHD[0:1](3) E4, H5 Low I/O BVSEL
SMI F9 Low Input BVSEL
SRESET A2 Low Input BVSEL
SYSCLK A10 –Input BVSEL
TA K6 Low Input BVSEL
TBEN E1 High Input BVSEL
TBST F11 Low Output BVSEL
TCK C6 High Input BVSEL
TDI(6) B9 High Input BVSEL
TDO A4 High Output BVSEL
TEA L1 Low Input BVSEL
TEST[0:3](12) A12, B6 , B10, E10 –Input BVSEL
TEST[4](9) D10 –Input BVSEL
TMS(6) F1 High Input BVSEL
TRST(6)(14) A5 Low Input BVSEL
TS(3) L4 Low I/O BVSEL
TSIZ[0:2] G6, F7, E7 High Output BVSEL
TT[0:4] E5, E6, F6, E9, C5 High I/O BVSEL
WT(3) D3 Low Output BVSEL
VDD H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13,
M8, M10, M12 – – N/A
Table 16. Pinout Listing for the PC7447, 360 CBGA Package (Continued)
Signal Name Pin Number Active I/O I/F Select(1)
41
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD su pplies power to the processor core and
the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V) or to
HRESET (selects 2.5V). If used, the pull-down resistor should be less than 250 Ω. For actual recommended value of VIN or
supply voltages see Figure 3 on page 12.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for e xample, 4.7 kΩ) to maintain the control signals in the negated state after they
have been actively negated and released by the PC7447 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure
proper operation.
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the PC7447 is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.It is recommended this test signal be tied to HRESET; however, other configuration s wil l not adversely affect performance.
11.These signals are for factory use only and must be left unconnected for normal machine operation.
12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
13.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation
42 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Mechanical Dimensions for the PC7447, 360 CBGA
Figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7447, 360 CBGA package.
Figure 25. Mechanical Dimensions and Bottom Surf ace Nomenclature for the PC7447, 360 CBGA Package
Notes: 1. Dimensioning and tolerance per ASME Y14.5M, 1994
2. Dimensions in millimeters
3. Top side A1 corner inde x is a metallized f eature with various shapes. Bottom side A1 corner is designated with a ball missing
from the array
CA
360X
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
B0.3
C
0.15
b
U
W
V
123456789101112131415161718
19
0.2
2X
C
A1 CORNER
B
0.2
2X
D
E
E3
E2
E1
E4
D2
D4
D3 D1
Capacitor Region
1
A
0.15 A
0.35 A
AA1
A2
A3
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1
A2 1.10 1.30
A3 – 0.6
b 0.82 0.93
D 25 BSC
D1 – 11.3
D2 8 –
D3 – 6.5
D4 10.9 11.1
e 1.27 BSC
E 25 BSC
E1 – 11.3
E2 8 –
E3 – 6.5
E4 9.55 9.75
43
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Substrate Capacitors for the PC7447, 360 CBGA
Figure 26 shows the connectivity of the substrate capacitor pads for the PC7447, 360 CBGA. All capacitors are 100 nF.
Figure 26. Substrate Bypass Capacitors for the PC7447, 360 CBGA
Package Parameters for
the PC7457, 483 CBGA The package parameters are as p rovided in the following list. The package type is
29 ×29 mm, 483-lead ceramic ball grid array (CBGA).
Package outline 29 mm × 29 mm
Interconnects 483 (22 × 22 ball array - 1)
Pitch 1.27 mm (50 mil)
Minimum module height –
Maximum module height 3.22 mm
Ball diameter 0.89 mm (35 mil)
1
C1-2
C1-1 C2-1 C3-1 C4-1 C5-1 C6-1
C6-2C5-2C4-2C3-2C2-2
C18-1
C18-2 C17-2 C16-2 C15-2 C14-2 C13-2
C13-1C14-1C15-1C16-1C17-1
C12-1
C12-2 C11-2 C10-2 C9-2 C8-2 C7-2
C7-1C8-1C9-1
C10-1C11-1
C19-2
C19-1 C20-1 C21-1 C22-1 C23-1 C24-1
C24-2C23-2C22-2C21-2C20-2
A1 CORNER
C1 GND VDD
C2 GND VDD
C3 GND OVDD
C4 GND VDD
C5 GND VDD
C6 GND VDD
C7 GND VDD
C8 GND VDD
C9 GND OVDD
C10 GND VDD
C11 GND VDD
C12 GND VDD
C13 GND VDD
C14 GND VDD
C15 GND VDD
C16 GND OVDD
C17 GND VDD
C18 GND OVDD
C19 GND VDD
C20 GND VDD
C21 GND OVDD
C22 GND VDD
C23 GND VDD
C24 GND VDD
Capacitor Pad Number
-1 -2
44 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Figure 27 shows the pinout of the PC7457, 483 CBGA package as viewed from the top
surface.
Figure 28 shows the side profile of the CBGA package to indicate the direction of the top
surface view .
Figure 27. Pinout of the PC7 457 , 483 CBG A Package as Viewe d fro m the Top Sur face
Figure 28. Side View of the CBGA Package
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
123456789101112131415
16 17 18 19
U
V
W
20 21 22
Y
AA
AB
Encapsulant
Substrate Assembly View Die
45
PC7457/47 [Preliminary]
5345A–HIREL–11/03
.
Table 17. Pinout Listing for the PC7457, 483 CBGA Package
Signal Name Pin Number Active I/O I/F Select(1)
A[0:35](2) E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2, N2, P8, M8, W4,
N6, U6, R5, Y4, P1, P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4,
AA1, D10, J4, G10, D9 High I/O BVSEL
AACK U1 Low Input BVSEL
AP[0:4] L5, L6, J1, H2, G5 High I/O BVSEL
ARTRY(3) T2 Low I/O BVSEL
AVDD B2 – Input N/A
BG R3 Low Input BVSEL
BMODE0(4) C6 Low Input BVSEL
BMODE1(5) C4 Low Input BVSEL
BR K1 Low Output BVSEL
BVSEL(6)(7) G6 High Input N/A
CI(3) R1 Low Output BVSEL
CKSTP_IN F3 Low Input BVSEL
CKSTP_OUT K6 Low Output BVSEL
CLK_OUT N1 High Output BVSEL
D[0:63]
AB15, T14, R14, AB13, V14, U14, AB14, W16, AA11, Y11, U12,
W13, Y14, U13, T12, W12, AB12, R12, AA13, AB11, Y12, V11, T11,
R11, W10, T10, W11, V10, R10, U10, AA10, U9, V7, T8, AB4, Y6,
AB7, AA6, Y8, AA7, W8, AB10, AA16, AB16, AB17, Y18, AB18,
Y16, AA18, W14, R13, W15, AA14, V16, W6, AA12, V6, AB9, AB6,
R7, R9, AA9, AB8, W9
High I/O BVSEL
DBG V1 Low Input BVSEL
DP[0:7] AA2, AB3, AB2, AA8, R8, W5, U8, AB5 High I/O BVSEL
DRDY(8) T6 Low Output BVSEL
DTI[0:3])(9) P2, T5, U3, P6 High Input BVSEL
EXT_QUAL(10) B9 High Input BVSEL
GBL M4 Low I/O BVSEL
GND
A22, B1, B5, B12, B14, B16, B18, B20, C3, C9, C21, D7, D13, D15,
D17, D19, E2, E5, E21, F10, F12, F14, F16, F19, G4, G7, G17, G21,
H13, H15, H19, H5, J3, J10, J12, J14, J17, J21, K5, K9, K11, K13,
K15, K19, L10, L12, L14, L17, L21, M3, M6, M9, M11, M13, M19,
N10, N12, N14, N17, N21, P3, P9, P11, P13, P15, P19, R17, R21,
T13, T15, T19, T4, T7, T9, U17, U21, V2, V5, V8, V12, V15, V19,
W7, W17, W21, Y3, Y9, Y13, Y15, Y20, AA5, AA17, AB1, AB22
–– N/A
GVDD(11) B13, B15, B17, B19, B21, D12, D14, D16, D18, D21, E19, F13, F15,
F17, F21, G19, H12, H14, H17, H21, J19, K17, K21, L19, M17, M21,
N19, P17, P21, R15, R19, T17, T21, U19, V17, V21, W19, Y21 –– N/A
HIT(8) K2 Low Output BVSEL
HRESET A3 Low Input BVSEL
46 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Signal Name Pin Number Active I/O I/F Select(1)
INT J6 Low Input BVSEL
L1_TSTCLK(10) H4 High Input BVSEL
L2_TSTCLK(12) J2 High Input BVSEL
L3VSEL(6)(7) A4 High Input N/A
L3ADDR[18:0] H11, F20, J16, E22, H18, G20, F22, G22, H20, K16, J18, H22, J20,
J22, K18, K20, L16, K22, L18 High Output L3VSEL
L3_CLK[0:1] V22, C17 High Output L3VSEL
L3_CNTL[0:1] L20, L22 Low Output L3VSEL
L3DATA[0:63]
AA19, AB20, U16, W18, AA20, AB21, AA21, T16, W20, U18, Y22,
R16, V20, W22, T18, U20, N18, N20, N16, N22, M16, M18, M20,
M22, R18, T20, U22, T22, R20, P18, R22, M15, G18, D22, E20,
H16, C22, F18, D20, B22, G16, A21, G15, E17, A20, C19, C18, A19,
A18, G14, E15, C16, A17, A16, C15, G13, C14, A14, E13, C13,
G12, A13, E12, C12
High I/O L3VSEL
L3DP[0:7] AB19, AA22, P22, P16, C20, E16, A15, A12 High I/O L3VSEL
L3_ECHO_CLK[0,2] V18, E18 High Input L3VSEL
L3_ECHO_CLK[1,3] P20, E14 High I/O L3VSEL
LSSD_MODE(7)(13) F6 Low Input BVSEL
MCP B8 Low Input BVSEL
No Connect(14) A8, A11, B6, B11, C11, D11, D3, D5, E11, E7, F2, F11, G2, H9 – – N/A
OVDD
B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7, J5, K3, L7, M5, N3,
P7, R4, T3, U5, U7, U11, U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17,
Y19, AA4, AA15 –– N/A
PLL_CFG[0:4] A2, F7, C2, D4, H8 High Input BVSEL
PMON_IN(15) E6 Low Input BVSEL
PMON_OUT B4 Low Output BVSEL
QACK K7 Low Input BVSEL
QREQ Y1 Low Output BVSEL
SHD[0:1] L4, L8 Low I/O BVSEL
SMI G8 Low Input BVSEL
SRESET G1 Low Input BVSEL
SYSCLK D6 – Input BVSEL
TA N8 Low Input BVSEL
TBEN L3 High Input BVSEL
TBST B7 Low Output BVSEL
TCK J7 High Input BVSEL
TDI(7) E4 High Input BVSEL
TDO H1 High Output BVSEL
TEA T1 Low Input BVSEL
Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)
47
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Notes: 1. OVDD supplie s power to the processor bus, JTAG, and all control si gnals except the L3 cache controls (L3CTL[0:1]); GV DD
supplies power to the L3 cache interfa ce (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and L3_CLK[0:1])
and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the processor core and the PLL (after filtering to
become AVDD). For actual recommended value of VIN or supply voltages, see Table 3 on page 12.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for e xample, 4.7 kΩ) to maintain the control signals in the negated state after they
have been actively negated and released by the PC7457 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure
proper operation.
6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V).
To program the L3 interface, connect L3VSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). If used, pull-down
resistors should be less than 250Ω.
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode.
10.These input signals for factory use only and must be pulled down to GND for normal machine operation.
11.Power must be supplied to GVDD, even whe n the L3 interface is disabled or unused.
12.It is recommended that this test signal be tied to HRESET; however, other configurations will not adversely affect
performance.
13.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
14.These signals are for factory use only and must be left unconnected for normal machine operation.
15.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
17.These pins are internally connected to VDD. They are intended to allow an external device to detect the core voltage level
present at the processor core. If unused, they must be connected directly to VDD or left unconnected.
Signal Name Pin Number Active I/O I/F Select(1)
TEST[0:5](13) B10, H6, H10, D8, F9, F8 – Input BVSEL
TEST[6](10) A9 – Input BVSEL
TMS(7) K4 High Input BVSEL
TRST(7)(16) C1 Low Input BVSEL
TS(3) P5 Low I/O BVSEL
TSIZ[0:2] L1,H3,D1 High Output BVSEL
TT[0:4] F1, F4, K8, A5, E1 High I/O BVSEL
WT(3) L2 Low Output BVSEL
VDD J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15, M10, M12,
M14, N9, N11, N13, N15, P10, P12, P14 –– N/A
VDD_SENSE[0:1](17) G11, J8 – – N/A
Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)
48 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Mechanical Dimensions for the PC7457, 483 CBGA
Figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7457, 483 CBGA package.
Figure 29. Mechanical Dimensions and Bottom Surf ace Nomenclature for the PC7457, 483 CBGA Package
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994
2. Dimensions in millimeters
3. Top side A1 cor ner i ndex is a metallized feature with va rious shapes. Bottom side. A1 corner is designated with a b all miss-
ing from the array
CA
483X
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
B0.3
C
0.15
b
U
W
V
Y
AB
AA
123456789101112131415161718192021
22
Capacitor Region
A
0.15 A
0.35 A
AA1
A2
A3
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1
A2 1.10 1.30
A3 – 0.6
b 0.82 0.93
D 29 BSC
D1 – 12.5
D2 8.5 –
D3 – 8.4
D4 10.9 11.1
e 1.27 BSC
E 29 BSC
E1 – 12.5
E2 8.5 –
E3 – 8.4
E4 9.55 9.75
0.2
2X
C
A1 CORNER
B
0.2
2X
D
E
E3
E2
E1
E4
D2
D4
D3 D1
1
49
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Substrate Capacitors for the PC7457, 483 CBGA
Figure 26 shows the connectivity of the substrate capacitor pads for the PC7457, 483 CBGA. All capacitors are 100 nF.
Figure 30. Substrate Bypass Capacitors for the PC7457, 483 CBGA
1
C1-2
C1-1 C2-1 C3-1 C4-1 C5-1 C6-1
C6-2C5-2C4-2C3-2C2-2
C18-1
C18-2 C17-2 C16-2 C15-2 C14-2 C13-2
C13-1C14-1C15-1C16-1C17-1
C12-1
C12-2 C11-2 C10-2 C9-2 C8-2 C7-2
C7-1C8-1C9-1
C10-1C11-1
C19-2
C19-1 C20-1 C21-1 C22-1 C23-1 C24-1
C24-2C23-2C22-2C21-2C20-2
A1 CORNER
C1 GND OVDD
C2 GND VDD
C3 GND GVDD
C4 GND VDD
C5 GND VDD
C6 GND GVDD
C7 GND VDD
C8 GND VDD
C9 GND GVDD
C10 GND VDD
C11 GND VDD
C12 GND GVDD
C13 GND VDD
C14 GND VDD
C15 GND VDD
C16 GND OVDD
C17 GND VDD
C18 GND OVDD
C19 GND VDD
C20 GND VDD
C21 GND OVDD
C22 GND VDD
C23 GND VDD
C24 GND VDD
Capacitor Pad Number
-1 -2
50 PC7457/47 [Preliminary] 5345A–HIREL–11/03
System Design
Information This section provides system and t hermal design recommend ations for successful appli-
cation of the PC7457.
PLL Configuration The PC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus)
frequency, the PLL configuration signals set the internal CPU and VCO frequency of
operation. T he PLL conf igurat ion for the PC7 457 is shown in Table 18 for a set o f exam-
ple frequencies. In this example, shaded cells represent settings that, for a given
SYSCLK frequency, result in core and/or VCO frequencies that don’t comply with the
1 GHz column in Table 8 on page 20.
Table 18. PC7457 Microprocessor PLL Configuration Example for 1.3 GHz Parts
PLL_CFG[0:4]
Example Bus-to-Core Freque ncy in MHz (VCO Frequency in MHz)
Bus-to-Core
Multiplier Core-to-VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz 167
MHz
01000 2x 2x
10000 3x 2x 500
(1000)
10100 4x 2x 532
(1064) 667
(1333)
10110 5x 2x 500
(1000) 667
(1333) 835
(1670)
10010 5.5x 2x 550
(1100) 733
(1466) 919
(1837)
11010 6x 2x 600
(1200) 800
(1600) 1002
(2004)
01010 6.5x 2x 540
(1080) 650
(1300) 866
(1730) 1086
(2171)
00100 7x 2x 525
(1050) 580
(1160) 700
(1400) 931
(1862) 1169
(2338)
00010 7.5x 2x 500
(1000) 563
(1125) 623
(1245) 750
(1500) 1000
(2000) 1253
(2505)
11000 8x 2x 533
(1066) 600
(1200) 664
(1328) 800
(1600) 1064
(2128)
01100 8.5x 2x 566
(1132) 638
(1276) 706
1412) 850
(1700) 1131
(2261)
01111 9x 2x 600
(1200) 675
(1350) 747
(1494) 900
(1800) 1197
(2394)
01110 9.5x 2x 633
(1266) 712
(1524) 789
(1578) 950
(1900) 1264
(2528)
10101 10x 2x 500
(1000) 667
(1333) 750
(1500) 830
(1660) 1000
(2000)
10001 10.5x 2x 525
(1050) 700
(1400) 938
(1876) 872
(1744) 1050
(2100)
51
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Notes: 1. PLL_CFG[0:4] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
frequencies which are not useful, not supported, or not tested f or b y the PC7455; See “Clock AC Specifications” on page 20.
for valid SYSCLK, core, and VCO frequencies.
PLL_CFG[0:4]
Example Bus-to-Core Freque ncy in MHz (VCO Frequency in MHz)
Bus-to-Core
Multiplier Core-to-VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz 167
MHz
10011 11x 2x 550
(1100) 733
(1466) 825
(1650) 913
(1826) 1100
(2200)
00000 11.5x 2x 575
(1150) 766
(532) 863
(1726) 955
(1910) 1150
(2300)
10111 12x 2x 600
(1200) 800
(1600) 900
(1800) 996
(1992) 1200
(2400)
11111 12.5x 2x 600
(1200) 833
(1666) 938
(1876) 1038
(2076) 1250
(2500)
01011 13x 2x 650
(1300) 865
(1730) 975
(1950) 1079
(2158) 1300
(2600)
11100 13.5x 2x 675
(1350) 900
(1800) 1013
(2026) 1121
(2242)
11001 14x 2x 700
(1400) 933
(1866) 1050
(2100) 1162
(2324)
00011 15x 2x 500
(1000) 750
(1500) 1000
(2000) 1125
(2250) 1245
(2490)
11011 16x 2x 533
(1066) 800
(1600) 1066
(2132) 1200
(2400)
00001 17x 2x 566
(1132) 850
(1900) 1132
(2264) 1275
(2550)
00101 18x 2x 600
(1200) 900
(1800) 1200
(2400)
00111 20x 2x 667
(1334) 1000
(2000)
01001 21x 2x 700
(1400) 1050
(2100)
01101 24x 2x 800
(1600) 1200
(2400)
11101 28x 2x 933
(1866)
00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly
11110 PLL off PLL off, no core clocking occurs
Table 18. PC7457 Microprocessor PLL Configura tion Example for 1.3 GHz Parts (Continued)
52 PC7457/47 [Preliminary] 5345A–HIREL–11/03
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabl ed. However, the
bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, m ust be driven at one-half the
frequency of SYSCLK and offset in phase to meet the required input setup t IVKH and hold time tIXKH (see Table 9 on page
21). The result will be that the processor bus frequency will be one-half SYSCLK while the inte rnal processor i s clocked at
SYSCLK frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document don’t apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the PC7455 regardless of the SYSCLK input.
The PC7457 generates t he clock for the external L3 synchronous data SRAMs by divid-
ing the core clock frequency of the PC7457. The core-to-L3 frequency divisor for the L3
PLL is selected through the L3_CL K bits of the L3CR register. Generally, the diviso r
must be chosen according to the frequency supported by the external RAMs, the fre-
quency of the PC7457 core, and timing analysis of the circuit board routing.
Table 19 shows various example L3 clock frequencies that can be obtained for a given
set of core frequencies.
Notes: 1. The core and L3 frequencies are f or reference only. Note that maximum L3 frequency is design dependent. Some examples
may represent core or L3 frequencies which are not useful, not supporte d, or not tested for the PC7457; see “L3 Clock AC
Specifications” on page 23 f o r valid L3_CLK frequencies and for more information regarding the maximum L3 frequency.
2. These core frequencies are not supported by all speed grades; see Table 8 on page 20.
Table 19. Sample Core-to-L3 Frequencies(1)
Core
Frequency
(MHz) ÷2 ÷2.5 ÷3 ÷3.5 ÷4 ÷4.5 ÷5 ÷5.5 ÷6 ÷6.5 ÷7 ÷7.5 ÷8
500 250 200 167 143 125 111 100 91 83 77 71 67 63
533 266 213 178 152 133 118 107 97 89 82 76 71 67
550 275 220 183 157 138 122 110 100 92 85 79 73 69
600 300 240 200 171 150 133 120 109 100 92 86 80 75
650 325 260 217 186 163 144 130 118 108 100 93 87 81
666 333 266 222 190 167 148 133 121 111 102 95 89 83
700 350 280 233 200 175 156 140 127 117 108 100 93 88
733 367 293 244 209 183 163 147 133 122 113 105 98 92
800 400 320 266 230 200 178 160 145 133 123 114 107 100
866 433 347 289 248 217 192 173 157 145 133 124 115 108
933 467 373 311 266 233 207 187 170 156 144 133 124 117
1000 500 400 333 285 250 222 200 182 166 154 143 133 125
1050(2) 525 420 350 300 263 233 191 191 175 162 150 140 131
1100(2) 550 440 367 314 275 244 200 200 183 169 157 147 138
1150(2) 575 460 383 329 288 256 209 209 192 177 164 153 144
1200(2) 600 480 400 343 300 267 218 218 200 185 171 160 150
1250(2) 638 500 417 357 313 278 227 227 208 192 179 167 156
1300(2) 650 520 433 371 325 289 236 236 217 200 186 173 163
53
PC7457/47 [Preliminary]
5345A–HIREL–11/03
PLL Power Supply
Filtering The AVDD power signal is provided on the PC7457 to provide power to the clock gener-
ation PLL. To ensure stability of the internal clock, the power supplied to the AVDD input
signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency
range of the PLL. A circuit similar to the one shown in Figure 29 using surface mount
capacitors with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as clo se as possible to the AVDD pi n to minimize noise co u-
pled from nearby circuits. It is often possible to route directly from the capacitors to the
AVDD pin, which is on the periphery of the 360 CBGA footprint and very close to the
periphery of the 483 CBGA footprint, without the inductance of vias.
The PLL power supply filter provided in the PC7457 RISC Microprocessor Hardware
Specifications has be en found to be les s effective for Rev 1.1 devices with the low core
voltages described in this specification.
As a result, the recommended value for the resistor in the circuit is being evaluated and
a new recommendation is indicated in Figure 31. Motorola continues to evaluate the fil-
tering requirements of the PC7457 and will make updated recommendations as needed.
Note that this recommendation applies to Rev. 1.1 devices only.
Figure 31. PLL Power Supply Filter Circuit
Decoupling
Recommendations Due to the PC7457 dy namic power manage ment feature, large address an d data buses,
and high operating frequencies, the PC7457 can gen erate transient power surges an d
high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the PC7457 system,
and the PC7457 itself re quires a clean, tightly reg ulate d source of po wer. Th erefore , it is
recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, and GVDD pin of the PC7457. It is also recommended that these decoupling
capacitors receive their power from separate VDD, OVDD/GVDD, and GND power planes
in the PCB, utilizing short traces to minimize inductance.
These capacitor s should have a value of 0.0 1 or 0.1 µF. Only ceramic surfa ce mount
technology (SMT) capacitors should be used to minimize lead inductance, preferably
0508 or 0603 orientations where connections are made along the length of the part.
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec-
ommendations for decoupling Motorola microprocessors, multiple small capacitors of
equal value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the VDD, GVDD, an d OVDD planes, to enable qu ick recharging
of the smaller chip capacitors. These bulk capacitors should have a low equivalent
series resistance (ESR) rating to ensure the quick response time necessary. They
should also b e conn ec ted t o the p ower and g round planes through two vias to minimize
inductance. Suggested bulk capacitors: 100 – 330 µF (AVX TPS tantalum or Sanyo
OSCON).
VDD
400Ω
2.2 µF2.2 µF
GND
AVDD
Low ESL surface mount capacitor
54 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Connection
Recommendations To ensure r eliable operation, it is highly recomm ended to con nect unused inp uts to an
appropriate signal level. Unused active low inputs should be tied to OVDD. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD,
OVDD, GVDD, and GND pins in the PC7457. If the L3 interface is not used, GVDD should
be connected to the OVDD power plane, and L3VSEL should be connected to BVSEL;
the remainder of the L3 interface may be left unterminated.
Output Buffer DC
Impedance The PC7457 processor bus and L3 I/O drivers are characterized over process, voltage,
and temperature.
To measure Z0, an external resistor is connected from the chip pad to OVDD or GND.
Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 30
on page 49).
The output impedance is the average of two components, the resistances of the pull-up
and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is
trimmed until the voltage at the pad equals OVDD/2. RN then becom es th e res istanc e of
the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is
trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of
the pull-up devices. RP and RN are designed to be close to each other in value. Then,
Z0 = (RP + RN)/2.
Figure 32. Driver Impedance Measurement
Table 20 summarizes the sign al impedance results. The imp edance increases with junc-
tion temperature and is relatively unaffected by bus voltage.
Table 20. Impedan ce Ch ara cte rist ics with VDD = 1.5V, OVDD = 1. 8V ±5%, Tj = 5° - 85 °C
Impedance Processor bus L3 Bus Unit
Z0Typical 33 – 42 34 – 42 Ω
Maximum 31 – 51 32 – 44 Ω
OVDD
OGND
SW2
SW1
RN
RP
Pad
Data
55
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Pull-up/Pull-down
Resistor Requirements The PC74 57 requires hi gh-resistive (weak: 4.7 kΩ) pull-up resistors on several control
pins of the bus interface to maintain the control signals in the negated state after they
have been actively negated and released by the PC7457 or other bus masters. These
pins are TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must b e pulled up to OVDD or d own to
GND to ensure proper device operation. For the PC7447, 360 BGA, the pins that must
be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the pins that must be pulled
down to GND are L1_TSTCLK and TEST[4]. F or the PC7457, 483 BGA, the pins that
must be pulled up to OVDD are LSSD_MODE and TEST[0:5]; the pins that must be
pulled down are L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be
pulled up through a pull-up resistor (weak or stronger: 4.7 – 1 kΩ) to prevent erroneous
assertions of this signal. In addition, the PC7457 has one open-drain style output that
requires a pull-up resistor (weak or stronger: 4.7 – 1 kΩ) if it is used by the system. This
pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be
less than 250Ω (see Table 16 on page 39). Because PLL_CFG[0:4] must remain stable
during normal operation, strong pull-up and pull-down resistors (1 kΩ or less) are rec-
ommended to configure these signals in order to protect against erroneous switching
due to ground bounce, power supply noise or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be
driven by any master and may, therefore, float in the high-impedance state for relatively
long periods of time. Because the PC7457 must continually monitor these signals for
snooping, this float condition ma y cause exce ssive power draw by t he input receivers on
the PC7457 or by other re ceivers in the system. It is recommended that these signals be
pulled up through weak (4 .7 kΩ) pull-up resistors by the system, or that they may be oth-
erwise driven by the system during inactive periods of the bus. The snooped address
and transfer attribute inputs are A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND
through weak pull-down resistors. If the PC7457 is in 60x bus mode, DTI[0:3] must be
pulled low to GND through weak pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in
progress and, t herefore, don’t require pull-up resistors on the bus. Other data bus receiv-
ers in the system, however, may require pull-ups, or that those signals be otherwise
driven by the system during inactive periods by the system. The data bus signals are
D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is
disabled through HID0, the input receivers for those pins are disabled, and those pins
don’t require pull-up resistors and should be left unconnected by the system. If all parity
generation is disabled through HID0, then all parity checking should also be disabled
through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull- up resistors.
56 PC7457/47 [Preliminary] 5345A–HIREL–11/03
JTAG Configuration
Signals Boundary-s can testing is enab led through th e JTAG interface signals. The T RST signal
is optional in the IEEE 1149.1 specification, but is pr ovided on all processors that imple-
ment the PowerPC architecture. While it is possible to force the TAP controller to the
reset state using only the TCK and TMS sign als, more reliable power-on reset perfor-
mance will be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the com mon on-chip processor (COP)
function, simply tying TRST to HRESET is not practical.
The COP function of the se processors allows a remot e computer system (t ypically, a PC
with dedicated hardware an d debugging software) to access and control the in ternal
operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the
processor. If the target system has independent reset sources, such as voltage moni-
tors, watchdog timers, power supply failures, or push-butto n switches, then the COP
reset signals must be merged into these signals with logic.
The arrangement shown in Figure 31 allows the COP port to independently assert
HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG
interface and COP header will not be used, TRST should be tied to HRESET through a
0Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring t hat t he JTAG sca n chain is initialized during power-on. While Motor-
ola recommends that the COP header be designed into the system as shown in Figure
31 on page 53, if this is not possible, the isolation resistor will allow future access to
TRST in the case where a JTAG interface may need to be wired onto the system in
debug situations.
The COP header shown in Figure 31 adds many benefits – breakpoin ts, watchpoints,
register and memory examination /modification, and other standard debugger features
are possible throu gh this interface – and can be as inexpensive as an unpopulated foot-
print for a header to be added when needed.
The COP interface ha s a st an dar d hea der f or conn ect ion to the ta rg et syst em , b ased on
the 0.025" square-post, 0.100" centered header assembly (often called a Berg header).
The connector typically has pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 31; conse-
quently, many different pin numbers have been observed from emulator vendors. Some
are numbere d top-to-bottom the n left-to-right, while ot hers use left-to-righ t then top-to-
bottom, while still others number the pins counter clockwise from pin 1 (as with an IC).
Regardless of the numbering, the signal placement recommended in Figure 31 is com-
mon to all known emulators.
The QACK signal shown in Figure 31 is usually connected to the PCI bridge chip in a
system and is an input to the PC7457 informing it that it can go into the quiescent state.
Under normal operation this occurs during a low-power mode selection. In order for
COP to work, the PC7457 must see this signal asserted (pulled down). While shown on
the COP header, not all emulator products drive this signal. If the product does not, a
pull-down resistor can be populated to assert this signal. Additionally, some emulator
products implement open-drain type outputs and can only drive QACK asserted; for
these tools, a p ull-up resistor can be im plemented to ensure this signal is deasserted
when it is not being driven by the tool. Note that the pull-up a nd pull-down resistors on
the QACK signal are mutually exclusive and it is never necessary to populate both in a
system. To preserve correct power-down operation, QACK should be merged via logic
so that it also can be driven by the PCI bridge.
57
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Figure 33. JTAG Interface Connection
Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7457. Connect pin 5 of the COP
header to OV DD with a 10 kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate on ly if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an
AND gate to TRST of the part. If the JTAG interf ace is not implemented, connect HRESET from the target source to TRST of
the part through a 0Ω isolation resistor.
6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an additional GND pin for
improved signal integrity.
HRESET HRESET
HRESET
13 SRESET
SRESET SRESET
11
VDD_SENSE
6
5(1)
15
2 kΩ10 kΩ
10 kΩ
10 kΩ
OVDD
OVDD
OVDD
OVDD
CHKSTP_IN CHKSTP_IN
8TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4TRST
7
16
2
10
14(2)
Key
QACK
OVDD
OVDD
OVDD
TRST
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OVDD
QACK
QACK
CHKSTP_OUT
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 kΩ(4) OVDD
1
2 kΩ(3)
0Ω(5)
12(6)
NC
From Target
Board Sources
(if any)
COP Header
58 PC7457/47 [Preliminary] 5345A–HIREL–11/03
Definitions
Datasheet Status
Description
Life Support
Applications These products are not designed for use in life support appliances, devices or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Atmel customers using or selling these products for use in such applications do
so at their own risk and agree to fully indemnify Atmel for any damages resulting from
such improper use or sale.
Table 21. Datashee t Status
Datasheet Status Validity
Objective specification This datasheet contains target and goal
specifications for discussion with customer and
application validation. Bef ore design phase
Target specification This data sheet contains target or goal
specifications for product de velopment. Valid during the design phase
Preliminary specification
α-site
This datasheet contains preliminary data.
Additional data ma y be published later; could
include simulation results. Valid before characterization phase
Preliminary specification β-site This datasheet also contai ns characterization
results. Valid before the industrialization phase
Product specification This datasheet contains final product
specification. Valid for production purposes
Limiting Values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stre ss above one or more of the
limiting values may cause permanent damage to the device. These are stress ratings only and ope ration of the device at these or at
any other conditions above those giv en in the Characteristics sections of the specification is not implied. Exposure to limiting values for
extended periods may affect device reliability.
Application Information
Where application information is given, it is advisory and does not form part of the specification.
59
PC7457/47 [Preliminary]
5345A–HIREL–11/03
Ordering Information
Note: 1. For availability of the different versions, contact your local Atmel sales office.
PC 7457 V G U 1000 L x
Prefix
Type
Screening Level(1)
U: Upscreening
Revision Level(1)
Rev. B, C
Application modifier(1)
L: 1.3V ± 50 mV
N: 1.1V ± 50 mV
Max internal processor speed
1000 MHz
1300 MHz (TBC)
Temperature Range: Tj(1)
Prototype
(X)
V: -40°C, 110°C
M: -55°C +125°C
Package
G: CBGA
PC 7447 V G U 1000 L x
Prefix
Type
Screening Level(1)
U: Upscreening
Revision Level(1)
Rev. B, C
Application modifier(1)
L: 1.3V ± 50 mV
N: 1.1V ± 50 mV
Max internal processor speed
1000 MHz
1300 MHz (TBC)
Temperature Range: Tj(1)
Prototype
(X)
V: -40°C, 110°C
M: -55°C +125°C
Package
G: CBGA
GH: HITCE (TBC)
Printed on recycled paper.
Disclaimer: Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Ter ms and Conditions located on the Company’s web site. The Company assumes no responsibility fo r any
errors which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not author ized for use
as critical components in life suppor t devices or systems.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golde n Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR , Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-74 3
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
5345A–HIREL–11/03
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its
subsidiar ies. Powe rP C™ is t he t ra de ma rk of I BM C or p or at io n. Motorola is the registered trademar k of Motorola, Inc. AltiVec™ is a trademark
of M o t o ro l a , I n c . Oth er ter ms and product names may be the trademarks of others.
