Device Operating
Temperature Range Package
MC145193
SEMICONDUCTOR
TECHNICAL DATA
PLL FREQUENCY
SYNTHESIZER
ORDERING INFORMATION
MC145193F TA = –40 to 85°C SO–20
F SUFFIX
PLASTIC PACKAGE
CASE 751J
(SO–20)
20
1
PIN CONNECTIONS
Order this document by MC145193/D
120
19
18
17
16
15
14
13
2
3
4
5
6
7
8
(Top V iew)
REFout
LD
φR
REFin
Output A
VDD
12
9
Test 1 11
10 VCC
VPD
Gnd
PDout
Rx
fin
φV
Din
CLK
ENB
Output B
Test 2
fin
EVALUATION KIT
The MC145193EVK, which contains
hardware and software, is available.
1
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
1.1 GHz PLL Frequency
Synthesizer
The MC145193 is recommended for new designs and offers reduced
power consumption. The counters are programmed via a synchronous serial
port which is SPI compatible. The serial port is byte-oriented to facilitate
control via an MCU. Due to the innovative BitGrabber Plus registers, the
MC145193 may be cascaded with other peripherals featuring BitGrabber
Plus without requiring leading dummy bits or address bits in the serial data
stream. In addition, BitGrabber Plus peripherals may be cascaded with
existing BitGrabber peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor
tied from the Rx pin to ground. This current can be varied via the serial port.
Slew–rate control is provided by a special driver designed for the REFout
pin. This minimizes interference caused by REFout.
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external
crystal and a programmable reference output. The R, A, and N counters are
fully programmable. The C register (configuration register) allows the part to
be configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from
being loaded into the counters, on–board circuitry synchronizes the update
of the A register if the A or N counters are loading. Similarly, an update of the
R register is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented
to the three counters (R, A, and N) simultaneously.
•Maximum Operating Frequency: 1100 MHz @ – 10 dBm
•Operating Supply Current: 3 mA Nominal at 3.0 V
•Operating Supply Voltage Range (VDD, VCC, VPD Pins): 2.7 to 5.5 V
•Current Source/Sink Phase Detector Output:
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V
•Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
•R Counter Division Range: 1 and 5 to 8191
•Dual–Modulus Capability Provides Total Division up to 262,143
•High–Speed Serial Interface: 4 Mbps
•Output A Pin, When Configured as Data Out, Permits Cascading of
Devices
•Two General–Purpose Digital Outputs:
Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
•Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
•See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for
Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
Motorola, Inc. 2000 Rev 1
MC145193
2MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
ENB
REFin
Din
CLK
REFout
fin
fin
OSC or
4–Stage
Divider
(Configurable)
20
1
18
19
11
10
Output A
Input
AMP
Select
Logic
313
24
13–Stage R Counter
64/65
Prescaler Modulus
Control
Logic
12–Stage
N Counter
6–Stage
A Counter
Internal
Control
Shift
Register
And
Control
Logic
Standby
Logic POR
BitGrabber A Register
24 Bits
BitGrabber C Register
8 Bits
Double–buffered
BitGrabber R Register
16 Bits
Phase/Frequency
Detector B And Control
Phase/Frequency
Detector A And Control
Lock Detector
And Control
6 12
4
2
LD
Rx
PDout
φR
φV
Output B
(Open–
Drain
Output)
Test 2
Test 1
9
15
13
4
3
6
8
2
16
Supply Connections:
Pin 12 = VCC (V+ To Input AMP and 64/65 Prescaler)
Pin 5 = VPD (V+ To Phase/Frequency Detectors A and B)
Pin 14 = VDD (V+ To Balance Of Circuit)
Pin 7 = Gnd (Common Ground)
17
Data Out
fR
fV
Port
BLOCK DIAGRAM
This device contains 7,278 active transistors.
MC145193
3
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
MAXIMUM RATINGS* (Voltages Referenced to Gnd, unless otherwise stated)
Parameter Symbol Value Unit
DC Supply Voltage (Pins 12 and 14) VCC, VDD –0.5 to 6.0 V
DC Supply Voltage (Pin 5) VPD VDD – 0.5 to 6.0 V
DC Input Voltage Vin –0.5 to VDD + 0.5 V
DC Output V oltage (except Output B, PDout,
φR, φV)Vout –0.5 to VDD + 0.5 V
DC Output V oltage (Output B, PDout, φR, φV) Vout –0.5 to VPD + 0.5 V
DC Input Current, per Pin (Includes VPD) Iin, IPD ±10 mA
DC Output Current, per Pin Iout ±20 mA
DC Supply Current, VDD and Gnd Pins IDD ±30 mA
Power Dissipation, per Package PD300 mW
Storage Temperature Tstg –65 to 150 °C
Lead Temperature, 1 mm from Case for 10
Seconds TL260 °C
NOTES: 1.Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.
2.ESD (electrostatic discharge) immunity meets Human Body Model (HBM) ≤2000 V and
Machine Model (MM) ≤200 V. Additional ESD data available upon request.
ELECTRICAL CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V, Voltages Referenced to Gnd, unless otherwise stated; VPD = 2.7 to 5.5 V, TA = –40 to 85°C)
Parameter Test Condition Symbol Guaranteed
Limit Unit
Maximum Low–Level Input Voltage
(Din, CLK, ENB)VIL 0.3 x VDD V
Minimum High–Level Input Voltage
(Din, CLK, ENB)VIH 0.7 x VDD V
Minimum Hysteresis Voltage (CLK, ENB) VDD = 2.7 V
VDD = 4.5 V VHys 100
250 mV
Maximum Low–Level Output Voltage
(REFout, Output A) Iout = 20 µA, Device in Reference Mode VOL 0.1 V
Minimum High–Level Output Voltage
(REFout, Output A) Iout = – 20 µA, Device in Reference Mode VOH VDD – 0.1 V
Minimum Low–Level Output Current
(REFout, LD) Vout = 0.3 V IOL 0.36 mA
Minimum Low–Level Output Current
(φR, φV)Vout = 0.3 V IOL 0.36 mA
Minimum Low–Level Output Current
(Output A) Vout = 0.4 V
VDD = 4.5 V IOL 1.0 mA
Minimum Low–Level Output Current
(Output B) Vout = 0.4 V IOL 1.0 mA
Minimum High–Level Output Current
(REFout, LD) Vout = VDD – 0.3 V IOH –0.36 mA
Minimum High–Level Output Current
(φR, φV)Vout = VPD – 0.3 V IOH –0.36 mA
Minimum High–Level Output Current
(Output A Only) Vout = VDD – 0.4 V
VDD = 4.5 V IOH –0.6 mA
(continued)
This device contains protection circuitry
to guard against damage due to high static
voltages or electric fields. However, precau-
tions must be taken to avoid applications of
any voltage higher than maximum rated
voltages to this high–impedance circuit.
MC145193
4MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
Parameter Test Condition Symbol Guaranteed
Limit Unit
Maximum Input Leakage Current
(Din, CLK, ENB, REFin)Vin = VDD or Gnd, Device in XTAL Mode Iin ±1.0 µA
Maximum Input Current
(REFin)Vin = VDD or Gnd, Device in Reference Mode Iin ±100 µA
Maximum Output Leakage Current (PDout) Vout = VPD or Gnd, Output in Floating State IOZ ±130 nA
(Output B) Vout = VPD or Gnd, Output in High–Impedance State ±1µA
Maximum Standby Supply Current
(VDD + VPD Pins) Vin = VDD or Gnd; Outputs Open; Device in Standby Mode,
Shut–Down Crystal Mode or REFout–Static–Low Reference
Mode; Output B Controlling VCC per Figure 21
ISTBY 30 µA
Maximum Phase Detector
Quiescent Current (VPD Pin) Bit C6 = High Which Selects Phase Detector A,
PDout = Open, PDout = Static State, Bit C4 = Low Which is
not
Standby, IRx = 170 µA, VPD = 5.5 V
IPD 750 µA
Bit C6 = Low Which Selects Phase Detector B, φR and
φV = Open, φR and φV = Static Low or High, Bit
C4 = Low Which is
not
Standby
30
Total Operating Supply Current
(VDD + VPD + VCC Pins) fin = 2.0 GHz; REFin = 13 MHz @ 1 Vpp;
Output A = Inactive and No Connect; VDD = VCC,
REFout, φV, φR, PDout, LD = No Connect;
Din, ENB, CLK = VDD or Gnd, Phase Detector B Selected
(Bit C6 = Low)
IT[Note] mA
NOTE: The nominal value is: 3 mA at VDD = VCC = VPD = 3.0 V. This is not a guaranteed limit.
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PDout
(Iout ≤ 1 mA @ VDD = 2.7 V and Iout ≤ 1.7mA @ VDD ≥ 4.5 V, VDD = VCC = 2.7 to 5.5 V, Voltages Referenced to Gnd)
Parameter Test Condition VPD Guaranteed
Limit Unit
Maximum Source Current Variation (Part–to–Part) Vout = 0.5 x VPD 2.7 ±15 %
4.5 ±15
5.5 ±15
Maximum Sink–vs–Source Mismatch [Note 3] Vout = 0.5 x VPD 2.7 11 %
4.5 11
5.5 11
Output Voltage Range [Note 3] Iout Variation ≤15% 2.7 0.5 to 2.2 V
Iout Variation ≤20% 4.5 0.5 to 3.7
Iout Variation ≤22% 5.5 0.5 to 4.7
NOTES: 1.Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2.See Rx Pin Description for external resistor values.
3.This parameter is guaranteed for a given temperature within –40 to 85°C.
MC145193
5
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)
Parameter Figure
No. Symbol Guaranteed
Limit Unit
Serial Data Clock Frequency (Note: Refer to Clock tw below) 1 fclk dc to 4.0 MHz
Maximum Propagation Delay, CLK to Output A (Selected as Data Out) 1, 5 tPLH, tPHL 100 ns
Maximum Propagation Delay, ENB to Output A (Selected as Port) 2, 5 tPLH, tPHL 150 ns
Maximum Propagation Delay, ENB to Output B 2, 6 tPZL, tPLZ 150 ns
Maximum Output Transition Time, Output A and Output B; tTHLonly, on Output B 1, 5, 6 tTLH, tTHL 50 ns
Maximum Input Capacitance – Din, ENB, CLK Cin 10 pF
TIMING REQUIREMENTS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)
Parameter Figure
No. Symbol Guaranteed
Limit Unit
Minimum Setup and Hold T imes, Din vs CLK 3 tsu, th50 ns
Minimum Setup, Hold and Recovery T imes, ENB vs CLK 4 tsu, th, trec 100 ns
Minimum Pulse Width, ENB 4 tw[Note] cycles
Minimum Pulse Width, CLK 1 tw125 ns
Maximum Input Rise and Fall T imes, CLK 1 tr, tf100 µs
NOTE: The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
MC145193
6MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
SWITCHING WAVEFORMS
Figure 1. Figure 2.
10%
VDD
Gnd
1/fclk
Output A
(Data Out)
CLK
90%
50%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
tw
tftr
ENB
Output A
Output B 10%
VDD
Gnd
50%
50%
tPLZ
tPLH tPHL
50%
tPZL
Figure 3. Figure 4.
Din
CLK
50%
Valid
50%
tsu thVDD
Gnd
VDD
Gnd
CLK
ENB
50%
tsu th
First
CLK Last
CLK
trec
50%
VDD
Gnd
VDD
Gnd
twtw
Figure 5. Figure 6.
Test Point
Device
Under
Test CL*
*Includes all probe and fixture capacitance.
Test Point
Device
Under
Test CL*
*Includes all probe and fixture capacitance.
+VPD
7.5 kΩ
MC145193
7
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
LOOP SPECIFICATIONS (VDD = VCC = 2.7 to 5.5 V unless otherwise indicated, TA = –40 to 85°C)
Fig.
Guaranteed
Operating
Range
Parameter Test Condition
Fig
.
No. Symbol Min Max Unit
Input Sensitivity Range, fin 100 MHz ≤ fin ≤ 1100 MHz 7 Pin – 10 4 dBm*
Input Frequency, REFin Externally Driven in
Reference Mode Vin ≥ 400 mVpp 2.7 ≤ VDD < 4.5 V
4.5 ≤ VDD ≤ 5.5 V 8 fref 1.5
1.5 20
30 MHz
Crystal Frequency, Crystal Mode C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray
Capacitance 9 fXTAL 2 15 MHz
Output Frequency, REFout CL = 20 pF, Vout ≥ 1 Vpp 10, 12 fout dc 10 MHz
Operating Frequency of the Phase Detectors fφdc 2 MHz
Output Pulse Width (φR, φV, and LD) fR in Phase with fV, CL = 20 pF, φR and φV
active for LD measurement, **
VPD = 2.7 to 5.5 V VDD = 2.7 V
VDD = 4.5 V
VDD = 5.5 V
11, 12 tw
40
18
14
120
60
50
ns
Output T ransition Times (LD, φV, and φR) CL = 20 pF, VPD = 2.7 V,
VDD = VCC = 2.7 V 11, 12 tTLH,
tTHL — 80 ns
Input Capacitance, REFin Cin — 7 pF
*Power level at the input to the dc block.
**When PDout is active, LD minimum pulse width is approximately 5 ns.
Figure 7. Test Circuit
Sine Wave
Generator
50 Ω
Device
Under
Test
0.01 µFTest
Point
VCC VDD
REFin
Gnd
Output A
Vin
Figure 8. Test Circuit — Reference Mode
(fR)
Test
Point
REFout
V+
Device Under
Test
C1
Test
Point
VCC VDD
Output A
Gnd
REFin
REFout
C2
Figure 9. Test Circuit — Crystal Mode
(fR)
V+
50%
REFout
1/f REFout
Figure 10. Switching Waveform
10%
90%
Output
tTLH
tTHL
Figure 11. Switching Waveform
50%
tw
Figure 12. Test Circuit
DC
Block
50 Ω PAD
Sine Wave
Generator
50 Ω
VCC VDD
Gnd V+
Test
Point
Output A (fV)
Device
Under
Test
fin
fin
NOTE: Alternately, the 50 Ω pad may be a T network.
Test Point
Device
Under
Test CL*
*Includes all probe and fixture capacitance.
MC145193
8MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
3
4
2
2
1
1
4
3
3 V
5 V
fin (PIN 11)
SOG PACKAGE
Figure 13. Normalized Input Impedance at fin — Series Format (R + jx)
Table 1. Input Impedence at fin — Series Format (R + jx), VCC = 3 V
Marker Frequency
(GHz) Resistance
(Ω)Reactance
(Ω)Capacitance/
Inductance
1 0.5 11.4 –168 1.9 pF
2 1 12.4 –59.4 2.68 pF
Table 2. Input Impedence at fin — Series Format (R + jx), VCC = 5 V
Marker Frequency
(GHz) Resistance
(Ω)Reactance
(Ω)Capacitance/
Inductance
1 0.5 11.8 –175 1.82 pF
2 1 11.5 –64.4 2.47 pF
MC145193
9
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
Din
Serial Data Input (Pin 19)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 3). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB.
CAUTION
The value programmed for the N counter must be
greater than or equal to the value of the A counter.
The 13 least significant bits (LSBs) of the R register are
double–buf fered. As indicated above, data is latched into the
first buffer on a 16–bit transfer. (The 3 MSBs are not
double–buf fered and have an immediate effect after a 16–bit
transfer.) The second buffer of the R register contains the 13
bits for the R counter. This second buffer is loaded with the
contents of the first buffer when the A register is loaded (a
24–bit transfer). This allows presenting new values to the R,
A, and N counters simultaneously. If this is not required, then
the 16–bit transfer may be followed by pulsing ENB low with
no signal on the CLK pin. This is an alternate method of
transferring data to the second buffer of the R register (see
Figure 16).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber Plus registers. Therefore, all bits
in the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.7 to 5.5 V. The formats are
shown in Figures 14, 15, and 16.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ
to 10 kΩ must be used. Parameters to consider when sizing
the resistor are worst–case IOL of the driving device,
maximum tolerable power consumption, and maximum data
rate.
Table 3. Register Access
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
Number
of Clocks Accessed
Register Bit
Nomenclature
8
16
24
Other Values ≤ 32
Values > 32
C Register
R Register
A Register
Not Allowed
See Figures
22 – 25
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
CLK
Serial Data Clock Input (Pin 18)
Low–to–high transitions on CLK shift bits available at the
Din pin, while high–to–low transitions shift bits from Output A
(when configured as Data Out, see Pin 16). The
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A
register . See Table 3 and Figures 14, 15, and 16. The number
of clocks required for cascaded devices is shown in Figures
23 through 25.
CLK typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of Din for more
information. NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
Gnd (with ENB being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK
being a don’t care) during power–up. Floating,
toggling, or having these pins in the wrong state
during power–up does not harm the chip, but
causes two potentially undesirable effects. First,
the outputs of the device power up in an unknown
state. Second, if two devices are cascaded, the A
Registers must be written twice after power up.
After these two accesses, the two cascaded chips
perform normally.
ENB
Active Low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an
inactive high state, shifting is inhibited and the port is held in
the initialized state. To transfer data to the device, ENB
(which must start inactive high) is taken low, a serial transfer
is made via Din and CLK, and ENB is taken back high. The
low–to–high transition on ENB transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 3.
Transitions on ENB must not be attempted while CLK is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB is high
and CLK is low.
This input is also Schmitt–triggered and switches near
50% of VDD, thereby minimizing the chance of loading
erroneous data into the registers. See the last paragraph of
Din for more information.
For POR information, see the note for the CLK pin.
MC145193
10 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
Output A
Configurable Digital Output (Pin 16)
Output A is selectable as fR, fV, Data Out, or Port. Bits A22
and A23 in the A register control the selection; see Figure 15.
If A23 = A22 = high, Output A is configured as fR. This
signal is the buffered output of the 13–stage R counter. The
fR signal appears as normally low and pulses high. The fR
signal can be used to verify the divide ratio of the R counter.
This ratio extends from 5 to 8191 and is determined by the
binary value loaded into bits R0–R12 in the R register. Also,
direct access to the phase detectors via the REFin pin is
allowed by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate is
2 MHz. Therefore, the frequency of fR should not exceed
2 MHz.
If A23 = high and A22 = low, Output A is configured as fV.
This signal is the buffered output of the 12–stage N counter.
The fV signal appears as normally low and pulses high. The
fV signal can be used to verify the operation of the prescaler,
A counter, and N counter. The divide ratio between the fin
input and the fV signal is N × 64 + A. N is the divide ratio of the
N counter and A is the divide ratio of the A counter. These
ratios are determined by bits loaded into the A register. See
Figure 15. The maximum frequency at which the phase
detectors operate is 2 MHz. Therefore, the frequency of fV
should not exceed 2 MHz.
If A23 = low and A22 = high, Output A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the CLK input. Upon power up, Output A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, Output A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander . This signal is low when the Port bit
(C1) of the C register is low, and high when the Port bit is
high.
Output B
Open–Drain Digital Output (Pin 15)
This signal is a general–purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (C0) of the C register is low. When the Out B bit
is high, Output B assumes the high–impedance state. Output
B may be pulled up through an external resistor or active
circuitry to any voltage less than or equal to the potential of
the VPD pin. Note: the maximum voltage allowed on the VPD
pin is 5.5 V.
Upon power–up, power–on reset circuitry forces Output B
to a low level.
REFERENCE PINS
REFin and REFout
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–resonant
crystal. Frequency–setting capacitors of appropriate values,
as recommended by the crystal supplier, are connected from
each of the two pins to ground (up to a maximum of 30 pF
each, including stray capacitance). An external resistor of
1 MΩ to 15 MΩ is connected directly across the pins to
ensure linear operation of the amplifier. The required
connections for the components are shown in Figure 9.
To turn on the oscillator , bits R15, R14, and R13 must have
an octal value of one (001 in binary, respectively). This is the
active–crystal mode shown in Figure 16. In this mode, the
crystal oscillator runs and the R Counter divides the crystal
frequency , unless the part is in standby. If the part is placed in
standby via the C register, the oscillator runs, but the R
counter is stopped. However, if bits R15 to R13 have a value
of 0, the oscillator is stopped, which saves additional power.
This is the shut–down crystal mode (shown in Figure 16) and
can be engaged whether in standby or not.
In the reference mode, REFin (Pin 20) accepts a signal
from an external reference oscillator, such as a TCXO. A
signal swinging from at least the VIL to VIH levels listed in the
Electrical Characteristics table may be directly coupled to the
pin. If the signal is less than this level, ac coupling must be
used as shown in Figure 8. Due to an on–board resistor
which is engaged in the reference modes, an external biasing
resistor tied between REFin and REFout is not required.
With the reference mode, the REFout pin is configured as
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REFout is
the REFin frequency divided by 16. In addition, Figure 16
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REFout pin is listed
in the Loop Specifications table for an output swing of 1 Vpp
and 20 pF loads. Therefore, for higher REFin frequencies, the
one–to–one ratio may not be used for this magnitude of
signal swing and loading requirements. Likewise, for REFin
frequencies above two times the highest rated frequency, the
ratio must be more than two.
The output has a special on–board driver that has
slew–rate control. This feature minimizes interference in the
application.
If REFout is unused, an octal value of two should be used
for R15, R14, and R13 and the REFout pin should be floated.
A value of two allows REFin to be functional while disabling
REFout, which minimizes dynamic power consumption.
LOOP PINS
fin and fin
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These
pins feed the on–board RF amplifier which drives the 64/65
prescaler. These inputs may be fed differentially. However,
they are usually used in a single–ended configuration (shown
in Figure 7). Note that fin is driven while fin must be tied to
ground via a capacitor.
Motorola does not recommend driving fin while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
MC145193
11
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
PDout
Single–Ended Phase/Frequency Detector Output (Pin 6)
This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a
linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR:
current–sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR:
current–sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR:
current–sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR:
current–sinking pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the
high–impedance state by utilization of the disable feature in
the C register (bit C6). This is a patented feature. Similarly,
PDout is forced to the high–impedance state when the device
is put into standby (STBY bit C4 = high).
The PDout circuit is powered by VPD. The phase detector
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PDout current divided by 2π.
φR and φV (Pins 3 and 4)
Double–Ended Phase/Frequency Detector Outputs
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized by
a linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: φV =
negative pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV =
essentially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR =
negative pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR =
essentially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and
interchanged via C register bits C6 or C4. This is a patented
feature. Note that when disabled or in standby , φR and φV are
forced to their rest condition (high state).
The φR and φV output signal swing is approximately from
Gnd to VPD.
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when fV
and fR are out of phase or different frequencies. LD is the
logical ANDing of φR and φV (see Figure 17).
This output can be enabled and disabled via the C register .
This is a patented feature. Upon power up, on–chip
initialization circuitry disables LD to a static low logic level to
prevent a false “lock” signal. If unused, LD should be disabled
and left open.
The LD output signal swing is approximately from Gnd to
VDD.
Rx
External Resistor (Pin 8)
A resistor tied between this pin and Gnd, in conjunction
with bits in the C register, determines the amount of current
that the PDout pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PDout;
see Tables 4 and 5 for other current values. The
recommended value for Rx is 3.9 kΩ (preliminary). A value of
3.9 kΩ provides current at the PDout pin of approximately 1
mA @ VDD = 3 V and approximately 1.7 mA @ VDD = 5 V in
the 100% current mode. Note that VDD, not VPD, is a factor in
determining the current.
When the φR and φV outputs are used, the Rx pin may be
floated.
Table 4. PDout Current*, C1 = Low with
Output A
not
Selected as “Port”;
Also, Default Mode When Output A
Selected as “Port”
Bit C3 Bit C2 PDout Current*
0
0
1
1
0
1
0
1
70%
80%
90%
100%
*At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
Table 5. PDout Current*, C1 = High with
Output A
not
Selected as “Port”
Bit C3 Bit C2 PDout Current*
0
0
1
1
0
1
0
1
25%
50%
75%
100%
*At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
MC145193
12 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
TEST POINT PINS
Test 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64. CAUTION
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
Test 2
Prescaler Output (Pin 13)
This pin may be used to access the on–board 64/65
prescaler output. CAUTION
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
POWER SUPPLY PINS
VDD
Positive Power Supply (Pin 14)
This pin supplies power to the main CMOS digital portion
of the device. Also, this pin, in conjunction with the Rx
resistor, determines the internal reference current for the
PDout pin. The voltage range is 2.7 to 5.5 V with respect to
the Gnd pin.
For optimum performance, VDD should be bypassed to
Gnd using a low–inductance capacitor mounted very close to
these pins. Lead lengths on the capacitor should be
minimized.
VCC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65
prescaler. The voltage range is 2.7 to 5.5 V with respect to
the Gnd pin. In standby mode, the VCC pin still draws a few
milliamps from the power supply. This current drain can be
eliminated with the use of transistor Q1 as shown in
Figure 21.
For optimum performance, VCC should be bypassed to
Gnd using a low–inductance capacitor mounted very close to
these pins. Lead lengths on the capacitor should be
minimized.
VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin may be more or less
than the potential applied to the VDD and VCC pins. The
voltage range for VPD is 2.7 to 5.5 V with respect to the Gnd
pin.
For optimum performance, VPD should be bypassed to
Gnd using a low–inductance capacitor mounted very close to
these pins. Lead lengths on the capacitor should be
minimized.
Gnd
Ground (Pin 7)
Common ground.
MC145193
13
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
ENB
CLK
Din
MSB LSB
C7 C6 C5 C4 C3 C2 C1 C0
12345678
NOTE
NOTE: At this point, the new byte is transferred to the C register and stored. No other
registers are affected.
Figure 14. C Register Access and Format
(8 Clock Cycles are Used)
C7 – POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout
and interchanges the φR function with φV as depicted in Figure 17. Also see the phase detector output
pin descriptions for more information. This bit is cleared low at power up.
C6 – PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing φR and φV
to the static high state. When cleared low, phase/frequency detector B is enabled (φR and φV) and
phase/frequency detector A is disabled with PDout forced to the high–impedance state. This bit is
cleared low at power up.
C5 – LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced
to a static low level. This bit is cleared low at power up.
C4 – STBY: When set, places the CMOS section of device, which is powered by the VDD and VPD pins, in the
standby mode for reduced power consumption: PDout is forced to the high–impedance state, φR and
φV are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut
off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained in the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REFout = static low is selected, the internal feedback resistor is disconnected and the input is inhibited
when in standby; in addition, the REFin input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.
When C4 is reset low, the part is taken out of standby in two steps. First, the REFin (only in one
mode) resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and
fV signals are inhibited from toggling the phase/frequency detectors and lock detector. Second, when
the first fV pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors
are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase and lock detectors. (Patented feature.)
C3, C2 – I2, I1: Controls the PDout source/sink current per Tables 4 and 5. With both bits high, the maximum current
is available. Also, see C1 bit description.
C1 – Port: When the Output A pin is selected as “Port” via bits A22 and A23, C1 determines the state of Output
A. When C1 is set high, Output A is forced high; C1 low forces Output A low. When Output A is
not
selected as “Port,” C1 controls whether the PDout step size is 10% or 25%. (See Tables 4 and
5.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when Output A is
selected as “Port.” The Port bit is not affected by the standby mode.
C0 – Out B: Determines the state of Output B. When C0 is set high, Output B is high–impedance; C0 low forces
Output B low. The Out B bit is not affected by the standby mode. This bit is cleared low at power
up.
MC145193
14 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
ÇÇ
ÇÇ
A22
ÇÇ
A21
ÇÇ
A20
ÇÇ
ÇÇ
A19
ÇÇ
A18
ÇÇ
ÇÇ
A17
ÇÇ
A16
ÇÇ
A15
ÇÇ
A14
ÇÇ
A13
ÇÇ
A12
ÇÇ
A11
ÇÇ
ÇÇ
A10
ÇÇ
A9
ÇÇ
ÇÇ
A8
ÇÇ
A7
ÇÇ
A6
ÇÇ
A5
ÇÇ
A4
ÇÇ
ÇÇ
A3
ÇÇ
A2
ÇÇ
ÇÇ
A1
ÇÇ
ÇÇ
ÇÇ
A0
ÇÇ
ÇÇ
ÇÇ
ÇÇ
A23
Note 3
234567891011121314151617181920212223241
1 1
MSB LSB
0
0
1
1
0
1
0
1
Port
Data Out
f
fV
R
Binary
Value Output A
Function
(Note 1)
Both Bits
Must Be
High
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
N COUNTER = 5
N COUNTER = 6
N COUNTER = 7
÷
÷
÷
.
.
.
F
F
.
.
.
F
F
.
.
.
E
FN COUNTER = 4094
N COUNTER = 4095
÷
÷
Hexadecimal Value
For N Counter
0
0
0
0
3
0
1
2
3
E
A COUNTER = 0
A COUNTER = 1
A COUNTER = 2
A COUNTER = 3
A COUNTER = 62
÷
4 1 Not Allowed
Hexadecimal Value
For A Counter
3
4F
0A COUNTER = 63
Not Allowed ÷
.
.
.
F
.
.
.
F Not Allowed
÷
÷
÷
÷
.
.
..
.
.
NOTES:
1. A power-on initialize circuit forces the Output A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This result s in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register’s second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.
ENB
CLK
Din
Figure 15.
Figure 15. A Register Access and Format
(24 Clock Cycles are Used)
MC145193
15
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
ENB
CLK
Din
12345678
MSB LSB
R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R11R12R13R14R15
9 10111213141516
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
1
2
3
4
5
6
7
8
·
·
·
E
F
Not Allowed
R COUNTER = ÷ 1 (Note 6)
Not Allowed
Not Allowed
Not Allowed
R COUNTER = ÷5
R COUNTER = ÷6
R COUNTER = ÷7
R COUNTER = ÷8
R COUNTER = ÷8190
R COUNTER = ÷8191
Hexadecimal Value
0
0
0
0
0
0
0
0
0
·
·
·
1
1
Binary Value
0
1
2
3
4
5
6
7
Crystal Mode, Shut Down
Crystal Mode, Active
Reference Mode, REFin Enabled and REFout
Static Low
Reference Mode, REFout = REFin (Buffered)
Reference Mode, REFout = REFin/2
Reference Mode, REFout = REFin/4
Reference Mode, REFout = REFin/8 (Note 3)
Reference Mode, REFout = REFin/16
Octal Value
NOTES:
1 Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).
2 Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).
3 A power–on initialize circuit forces a default REFin to REFout ratio of eight.
4 At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 – R12
are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered yet
and retains the previous ratio loaded. The C and A registers are not affected.
5 Optional load pulse. At this point, bits R0 – R12 are transferred to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A
registers are not affected. The first buffer of the R register is not affected. Also, see Note 3 of Figure 15 for an alternate method of loading
the second buffer in the R register.
6 Allows direct access to reference input of phase/frequency detectors.
Note
4Note
5
Figure 16. R Register Access and Format
(16 Clock Cycles are Used)
MC145193
16 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
NOTE: The PDout either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output is in the floating condition and
the voltage at that pin is determined by the low–pass filter capacitor. PDout, φR, and φV are shown with the polarity bit (POL) = low; see Figure 14 for POL.
fR
Reference
REFin ÷R
fV
Feedback
fin ÷(N x 64 + A)
PDout
φR
φV
LD
VH
VL
Sourcing Current
VH
VH
VL
Float
VH
VL
VL
VL
VH
*
Sinking Current
VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.
Figure 17. Phase/Frequency Detectors and Lock
Detector Output Waveforms
MC145193
17
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
DESIGN CONSIDERATIONS
Crystal Oscillator Considerations
The following options may be considered to provide a
reference frequency to Motorola’s CMOS frequency
synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated
crystal oscillators (TCXOs) or crystal–controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of CMOS logic levels at the output may be
direct or dc coupled to REFin. If the oscillator does not have
CMOS logic levels on the outputs, capacitive or ac coupling
to REFin may be used (see Figure 8).
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the
eem
Electronic Engineers Master Catalog,
the
Gold Book,
or
similar publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications. The reference signal is usually ac
coupled to REFin (see Figure 8). For large amplitude signals
(standard CMOS logic levels), dc coupling may be used.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference
source frequency. A fundamental mode crystal, parallel
resonant at the desired operating frequency, should be
connected as shown in Figure 18.
The crystal should be specified for a loading capacitance
(CL) which does not exceed approximately 20 pF when used
at the highest operating frequencies listed in the Loop
Specifications table. Assuming R1 = 0 Ω, the shunt load
capacitance (CL) presented across the crystal can be
estimated to be:
CL = CinCout
Cin + Cout + Ca + Cstray + C1 •C2
C1 + C2
where Cin = 5 pF (see Figure 19)
Cout = 6 pF (see Figure 19)
Ca = 1 pF (see Figure 19)
C1 and C2 = external capacitors (see Figure 18)
Cstray = the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
REFin and REFout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
Circuit stray capacitance can also be handled by adding the
appropriate stray value to the values for Cin and Cout. For this
approach, the term Cstray becomes 0 in the above expression
for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 20. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency (fR) at Output A as a function of supply voltage.
(REFout is not used because loading impacts the oscillator.)
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in
frequency or becomes unstable with an increase in supply
voltage. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start–up time is
proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
(see Table 6).
R1*
C2C1
Frequency Synthesizer
REFout
REFin Rf
*May be needed in certain cases. See text.
Figure 18. Pierce Crystal Oscillator Circuit
Cin Cout
Ca
REFin REFout
Cstray
Figure 19. Parasitic Capacitances of the
Amplifier and Cstray
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
2
1
2
121
RSLSCS
ReXe
CO
Figure 20. Equivalent Crystal Networks
MC145193
18 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”,
Proc. IEEE,
Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”,
Electro–Technology
, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”,
Electronic
Design
, May 1966.
D. Babin, “Designing Crystal Oscillators”,
Machine Design
,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design
, April 25, 1985.
Table 6. Partial List of Crystal
Manufacturers
CTS Corp.
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Motorola cannot recommend
one supplier over another and in no
way suggests that this is a complete
listing of crystal manufacturers.
MC145193
19
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
F(s) =
Assuming Gain A is very large, then:
Z(s) =
ζ =
ωn =
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
(B)
A
C
R2
C
VCO
(A)
φR
φV
R1
R1R2
KφKVCO
NC
R
2
sC
ωn = KφKVCO
NCR1
ζ = ωnR2C
2
R2sC + 1
R1sC
NOTE:
For (B), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the midpoint
to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not significantly
affect ωn.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = IPDout/2π amps per radian for PDout
Kφ (Phase Detector Gain) = VPD/2π volts per radian for φV and φR
KVCO (VCO Transfer Function) = 2π∆fVCO
∆VVCO
For a nominal design starting point, the user might consider a damping factor ζ ≈0.7 and a natural loop frequency ωn ≈ (2πfR/50) where fR
is the frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering, higher fR–related
VCO sidebands.
RECOMMENDED READING:
Gardner, Floyd M.,
Phaselock Techniques (second edition).
New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim,
Frequency Synthesizers: Theory and Design (second edition).
New York, Wiley–Interscience, 1980.
Blanchard, Alain,
Phase–Locked Loops: Application to Coherent Receiver Design.
New York, Wiley–Interscience, 1976.
Egan, William F.,
Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L.,
Digital PLL Frequency Synthesizers Theory and Design.
Englewood Clif fs, NJ, Prentice–Hall, 1983.
Berlin, Howard M.,
Design of Phase–Locked Loop Circuits, with Experiments.
Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold,
The PLL Synthesizer Cookbook.
Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H.,
Integrated Circuits Applications Handbook
, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,”
EDN
. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from
Electronic Design,
1987.
AN1253, An Improved PLL Design Method Without ωn and ζ, Motorola Semiconductor Products, Inc., 1995.
–
+
KVCOC
N
Kφ
1 + sRC
NOTE:
For (A), using Kφ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/filter
combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ωc = 1/RC′ should be chosen
such that ωn is not significantly affected.
C
VCO
R
PDout
radians per volt
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This additional
filtering may be active or passive.
=ωnRC
2
MC145193
20 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
Threshold
Detector
Low–pass
Filter
NC
1000 pF
UHF
VCO
Integrator MCU
+3 V
General–purpose
Digital Output
+3 V
REFout REFin
VCC
VDD
Gnd
LD
φR
φV
VPD
PDout
Rx
Test 1
fin
fin
Test 2
Output B
Output A
ENB
CLK
Din
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
Q1
NC
+ 3 V
UHF Output
Buffer
Note 2
NOTES:
1 When used, the φR and φV outputs are fed to an external combiner/loop filter. See the Phase–
Locked Loop — Low–Pass Filter Design (Page 19) for additional information.
2 T ransistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section
of the device to be shut down via use of the general–purpose digital pin, Output B. If the standby
feature is not needed, tie Pin 12 directly to the power supply.
3 For optimum performance, bypass the VCC, VDD, and VPD pins to Gnd with low–inductance ca-
pacitors.
4 The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution
required for the VCO. Also, the VCO frequency divided by fR = NT = N x 64 + A; this determines
the values (N, A) that must be programmed into the N and A counters, respectively.
Figure 21. Example Application
CMOS
MCU
Output A
(Data Out)
ENBCLKDin
Device #1
(MC145193 or MC145202–1) Output A
(Data Out)
ENB
CLKDin
Device #2
(MC145193 or MC145202–1)
Optional
NOTE: See related Figures 23, 24, and 25.
Figure 22. Cascading Two Devices
MC145193
21
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
Figure 23. Figure 24.
1 2 7 8 910 15161718 23242526 3132
C Register Bits of Device #2
in Figure 22 C Register Bits of Device #1
in Figure 22
*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.
C7 C6 C0 X X X X X X C7 C6 C0
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
*
ENB
CLK
Din
12 7 8 9 151617 232425 3132
A Register bits of Device #2
in Figure 22 A Register Bits of Device #1
in Figure 22
A23 A22 A16 A15 A8 A7 A0 A23 A16
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
38 39 40 47 48
A9 A8 A0
*
ENB
CLK
Din
* At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, t he
13 LSBs in each of the first buffers of the R registers are transferred to the respective R register’s second buffer. Thus, the
R, N, and A counter can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
Neither C register is affected.
Figure 23. Accessing the C Registers of
Two Cascaded MC145193 or MC145202–1 Devices
Figure 24. Accessing the A Registers of
Two Cascaded MC145193 or MC145202–1 Devices
MC145193
22 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
12 7 8 9 151617 232425
R Register Bits of Device #2
in Figure 22 R Register Bits of Device #1
in Figure 22
R15 R14 R8 R7 R0 X X R15
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
31 32 33 39 40
R8 R7 R0
ÇÇÇ
Note 1 Note 2
Figure 25.
ENB
CLK
Din
1. At this point, bits R13, R14 and R15 are stored and sent to the ‘‘OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through
R12 are loaded into the first buffer in the double–buffered section of the R register . Therfore, the R counter divide is not altered yet and
retains the previous ratio loaded. The C and A registers are not affected.
2. Optional load pulse. At this point, the bits R0 through R12 are transfered to the second buffer of the R register. The R counter begins dividing
are not affected. The first buf fer of the R register is not affected. Also, see note of Figure 24 for an alternate method of loading the second
buffer in the R register.
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A registers
Notes Applicable to Each Device:
Figure 25. Accessing the R Registers of Two Cascaded
MC145193 or MC145202–1 Devices
MC145193
23
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
F SUFFIX
PLASTIC PACKAGE
CASE 751J–02
(SO–20)
ISSUE A
OUTLINE DIMENSIONS
–A–
–B–
G
S10 PL
M
0.13 (0.005) BM
D20 PL
M
0.13 (0.005) T A S
BS
L
C
0.10 (0.004) K
J
M
–T– SEATING
PLANE
110
1120
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.12 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A12.55 12.80 0.494 0.504
B5.10 5.40 0.201 0.213
C––– 2.00 ––– 0.079
D0.35 0.45 0.014 0.018
G1.27 BSC 0.050 BSC
J0.18 0.23 0.007 0.009
K0.55 0.85 0.022 0.033
L0.05 0.20 0.002 0.008
M0 7 0 7
S7.40 8.20 0.291 0.323
____
MC145193
24 MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
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MC145193/D
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