SN820X Family Data Sheet Wi-Fi Network Controller Module Revision History Revision 0.1 0.5 0.6 0.7 1.0 1.1 Date 12/09/2012 02/03/2012 02/20/2012 04/20/2012 08/27/2012 01/23/2013 Author Y. Fang Y. Fang N. Nagayama J. Gregus Y. Fang Y. Fang 1.2 1.3 05/30/2013 09/20/2013 R. Willett R Willett Changed specs in Table 1 for Pin 2, 3, 4, and 30 1.4 11/07/13 R. Willett Added Acronyms list; Revised Fig. 1.1, 2.1; revised content and renumbered tables in Chap. 3: added Chapters 4 - 10 and reorganized information; amended regulatory information. 1.5 11/11/13 R Willett Revised Operating Temperature specification on page 6; revised Table 5.1 "Absolute Maximum Ratings," page 38. 2.0 11/25/13 R Willett Removed references to SyChip; updated copyright, deleted Chap 11, "Disclaimer;" 2.1 12/17/13 R. Willett Added text describing module software download in Chapter 1, page 7. 2.2 3.0 02/28/14 07/25/14 R. Willett R. Willett Revised text on page 42, Table 9.2. 3.1 3.2 8/22/14 3/21/16 R. Willett R. Willett Revised Table 5.1 to include VDD, VBAT and VDD_WiFi. 3.3 5/24/17 R. Willett Updated Copyright and version number on page footer. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Change Description Initial version Preliminary version Update performance data and adjusted table format Update CE compliance information Formal release Added Power Rail Current specification and Standby Mode Current specification Separated Data Sheet/User Manual and created new data sheet combining SN8200/8200 UFL and SN8205/8205 UFL Reformatted document to new Murata visual identity; Added Anatel certification, page 39 Deleted minimum values for Receive Sensitivity on Table 4.1.1 page 34, Table 4.2.1 page 35, and Table 4.3.1 page 36; updated Murata address on page 42. www.murata.com This page intentionally left blank. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 2 of 42 www.murata.com Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Model SN820X Module Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Model SN820X Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 7 7 7 2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Top and Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 PCB Footprint (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Typical Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Output Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 I2C Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 I2S SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 12-Bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 DAC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 14 15 17 20 24 31 4 RF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 DC/RF Characteristics for IEEE 802.11b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 DC/RF Characteristics for IEEE 802.11g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 DC/RF Characteristics for IEEE 802.11n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 36 37 5 Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 Packing and Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 Carrier Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 Module Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 RoHS Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Technical Support Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 3 of 42 www.murata.com List of Figures FIGURE 1.1: SN820X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2.1: SN820X and SN820XUFL Top and Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 2.2: Detailed Pad Dimensions (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FIGURE 3.1: SN8200/8200UFL I2C bus AC Waveforms and Measurement Circuit . . . . . . . . . . . . . 18 FIGURE 3.2: SN8205/8205UFL I2C bus AC Waveforms and Measurement Circuit . . . . . . . . . . . . . 19 FIGURE 3.3: SPI Timing Diagram - Slave Mode and CPHA = 0, SN8200/8200UFL and SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FIGURE 3.4: SPI Timing Diagram - Slave Mode and CPHA = 1(1)SPI Timing Diagram - Slave Mode and CPHA = 0, SN8200/8200UFL and SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . 23 FIGURE 3.5: SPI Timing Diagram - Master Mode SN8200/8200UFL and SN8205/8205UFL . . . . . 24 FIGURE 3.6: ADC Accuracy Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 3.7: ADC Accuracy Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 3.8: Typical Connection Diagram Using the ADC, SN8205/8205UFL . . . . . . . . . . . . . . . . 30 FIGURE 7.1 SN820X/820XUFL Carrier Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FIGURE 7.2 Typical SN820X/820XUFL module marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 4 of 42 www.murata.com List of Tables TABLE 1.1: SN820X WiFi Network Controller Module Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TABLE 2.1: Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TABLE 2.2: Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 2.3: Signal Pinouts for SN820X/820XUFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 3.1.1: TABLE 3.2.1: TABLE 3.2.2: TABLE 3.3.1: TABLE 3.3.2: TABLE 3.3.3: TABLE 3.4.1: TABLE 3.4.2: TABLE 3.5.1: TABLE 3.5.2: TABLE 3.5.3: TABLE 3.5.4: TABLE 3.6.1: TABLE 3.6.2: TABLE 3.7.1: TABLE 3.7.2: TABLE 3.7.3: TABLE 3.7.4: TABLE 3.7.5: TABLE 3.7.6: TABLE 3.8.1: TABLE 3.8.2: SN8200/SN8200UFL and SN8205/SN8205 UFL Typical Power Consumption . . . . . Digital I/O Characteristics SN8200/SN8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital I/O Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Characteristics, SN820X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Characteristics, SN8200/SN8200UFL . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Characteristics, SN8205/SN8205UFL . . . . . . . . . . . . . . . . . . . . . . . . I2C Characteristics SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Characteristics SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCL Frequency (fPCLK1= 36 MHz., VDD = 3.3 V)(1)(2) SN8200/8200UFL . . . . . . . SCL Frequency (fPCLK1= 30 MHz., VDD = 3.3 V)(1)(2) SN8205/8205UFL . . . . . . . SPI Characteristics SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Characteristics SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAIN max for fADC = 14 MHz(1), SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . ADC accuracy, SN8200/8200UFL - limited test conditions(1)(2) . . . . . . . . . . . . . . . . ADC Accuracy (1) (2) (3), SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Accuracy, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Characteristics, SN8200/8200UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Characteristic, SN8205/8205UFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 15 15 15 16 17 18 19 20 20 21 23 25 25 26 27 28 30 32 TABLE 4.1.1: RF Characteristics for IEEE 802.11b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TABLE 4.2.1: RF Characteristics for IEEE 802.11g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TABLE 4.3.1: RF Characteristics for IEEE 802.11n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 5.1: Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 5.2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 6.1: Regulatory Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 9.1: SN8200/8200UFL Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 9.2: SN8205/8205UFL Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 5 of 42 www.murata.com 1 Introduction 1.1 Model SN820X Module Family The SN820X Module Family is a portfolio of low power, self-contained, embedded wireless module solutions that address the connectivity demands of M2M applications. These products integrate a micro-controller, a Wi-Fi BB/MAC/RF IC, an RF front end and two clocks into small form factor modules. The module family includes 2 different micro-controller options as shown below. The modules can also be purchased with either a standard on-board chip antenna or a U.FL connector where remote antenna flexibility is required. TABLE 1.1: SN820X WiFi Network Controller Module Family Model # P/N Built-in STM RAM Size Flash Size SN8200 88-00151-00 ARM Cortex M3 96KB 768KB SN8200UFL 88-00151-02 ARM Cortex M3 96KB 768KB SN8205 88-00158-00 ARM Cortex M3 128KB 1024KB SN8205UFL 88-00158-02 ARM Cortex M3 128KB 1024KB 1.2 Model SN820X Module Features * * * * * * * * * * * * * 2.4 GHz IEEE 802.11 b/g/n radio technology Dimensions: 30.5 x 19.4 x 2.8 mm Antenna configurations: On-board antenna or U.FL connector Transmitter power: +18 dBm @80211b Receiver sensitivity: -96 dBm MCU: ARM Cortex-M3 Serial Interface Options: UART, SPI Peripheral Interface Options: ADC, DAC, I2C, I2S, GPIO Operating temperature range: -40 C to +85 C RoHS2 compliant MSL Level 3 FCC/IC certified and CE compliant Compatible with Broadcom WICEDTM SDK Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 6 of 42 www.murata.com 1.3 Block Diagram VBAT VDD VDD_WIFI_IN 16 MHz UART SPI I2C 12S ADC DAC GPIO ARM Cortex M3 for on-board (antenna version) 26 MHz TCXO ANT Wi-Fi SoC (802.11b/g/n SPDT LPF for U.FL (connector version) 32 KHz (optional) WIFI_SLEEP _CLK_IN (optional) FIGURE 1.1: SN820X Block Diagram Murata offers Serial-to-WiFi and EZ Web Wizzard software for SN820x in the SN820x EVK+. The modules are also compatible with Broadcom WICEDTM SDK. The customer can obtain the WICEDTM SDK from Broadcom directly. The modules are delivered with no application firmware pre-installed. Finalize the firmware image, and then download the firmware to the module. For more details, please see reference [4]. 1.4 Acronyms - ADC Analog to Digital Converter DAC Digital to Analog Converter GPIO General-Purpose Input-Output I2C Intelligent Interface Controller I2S Integrated Interchip Sound ISM Industrial, Scientific and Medical MAC Medium Access Control MSL Moisture Sensitivity Level PER Packet Error Rate ROHS Restriction of Hazardous Substances SPI Serial Peripheral Interface UART Universal Asynchronous Receiver-Transmitter 1.5 References [1] STM32F103RF Data Sheet, ST Microelectronics [2] STM32F205RG, Data Sheet, ST Microelectronics [3] SN820X Wi-Fi Network Controller Module Family User Manual, Murata [4] AN_SN8200_002 SN820X Firmware Downloading Application Note, Murata Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 7 of 42 www.murata.com 2 Mechanical Specifications 2.1 Module Dimensions TABLE 2.1: Module Dimensions Parameter Dimensions (LxWxH) Dimension tolerances (LxWxH) Typical Units 30.5 x 19.4 x 2.8 mm 0.2 mm 2.2 Top and Side View SN820X Top and Side View SN820XUFL Top and Side View FIGURE 2.1: SN820X and SN820XUFL Top and Side View Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 8 of 42 www.murata.com 2.3 PCB Footprint (top view) FIGURE 2.2: Detailed Pad Dimensions (top view) Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 9 of 42 www.murata.com 2.4 Pinouts TABLE 2.2: Pinouts Pin # Pin Name I/O 1 GND 2 OSC32_IN I/O Optional precision 32.768 KHz slow clock input. No connect if not used 3 OSC32_OUT I/O No connect 4 WIFI_VDD_EN I/O No connect 5 ADC3 I/O General purpose I/O or ADC3 6 ADC4 I/O General purpose I/O or ADC4 7 ADC5 I/O General purpose I/O or ADC5 8 VDD PI DC supply for MCU and I/O 9 ADC6 I/O General purpose I/O or ADC6 10 DAC2 I/O General purpose I/O or DAC2 11 DAC1 I/O General purpose I/O or DAC1 12 ADC1 I/O General purpose I/O or ADC1 13 Reserved - No connect 14 Reserved - No connect 15 GND - Ground 16 GND - Ground 17 GND - Ground 18 GND - Ground 19 GND - Ground 20 GND - Ground 21 GND - Ground 22 GND - Ground 23 GND - Ground 24 GND - Ground 25 GND - Ground 26 VDD_WIFI_IN 27 Reserved - No connect 28 Reserved - No connect 29 Reserved - No connect 30 WIFI_SLEEP_CLK_IN I Optional precision 32.768 kHz Wi-Fi sleep clock input. Tie to GND if not used 31 GND - Ground 32 UART_TX I/O General purpose I/O or UART_TX 33 UART_RX I/O General purpose I/O or UART_RX 34 UART_CTS I/O General purpose I/O or UART_CTS 35 UART_RTS I/O General purpose I/O or UART_RTS 36 JTMS I/O General purpose I/O or JTMS Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 - Description PI Page 10 of 42 Ground Wi-Fi power supply www.murata.com TABLE 2.2: Pinouts (Continued) 37 JTDI/SPI_NSS Pin # Pin Name I/O General purpose I/O or JTDI or SPI_NSS I/O 38 JTCK 39 Ground 40 JTDO/SPI_SCK I/O General purpose I/O or JTDO or SPI_SCK 41 JTRST/SPI_MISO I/O General purpose I/O or JTRST or SPI_MISO 42 SPI_MOSI I/O General purpose I/O or SPI_MOSI 43 I2C_SCL I/O General purpose I/O or I2C_SCL 44 I2C_SDA I/O General purpose I/O or I2C_SDA 45 BOOT - Normal operation if connected to ground at power up. 46 ADC2 I/O 47 MICRO_RST_N 48 VBAT PI 49 GND - Ground 50 GND - Ground 51 GND - Ground 52 GND - Ground 53 GND - Ground 54 GND - Ground 55 GND - Ground 56 GND - Ground 57 GND - Ground 58 GND - Ground 59 GND - Ground 60 GND - Ground 61 Reserved - No connect 62 GND - Ground Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 I/O Description - I Page 11 of 42 General purpose I/O or JTCK Ground General purpose I/O or ADC2 Module reset Power supply for backup circuitry when VDD is not present www.murata.com TABLE 2.3: Signal Pinouts for SN820X/820XUFL Pin 5 Pin name ADC3 STM32F103RF/STM32F205RG pin PA0/WKUP/ADC123_0/USART2_CTS TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR 6 ADC4 PA1/ADC123_1/USART2_RTS TIM2_CH2 / TIM5_CH2 7 ADC5 PA2/ADC123_2/USART2_TX TIM2_CH3 / TIM5_CH3 / TIM9_CH1 9 ADC6 PA3/ADC123_3/USART2_RX TIM2_CH4 / TIM5_CH4 / TIM9_CH2 10 DAC2 PA4/ADC12_4/DAC1/USART2_CK/SPI1_NSS 11 DAC1 PA5/ADC12_5/DAC2/SPI1_SCK 12 ADC1 PA7/ADC12_7/SPI1_MOSI 32 UART_TX PA9/UART1_TX 33 UART_RX PA10/UART1_RX 34 UART_CTS PA11/UART1_CTS/USB2_DM/CAN_RX 35 UART_RTS PA12/UART1_RTS/USB2_DP/CAN_TX 36 JTMS PA13/JTMS/SWIO 37 JTDI/SPI_NSS PA15/JTDI/SPI3_NSS/I2S3_WS 38 JTCK PA14/JTCK/SWCLK 40 JTDO/SPI_SCK PB3/JTDO/SPI3_SCK/I2S3_CK 41 JTRST/SPI_MISO PB4/JTRST/SPI3_MISO 42 SPI_MOSI PB5/I2C1_SMBA/SPI3_MOSI/ I2S3_SD 43 I2C_SCL PB6/I2C1_SCL TIM4_CH1 44 I2C_SDA PB7/I2C1_SDA TIM4_CH2 46 ADC2 PA6/ADC12_6/SPI1_MISO Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 12 of 42 www.murata.com 3 DC Electrical Specifications The I/O pins from SN820X are based on the built-in STM32 microcontroller. The information shown in sections 3.2 through 3.8 is derived from the ST Microelectronics Data Sheet for user convenience. For original information, see reference [1] and [2] on page of References. 3.1 Typical Power Consumption TABLE 3.1.1: SN8200/SN8200UFL and SN8205/SN8205 UFL Typical Power Consumption Values Item 11b Condition Receive mode Min 11 Mbps Transmit mode (18 dBm/ 100% Duty Cycle) 11g Receive mode 54 Mbps Transmit mode (14.5 dBm/100% Duty Cycle) 11n Receive mode MCS7 Transmit mode (13.5 dBm/ 100% Duty Cycle) Typ Max Units 110 mA 370 mA 110 mA 290 mA 110 mA 280 mA Standby Mode with IEEE802.11 Power Save DTIM 1, Telnet session established and idling 3.15 mA Standby Mode with IEEE802.11 Power Save DTIM 3, Telnet session established and idling 1.28 mA 3.2 GPIO Interface The general purpose I/O (GPIO) pins available on the SN820X will connect to various external devices. GPIOs are configured as input floating by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. They can also be programmed to have internal pull-up or pull-down resistors. The MICRO_RST_N pin is connected to a permanent pull-up resistor, RPU. TABLE 3.2.1: Digital I/O Characteristics SN8200/SN8200UFL SYM min. Input Low Voltage1 VIL Input High Voltage1 typ. max. unit -0.3 0.28 (VDD-2) +0.8 V VIH 0.41 (VDD-2) +1.3 VDD+0.3 V Input Low Voltage2 VIL -0.3 0.32 (VDD2) +0.75 V Input High Voltage2 VIH 0.42 (VDD-2) +1 VDD +0.5 V Input Low Voltage (MICRO_RST_N) VIL -0.5 0.8 V Input High Voltage (MICRO_RST_N) VIH 2 VDD + 0.5 V 0.4 V Output Low Voltage VOL Output High Voltage VOH VDD - 0.4 Weak Pull-up Equivalent Resistor RPU 30 40 50 k Weak Pull-down Equivalent resistor RPD 30 40 50 k V 1 - for pins 5, 6, 7, 9, 10, 11, 12, 42, 46 2 - for pins 32 - 38, 40, 41, 43, 44 Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 13 of 42 www.murata.com TABLE 3.2.2: Digital I/O Characteristics, SN8205/8205UFL SYM min. Voltage1 max. unit VIL -0.3 0.3 VDD V Input High Voltage1 VIH 0.7 VDD 3.6 V Input Low Voltage2 VIL -0.3 0.3 VDD V Input High Voltage2 VIH 0.7 3.6 V Input Low Voltage (MICRO_RST_N) VIL -0.5 0.8 V Input High Voltage (MICRO_RST_N) VIH 2 VDD + 0.5 V Input Low Output Low Voltage VOL Output High Voltage VOH Weak Pull-up Equivalent Resistor R Weak Pull-down Equivalent resistor R typ. 0.4 V VDD - 0.4 PU PD V 30/8* 40/11* 50/15* k 30/8* 40/11* 50/15* k 1 - for pins 5, 6, 7, 9, 10, 11, 12, 42, 46 2 - for pins 32-38, 40, 41, 43, 44 (*) - Pin 33 3.3 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. * In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Table 3.3.1. * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD. TABLE 3.3.1: Voltage Characteristics, SN820X Symbol VDD-VSS Ratings Min Max U External main supply voltage (including VDDA, VDD)(1) -0.3 4.0 Input voltage on five-volt tolerant pin(2) VSS-0.3 VDD+4 VIN Input voltage on any other pin VSS-0.3 4.0 |VDDx| Variations between different VDD power pins - 50 |VSSX - VSS| Variations between all the different ground pins - 50 mV VESD(HBM) Electrostatic discharge voltage (human body model) 2000 V V 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 14 of 42 www.murata.com TABLE 3.3.2: Current Characteristics, SN8200/8200UFL Symbol Ratings Max. IVDD Total current into VDD/VDDA power lines (source)(1) 150 IVSS Total current out of VSS ground lines (sink) 150 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 (1) IIO IINJ(PIN)(2) mA -5/+0 Injected current on five volt tolerant pins(3) 5 Injected current on any other pin (4) IINJ(PIN) Uni 25 Total injected current (sum of all I/O and control pins) (5) TABLE 3.3.3: Current Characteristics, SN8205/8205UFL Symbol Ratings Max. IVDD Total current into VDD power lines (source)(1) 120 IVSS Total current out of VSS ground lines (sink)(1) 120 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IIO Injected current on five-volt tolerant I/O(3) IINJ(PIN) (2) IINJ(PIN)(4) Unit mA -5/+0 Injected current on any other pin(4) 5 Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values) 3.4 Output Voltage Levels Unless otherwise specified, the parameters given in Table 3.4.1 and Table 3.4.2 are derived from tests performed under ambient temperature and VDD supply voltage conditions. All I/Os are CMOS and TTL compliant. TABLE 3.4.1: Output Voltage Characteristics, SN8200/SN8200UFL Symbol VOL (1) Parameter Conditions Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 TTL port(3) IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port(3) IIO=+ 8mA 2.7 V < VDD < 3.6 V Page 15 of 42 Min Max - 0.4 Unit V VDD--0.4 - 0.4 V 2.4 www.murata.com TABLE 3.4.1: Output Voltage Characteristics, SN8200/SN8200UFL (Continued) Symbol Parameter VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time Conditions VOL(2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOL(2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time IIO = +20 mA 2.7 V < VDD < 3.6 V Min Max - 1.3 Unit V VDD--1.3 0.4 IIO= +6 mA 2 V < VDD < 2.7 V V VDD--0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 3.4.1 and the sum of IIO (I/ O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 3.4.1 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 4. Based on characterization data, not tested in production. TABLE 3.4.2: Output Voltage Characteristics, SN8205/SN8205UFL Symbol VOL (2) Parameter Conditions Min Max Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port(3) IIO=+ 8mA 2.7 V < VDD < 3.6 V - 0.4 VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOL(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOL(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time TTL port(3) IIO = +8 mA 2.7 V < VDD < 3.6 V V VDD--0.4 - 0.4 V 2.4 - IIO = +20 mA 2.7 V < VDD < 3.6 V Unit 1.3 V VDD--1.3 0.4 IIO= +6 mA 2 V < VDD < 2.7 V V VDD--0.4 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 3.4.2 and the sum of IIO (I/ O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 3.4.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 16 of 42 www.murata.com 3.5 I2C Interface Characteristics Unless otherwise specified, the parameters given below are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions. The SN8200/8200UFL and SN8205/8205UFL performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins to which SDA and SCL are mapped are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 3.5.1 and Table 3.5.2. TABLE 3.5.1: I2C Characteristics SN8200/8200UFL Standard mode Symbol Parameter M Fast mode I2C(1) Max Min Max Unit tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(3) - 0(4) 900(3) tr(SDA) tr(SCL) - 1000 20 + 0.1Cb 300 SDA and SCL rise time tf(SDA) tf(SCL) - 300 - 300 SDA and SCL fall time th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - s tsu(STO) Stop condition setup time 4.0 - 0.6 - s Stop to Start condition time (bus free) 4.7 - 1.3 - s - 400 - 400 pF tw(STO:STA) Cb Capacitive load for each bus line s ns 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 17 of 42 www.murata.com TABLE 3.5.2: I2C Characteristics SN8205/8205UFL Standard mode Symbol Parameter M Fast mode I2C(1 Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 - 0 900(3) - 1000 20 + 0.1Cb 300 tr(SDA) tr(SCL) SDA and SCL rise time tf(SDA) tf(SCL) th(STA) SDA and SCL fall time Start condition hold time Unit s ns - 300 - 300 4.0 - 0.6 s tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s Stop to Start condition time (bus free) 4.7 - 1.3 - s - 400 - 400 pF tw(STO:STA) Cb Capacitive load for each bus line 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal. FIGURE 3.1: SN8200/8200UFL I2C bus AC Waveforms and Measurement Circuit Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 18 of 42 www.murata.com FIGURE 3.2: SN8205/8205UFL I2C bus AC Waveforms and Measurement Circuit TABLE 3.5.3: SCL Frequency (fPCLK1= 36 MHz., VDD = 3.3 V)(1)(2) SN8200/8200UFL I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 19 of 42 www.murata.com TABLE 3.5.4: SCL Frequency (fPCLK1= 30 MHz., VDD = 3.3 V)(1)(2) SN8205/8205UFL I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. 3.6 I2S SPI Characteristics The I2S interface is multiplexed with SPI and can operate in master or slave mode. Unless otherwise specified, the parameters below for I2S derive from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions. TABLE 3.6.1: SPI Characteristics SN8200/8200UFL Symbol fSCK Parameter SPI clock frequency 1/tc(SCK) Conditions Min Max Uni Master mode - 18 MHz Slave mode - 18 - 8 ns % tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 2tPCLK - Master mode, fPCLK =36MHz, presc = 4 50 60 Master mode 5 - Slave mode 5 - Master mode 5 - tw(SCLH) (1) SCK high and low time t tsu(MI) (1) (1) w(SCLL) tsu(SI)(2) Data input setup time th(MI) (1) th(SI)(1) Data input hold time Slave mode 4 - ta(SO)(1)(3) Data output access Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(1)(2) Data output disable Slave mode 2 10 tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - th(SO)(1) th(MO)(1) Data output hold time ns 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 20 of 42 www.murata.com TABLE 3.6.2: SPI Characteristics SN8205/8205UFL Symbol Parameter fSCK Conditions Min Max SPI1 master/slave mode - 30 SPI2/SPI3 master/slave mode - 15 - 8 ns 30 70 % 1/tc(SCK) SPI clock frequency tr(SCL) tf(SCL) SPI clock rise and fall time Capacitive load: C = 30 pF, fPCLK = 30 MHz SPI slave input clock duty cycle Slave mode DuCy(SCK) tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 2tPCLK - Master mode, fPCLK=3- MHz tPCLK-3 tPCLK+3 presc = 2 Master mode 5 - Slave mode 5 - tw(SCLH)(1) SCK high and low time tsu(MI) (1) Data input setup time Master mode 5 - Data input hold time Slave mode 4 - ta(so)(1)(2) Data output access time Slave mode, fPCLK = 30 MHz 0 3tPCLK tdis(SO)(1)(3) Data output disable time Slave mode 2 th(MI) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - t(MO) (1) Data output hold time MHz ns 10 tv(SO)(1) th(SO)(1) Unit 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 21 of 42 www.murata.com FIGURE 3.3: SPI Timing Diagram - Slave Mode and CPHA = 0, SN8200/8200UFL and SN8205/8205UFL FIGURE 3.4: SPI Timing Diagram - Slave Mode and CPHA = 1(1)SPI Timing Diagram - Slave Mode and CPHA = 0, SN8200/8200UFL and SN8205/8205UFL 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7 VDD. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 22 of 42 www.murata.com FIGURE 3.5: SPI Timing Diagram - Master Mode SN8200/8200UFL and SN8205/8205UFL Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 3.7 12-Bit ADC Characteristics Unless otherwise specified, the parameters given below are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions. NOTE: It is recommended to perform a calibration after each power-up. TABLE 3.7.1: ADC Characteristics, SN8200/8200UFL Symbol Parameter VDDA Conditions Min Typ Max Unit Power supply 2.4 - 3.6 V VREF+ Positive reference voltage 2.4 - VDDA V IVREF Current on the VREF input pin - 160 220(1) A fADC ADC clock frequency 0.6 - 14 MHz fS(2) Sampling rate 0.05 - 1 MHz - - 823 kHz - - 17 1/fADC 0 (VSSA or VREF- - VREF+ V - 50 fADC = 14 MHz fTRIG(2) External trigger frequency VAIN Conversion voltage range(3) tied to ground) See Equation 1 RAIN(2) External input impedance Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 for details Page 23 of 42 - k www.murata.com TABLE 3.7.1: ADC Characteristics, SN8200/8200UFL RADC(2) Sampling switch resistance - - 1 k CADC(2) Internal sample and hold capacitor - - 8 pF tCAL fADC = 14 MHz Calibration time fADC = 14 MHz tlat(2) Injection trigger conversion latency fADC = 14 MHz tlatr(2) Regular trigger conversion latency fADC = 14 MHz tS(2) Sampling time tSTAB(2) Power-up time fADC = 14 MHz tCONV(2) Total conversion time (including sampling time) 1. 2. 3. 4. 5.9 s 83 1/fADC - - 0.214 s - - 3(4) 1/fADC - - 0.143 s - - 2(4) 1/fADC 0.107 - 17.1 s 1.5 - 239.5 1/fADC 0 0 1 s 18 s 1 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC Based on characterization, not tested in production. Guaranteed by design, not tested in production. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified above. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 24 of 42 www.murata.com Equation 1 (SN8200/8200UFL): RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). TABLE 3.7.2: RAIN max for fADC = 14 MHz(1), SN8200/8200UFL Ts (cycles) tS (s) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. TABLE 3.7.3: ADC accuracy, SN8200/8200UFL - limited test conditions(1)(2) Symbol E Parameter Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, 1. 2 1 1.5 VDDA = 3 V to 3.6 V TA = 25 C Measurements made after 0. 1.5 0. 1 0. 1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. 3. Based on characterization, not tested in production. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 25 of 42 www.murata.com TABLE 3.7.4: ADC Accuracy (1) (2) (3), SN8200/8200UFL Symbol Parameter E Total unadjusted error E Offset error E Gain error ED Differential linearity error EL Integral linearity error Test conditions fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after Typ Max(4) 2 5 1. 2.5 1. 3 1 2 1. 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. 4. Preliminary values. FIGURE 3.6: ADC Accuracy Characteristics, SN8200/8200UFL Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 26 of 42 www.murata.com TABLE 3.7.5: ADC Characteristics, SN8205/8205UFL Symbol Parameter VDDA Power supply VREF+ Positive reference voltage Typ Max Unit (1) - 3.6 V 1.8(1) - VDDA V VDDA = 1.8(1) to 2.4 V 0.6 - 15 MHz VDDA = 2.4 to 3.6 V 0.6 - 30 MHz fADC = 30 MHz with 12-bit resolution - - 1764 kHz - - 17 1fADC 0 (VSSA or VREFtied to ground) - VREF+ V - - 50 k Sampling switch resistance 1.5 - 6 k CADC(3) Internal sample and hold capacitor - 4 - pF tlat (3) Injection trigger conversion latency - - 0.100 s - - 3(6) 1/fADC - - 0.067 s - - 2(6) 1/fADC fADC ADC clock frequency fTRIG(3) External trigger frequency VAIN Conversion voltage range(4) RAIN(3) External input impedance Conditions Min 1.8 See Equation 1 for details RADC(3,5) fADC = 30 MHz fADC = 30 MHz tlatr (3) Regular trigger conversion latency 0.100 - 16 s Sampling time fADC = 30 MHz 3 - 480 1/fADC Power-up time - 2 3 s 0.5 - 16.40 s 0.43 - 16.34 s 0.37 - 16.27 s 0.3 - 16.20 s ts(3) tSTAB(3) fADC = 30 MHz tCONV(3) 12-bit resolution Total conversion time (including sampling time) fADC = 30 MHz 10-bit resolution fADC = 30 MHz 8-bit resolution fADC = 30 MHz 6-bit resolution 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 12-bit resolution Single ADC fs(3) Sampling rate (fADC = 30 MHz) Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 1/fADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Page 27 of 42 www.murata.com TABLE 3.7.5: ADC Characteristics, SN8205/8205UFL (Continued) Symbol Parameter Conditions Min Typ Max Unit - 300 500 A - - 16 A - 1.6 1.8 mA - - 60 A fADC = 30 MHz IVREF+(3) ADC VREF DC current consumption in conversion mode 3 sampling time 12bit resolution fADC = 30 MHz 480 sampling time 12-bit resolution fADC = 30 MHz IVDDA(3) ADC VDDA DC current consumption in conversion mode 1. 2. 3. 4. 5, 6. 3 sampling time 12bit resolution fADC = 30 MHz 480 sampling time 12-bit resolution If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 C temperature range. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. Based on characterization, not tested in production. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified above. Equation 1: SN8205/8205UFL RAIN Max Formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. TABLE 3.7.6: ADC Accuracy, SN8205/8205UFL Symbol Parameter ET Total unadjusted error E Offset error E Gain error ED Differential linearity error EL Integral linearity error Test conditions fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 k, VDDA = 1.8(3) to 3.6 V Typ Max(2) 2 5 1. 2.5 1. 3 1 2 1. 3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. 3. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 C temperature range. NOTE: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 28 of 42 www.murata.com FIGURE 3.7: ADC Accuracy Characteristics, SN8205/8205UFL 1. 2. 3. 4. Example of an actual transfer curve. Ideal transfer curve. End point correlation line. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. FIGURE 3.8: Typical Connection Diagram Using the ADC, SN8205/8205UFL Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 29 of 42 www.murata.com 3.8 DAC Electrical Specifications TABLE 3.8.1: DAC Characteristics, SN8200/8200UFL Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.6 V VSSA Ground 0 - 0 V Resistive load vs. VSSA with buffer ON 5 - - k Resistive load vs. VDDA with buffer ON 15 - - k RLOAD(1) RO (1) CLOAD(1) DAC_OUT min(1) DAC_OUT max (1) DAC_OUT min(1) DAC_OUT max(1) IDDVREF+ IDDA DNL(2) Impedance output with buffer OFF Capacitive load - - 15 k - - 50 pF 0.2 - - V Higher DAC_OUT voltage with buffer ON - - VDDA - 0.2 V Lower DAC_OUT voltage with buffer OFF - 0.5 DAC DC current consumption in quiescent mode (Standby mode) DAC DC current consumption in quiescent mode (Standby mode) Differential non linearity VREF+ must always be below VDDA When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. Lower DAC_OUT voltage with buffer ON Higher DAC_OUT voltage with buffer OFF Comments It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V mV It gives the maximum output excursion of the DAC. - VREF+ - 10 mV V - 380 A - 380 A With no load, middle code (0x800) on the inputs - 480 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - With no load, worst code (0x0E4) at VREF+ = 3.6 V in terms of DC consumption on the inputs LSB Difference between two 0.5 Given for the DAC in 10-bit configuration consecutive code-1LSB) INL(2) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 3 LSB Given for the DAC in 12-bit configuration - - 1 LSB Given for the DAC in 10-bit configuration - - 4 LSB Given for the DAC in 12-bit configuration Page 30 of 42 www.murata.com TABLE 3.8.1: DAC Characteristics, SN8200/8200UFL (Continued) Symbol Parameter Min Typ Max Unit Comments (2) Offset error - - 10 mV Given for the DAC in 12-bit configuration - - 3 LSB Given for the DAC in 10-bit at VREF+ VREF+/2) - - 12 LSB Given for the DAC in 12-bit at VREF+ Gain error - - 0.5 % Given for the DAC in 12bit configuration tSETTLING(2) Settling time (full scale: for a 10bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value1LSB - 3 4 s CLOAD 50 pF, RLOAD 5 k Update Max frequency for a correct - - 1 MS/s rate(2) CLOAD 50 pF, RLOAD 5 k DAC_OUT change when - 6.5 10 s CLOAD 50 pF, RLOAD 5 k Offset (difference between measured value at Code (0x800) and the ideal value = = 3.6 V = 3.6 V Gain error (2) small variation in the input code (from code i to i+1LSB) tWAKEUP(2) Wakeup time from off state (Setting the ENx bit in the input code between lowest and highest DAC Control register) PSRR+(1) Power supply rejection ratio - -67 -40 dB No RLOAD, CLOAD = 50 pF (to VDDA) (static DC measurement 1. Guaranteed by design, not tested in production. 2. Preliminary values. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 31 of 42 www.murata.com TABLE 3.8.2: DAC Characteristic, SN8205/8205UFL Symbol Parameter Min Ty M Unit VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VSSA Ground 0 - 0 V RLOAD(2) Resistive load with buffer ON 5 - - k RO(2) Impedance output with buffer OFF - - 15 k Capacitive load - - 50 pF CLOAD(2) DAC_OUT min(2) DAC_OUT (2) max DAC_OUT min(2) DAC_OUT max(2) IVREF+(4) IDDA (4) DNL(4) 0.2 - - V Higher DAC_OUT voltage with buffer ON - - VDDA - 0.2 V Lower DAC_OUT voltage with buffer OFF - 0.5 - mV DAC DC VREF current consumption in quiescent mode (Standby mode) DAC DC VDDA current consumption in quiescent mode(3) When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ - 1LSB - - V - 170 240 - 50 75 280 380 It gives the maximum output excursion of the DAC. With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs A - VREF+ = 1.8 V A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 475 625 A - - 0.5 LSB - - 2 LSB Given for the DAC in 12-bit configuration. - - 1 LSB Given for the DAC in 10-bit configuration. Differential non linearity Difference between two consecutive code-1LSB) INL(4) VREF+ VDDA It gives the maximum output excursion of the DAC. Lower DAC_OUT voltage with buffer ON Higher DAC_OUT voltage with buffer OFF Comments Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Given for the DAC in 10-bit configuration. Given for the DAC in 12-bit configu- Page 32 of 42 www.murata.com TABLE 3.8.2: DAC Characteristic, SN8205/8205UFL (Continued) Symbol Parameter Min Ty M Unit Offset error Offset(4) (difference between - - 10 mV Given for the DAC in 12-bit configuration - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - 0.5 % Given for the DAC in 12-bit configuration measured value at Code (0x800) and the ideal value = VREF+/2) Gain error(4) Gain error Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value 4LSB tSETTLING(4) CLOAD 50 pF, - 3 6 s - - - dB Total Harmonic Distortion THD(4) Buffer ON Update rate (2) RLOAD 5 k CLOAD 50 pF, Max frequency for a correct RLOAD 5 k CLOAD 50 pF, DAC_OUT change when small variation in the input Comments MS/s RLOAD 5 k - - 1 - 6.5 10 s input code between lowest and highest possible ones. - -67 -40 dB No RLOAD, CLOAD = 50 pF code (from code i to i+1LSB) t WAKEUP (4) Wakeup time from off state (Setting the ENx bit in the CLOAD 50 pF, RLOAD 5 k DAC Control register) PSRR+ Power supply rejection ratio (to VDDA) (static DC measurement) 1. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 C temperature range. 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 33 of 42 www.murata.com 4 RF Specifications 4.1 DC/RF Characteristics for IEEE 802.11b Conditions: 25C, VDD_WIFI_IN=3.6 V, VDD= 3.3 V, 11 MBps mode unless otherwise specified. Parameters measured at RF connector. TABLE 4.1.1: RF Characteristics for IEEE 802.11b Parameters Specification Standards conformance IEEE 802.11b Modulation DSSS/CCK Physical layer data rate 1,2,5.5,11 Mbps RF Characteristics Minimum Typical Maximum Unit 2400 -- 2483.5 MHz Carrier frequency error -20 -- +20 ppm Transmit output power 1 16 18 20 dBm 1st side lobes -- -- -30 dBr 2nd side lobes -- -- -50 dBr Power-on and power-down ramp -- -- 2 s RF carrier suppression 15 -- -- dBc Modulation accuracy (EVM) -- -- 35 % 30 MHz to 1 GHz, BW=100 kHz -96 dBm 1 GHz to 12.75 GHz, BW=1 MHz -41 dBm 1.8 GHz to 1.9 GHz, BW=1 MHz -65 dBm 5.15 GHz to5.3 GHz, BW=1 MHz -85 dBm Frequency range Spectrum mask Out-of-band spurious emissions Receive sensitivity 1 1 Mbps, FER 8% -96 -- dBm 11 Mbps, FER 8% -88 -- dBm -- -- dBm Maximum input level, FER 8% -9.5 Adjacent channel rejection, FER 8% 35 dB Notes: 1. Derate by 1.5 dB for temperatures less than -10C or more than +55C in both transmit and receive modes. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 34 of 42 www.murata.com 4.2 DC/RF Characteristics for IEEE 802.11g Conditions: 25C, VDD_WIFI_IN=3.6 V, VDD= 3.3 V, 54 Mbps mode unless otherwise specified. Parameters measured at RF connector. TABLE 4.2.1: RF Characteristics for IEEE 802.11g Parameters Specification Standards conformance IEEE 802.11g Modulation OFDM Data rate 6, 9, 12, 18, 24, 36, 48, 54 Mbps RF Characteristics Minimum Typical Maximum Unit 2400 -- 2483.5 MHz Carrier frequency error -20 -- +20 ppm Transmit output power1 12.5 14.5 16.5 dBm Frequency range Spectrum mask 9 MHz to 11 MHz, 0 dB to -20 dB 0 - dB 11 MHz to 20 MHz, -20 dB to -28 dB 0 - dB 20 MHz to 30 MHz, -28 dB to -40 dB 0 - dB 30 MHz to 33 MHz, -40 dB 0 - dB -25 dB 30 MHz to 1 GHz, BW=100 kHz -96 dBm 1 GHz to 12.75 GHz, BW=1 MHz -41 dBm 1.8 GHz to 1.9 GHz, BW=1 MHz -65 dBm 5.15 GHz to5.3 GHz, BW=1 MHz -85 dBm Constellation Error (EVM) -- -- Out-of-band spurious emissions Received Sensitivity1 6 Mbps, PER 10% -89 -- dBm 54 Mbps, PER 10% -74 -- dBm -- -- dBm Maximum input level, PER 10% -13 Adjacent channel rejection, PER 10% -1 dB Notes: 1. Derate by 1.5 dB for temperatures less than -10C or more than +55C in both transmit and receive modes. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 35 of 42 www.murata.com 4.3 DC/RF Characteristics for IEEE 802.11n Conditions: 25 C, VDD_WIFI_IN=3.6 V, VDD= 3.3 V, 65 Mbps mode unless otherwise specified. Parameters measured at RF connector. TABLE 4.3.1: RF Characteristics for IEEE 802.11n Parameters Specification Standards conformance IEEE 802.11n Modulation OFDM Data rate 6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps RF Characteristics Minimum Typical Maximum Unit 2400 -- 2483.5 MHz Carrier frequency error -20 -- +20 Ppm Transmit Output Power1 11 13 15 dBm Frequency range Spectrum mask 9 MHz to 11 MHz, 0 dB to -20 dB 0 - dB 11 MHz to 20 MHz, -20 dB to -28 dB 0 - dB 20 MHz to 30 MHz, -28 dB to -45 dB 0 - dB 30 MHz to 33 MHz, -45 dB 0 - dB -28 dB 30 MHz to 1 GHz, BW=100 kHz -96 dBm 1 GHz to 12.75 GHz, BW=1 MHz -41 dBm 1.8 GHz to 1.9 GHz, BW=1 MHz -65 dBm 5.15 GHz to 5.3 GHz, BW=1 MHz -85 dBm -- dBm Constellation Error (EVM) -- -- Out-of-band spurious emissions Received Minimum Sensitivity1 65 Mbps, PER 10% -71 Maximum input level, PER 10% -13 dB Adjacent channel rejection, PER 10% -2 dB Notes: 1. Derate by 1.5 dB for temperatures less than -10C or more than +55C in both transmit and receive modes. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 36 of 42 www.murata.com 5 Environmental Specifications 5.1 Absolute Maximum Rating TABLE 5.1: Absolute Maximum Rating Symbol Minimum Maximum Unit Tsop Specification operating temperature Description -30 85 C Top* Operating temperature -40 85 C Tst Storage temperature -40 85 C VDD Power supply 0 4.0 V VBAT Power supply for backup circuitry when VDD is not present. 0 4.0 V 0 4.0 V 0 dBm VDD-WiFi Wi-Fi Power Supply RFin RF input power MSL Moisture Sensitivity Level RoHS2 Restriction of Hazardous Substances 3 Compliant *Note: RF performance may be degraded at extreme temperatures. 5.2 Recommended Operating Conditions TABLE 5.2: Recommended Operating Conditions Minimum (V) Typical (V) Maximum (V) Supply Current Specification (mA) VDD 2.4 3.3 3.6 150 VBAT 2.0 3.3 3.6 10 VDD_WiFi 3.0 3.6 4.0 500 Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 37 of 42 www.murata.com 6 Regulatory Information The table below shows the regulatory compliance status of the SN820X Module family. TABLE 6.1: Regulatory Compliance Regulatory Body Standard Certificate ID FCC CFR Part 15 QPU8200 IC RSS-210 4523A-SN8200 CE ANATEL Compliant Anatel Resolution NO. 506 1322-14-8488 For more information refer to the SN820X Wi-Fi Network Controller Module Family User Manual, reference [3], on page 7. Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 38 of 42 www.murata.com 7 Packing and Marking Information 7.1 Carrier Tape Dimensions FIGURE 7.1 SN820X/820XUFL Carrier Tape Dimensions 7.2 Module Marking Information The following marking information may be printed on a permanent label affixed to the module shield or permanently laser written into the module shield itself. The 2D barcode is used for internal purposes. A pin 1 ID is stamped into the shield. The Model will vary according to the module used - SN8200, SN8200UFL, SN8205, SN8205UFL, however the FCC ID and IC certification numbers apply to all modules in the SN820X Family. FIGURE 7.2 Typical SN820X/820XUFL module marking Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 39 of 42 www.murata.com 8 RoHS Declaration To the best of our present knowledge, given our supplier declarations, this product does not contain substances that are banned by Directive 2002/95/EC or contain a maximum concentration of 0.1% by weight in homogeneous materials for * * * * * Lead and lead compounds Mercury and mercury compounds Chromium (VI) PBB (polybrominated biphenyl) PBDE (polybrominated biphenyl ether) And a maximum concentration of 0.01% by weight in homogeneous materials for * Cadmium and cadmium compounds Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 40 of 42 www.murata.com 9 Ordering Information TABLE 9.1: SN8200/8200UFL Ordering Information RFM Model Number RFM Part Number Standard Order Increment SN8200 Evaluation Kit SN8200 EVK+ 88-00151-95 1 pc SN8200 Module in Tape & Reel SN8200 88-00151-00 400 pcs SN8200UFL Evaluation Kit SN8200UFL EVK+ 88-00151-97 1 pc SN8200UFL Module in Tape & Reel SN8200UFL 88-00151-02 400 pcs Product TABLE 9.2: SN8205/8205UFL Ordering Information Product RFM Model Number RFM Part Number Standard Order Increment SN8205 Evaluation Kit SN8205 EVK+ 88-00158-95 1 pc SN8205 Module in Tape & Reel SN8205 88-00158-00 400 pcs SN8205UFL Evaluation Kit SN8205UFL EVK+ 88-00158-97 1 pc SN8205UFL Module in Tape & Reel SN8205UFL 88-00158-02 400 pcs Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 41 of 42 www.murata.com 10 Technical Support Contact For technical support, please contact tech_sup@murata.com Murata Electronics, N.A., Inc. 4100 Midway Road Carrollton, TX 75007 USA Copyright (c) Murata Manufacturing Co., Ltd. All rights reserved. 2012 SN820X (R) 3.3 5/24/17 Page 42 of 42 www.murata.com