www.ti.com
FEATURES DESCRIPTION
APPLICATIONS
Horizontal Scale = 200 ps
OUTPUTS OPERATING SIMULTANEOUSLY
1.3 Gbps
223 -1 PRBS
VCC = 3.3 V
|VID| = 200 mV, VIC = 1.2 V
Vertical Scale = 400 mV/div
650 MHz
OUTPUT 1
OUTPUT 2
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
2x2 LVPECL CROSSPOINT SWITCH
•High Speed 2x2 LVPECL Crosspoint Switch
The SN65LVCP23 is a 2x2 LVPECL crosspointswitch. The dual channels incorporate wide•LVDS Crosspoint Switch Available in
common-mode (0 V to 4 V) receivers, allowing forSN65LVCP22
the receipt of LVDS, LVPECL, and CML signals. The•50 ps (Typ), of Peak-to-Peak Jitter With
dual outputs are LVPECL drivers to providePRBS = 2
23
– 1 Pattern
high-speed operation. The SN65LVCP23 provides a•Output (Channel-to-Channel) Skew Is 10 ps
single device supporting 2:2 buffering (repeating),(Typ), 50 ps (Max)
1:2 splitting, 2:1 multiplexing, 2x2 switching, andLVDS/CML to LVPECL level translation on each•Configurable as 2:1 Mux, 1:2 Demux,
channel. The flexible operation of the SN65LVCP23Repeater or 1:2 Signal Splitter
provides a single device to support the redundant•Inputs Accept LVDS, LVPECL, and CML
serial bus transmission needs (working andSignals
protection switching cards) of fault-tolerant switchsystems found in optical networking, wireless•Fast Switch Time of 1.7 ns (Typ)
infrastructure, and data communications systems. TI•Fast Propagation Delay of 0.75 ns (Typ)
offers an additional gigabit repeater/translator in the•16 Lead SOIC and TSSOP Packages
SN65LVDS101.•Operating Temperature: –40°C to 85°C
The SN65LVCP23 uses a fully differential data pathto ensure low-noise generation, fast switching times,low pulse width distortion, and low jitter. Output•Gigabit Ethernet Redundant Transmission
channel-to-channel skew is less than 10 ps (typ) andPaths
50 ps (max) to ensure accurate alignment of outputsin all applications. Both SOIC and TSSOP package•Gigabit Interface Converters (GBICs)
options are available.•Fibre Channel Redundant TransmissionPaths
•HDTV Video Routing•Base Stations•Protection Switching for Serial Backplanes•Network Switches/Routers
•Optical Networking Line Cards/Switches•Clock Distribution
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
PACKAGE DISSIPATION RATINGS
THERMAL CHARACTERISTICS
0 1 0 1
OUT 0 OUT 1
EN 0
EN 1
SEL 1
SEL 0
IN 0
IN 1
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE DESIGNATOR PART NUMBER
(1)
SYMBOLIZATION
SOIC SN65LVCP23D LVCP23TSSOP SN65LVCP23PW LVCP23
(1) Add the suffix R for taped and reeled carrier
CIRCUIT T
A
≤25°C DERATING FACTOR
(1)
T
A
= 85°CPACKAGE
BOARD MODEL POWER RATING ABOVE T
A
= 25°C POWER RATING
SOIC (D) High-K
(2)
1361 mW 13.9 mW/°C 544 mWTSSOP (PW) High-K
(2)
1074 mW 10.7 mW/°C 430 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.(2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
PARAMETER TEST CONDITIONS VALUE UNITS
D 15.7 °C/Wθ
JB
Junction-to-board thermal resistance
PW 22.1 °C/WD 26.1 °C/Wθ
JC
Junction-to-case thermal resistance
PW 17.3 °C/WTypical V
CC
= 3.3 V, T
A
= 25°C, 2 Gbps 165 mWP
D
Device power dissipation
Maximum V
CC
= 3.6 V, T
A
= 85°C, 2 Gbps 234 mW
FUNCTIONAL BLOCK DIAGRAM
2
Submit Documentation Feedback
www.ti.com
CIRCUIT FUNCTION TABLE
OUT 0
OUT 1
EN 0
EN 1
IN 0
IN 1
OUT 0
OUT 1
EN 0
EN 1
IN 0
IN 1
OUT 0
OUT 1
EN 0
EN 1
IN 0
IN 1
OUT 0
OUT 1
EN 0
EN 1
IN 0
IN 1
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
INPUTS
(1)
OUTPUTS
(1)
LOGIC DIAGRAMIN 0 IN 1 SEL 0 SEL1 EN 0 EN 1 OUT 0 OUT 1
X X X X L L L L>100 mV X L L H L H L<-100 mV X L L H L L L<-100 mV X L L H H L L>100 mV X L L H H H H>100 mV X L L L H L H<-100 mV X L L L H L L>100 mV X L H H L H L<-100 mV X L H H L L L<-100 mV <-100 mV L H H H L L<-100 mV >100 mV L H H H L H>100 mV <-100 mV L H H H H L>100 mV >100 mV L H H H H HX >100 mV L H L H L HX <-100 mV L H L H L LX >100 mV H H H L H LX <-100 mV H H H L L LX <-100 mV H H H H L LX >100 mV H H H H H HX >100 mV H H L H L HX <-100 mV H H L H L LX >100 mV H L H L H LX <-100 mV H L H L L L<-100 mV <-100 mV H L H H L L<-100 mV >100 mV H L H H H L>100 mV <-100 mV H L H H L H>100 mV >100 mV H L H H H H>100 mV X H L L H L H<-100 mV X H L L H L L
(1) H = High level, L = Low level, Z = High impedance, X = Don't care
3Submit Documentation Feedback
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
IN +
INPUTS VCC
300 kΩ
400 Ω
SEL, EN
7 V 7 V 7 V
IN -
R
R
OUT +
OUT -
VCC
OUTPUTS
VCC
VCC
7 V
7 V
VCC
R
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
4
Submit Documentation Feedback
www.ti.com
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
over operating free-air temperature range unless otherwise noted
(1)
UNITS
Supply voltage range,
(2)
V
CC
–0.5 V to 4 VCMOS/TTL input voltage (ENO, EN1, SEL0, SEL1) –0.5 V to 4 VReceiver input voltage (IN+, IN–) –0.7 V to 4.3 VLVPECL driver output voltage (OUT+, OUT–) –0.5 V to 4 VContinuous 50 mAOutput current
Surge 100 mAStorage temperature range –65°C to 125°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 235°CContinuous power dissipation See Dissipation Rating TableHuman body model
(3)
All pins ±5 kVElectrostatic discharge
Charged-device mode
(4)
All pins ±500 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VReceiver input voltage 0 4 VJunction temperature 125 °CT
A
Operating free-air temperature
(1)
–40 85 °C|V
ID
| Magnitude of differential input voltage 0.1 3 V
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
5Submit Documentation Feedback
www.ti.com
INPUT ELECTRICAL CHARACTERISTICS
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
V
IH
High-level input voltage 2 V
CC
VV
IL
Low-level input voltage GND 0.8 VI
IH
High-level input current V
IN
= 3.6 V or 2.0 V, V
CC
= 3.6 V ±3 ±20 µAI
IL
Low-level input current V
IN
= 0.0 V or 0.8 V, V
CC
= 3.6 V ±1 ±10 µAV
CL
Input clamp voltage I
CL
= –18 mA –0.8 –1.5 V
LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1)
V
OH
Output high voltage V
CC
– 1.3 V
CC
– 0.85
VR
L
= 50 Ωto V
TT
,V
OL
Output low voltage V
CC
– 2.2 V
CC
– 1.65V
TT
= V
CC
– 2.0 V, See Figure 2|V
OD
| Differential output voltage 600 800 1000 mVC
O
Differential output capacitance V
I
= 0.4 sin(4E6 πt) + 0.5 V 3 pF
RECEIVER DC SPECIFICATIONS (IN0, IN1)
V
TH
Positive-going differential input voltage threshold See Figure 1 and Table 1 100 mVNegative-going differential input voltageV
TL
See Figure 1 and Table 1 –100 mVthresholdV
ID(HYS)
Differential input voltage hysteresis 25 mVV
ID
= 100 mV,V
CMR
Common-mode voltage range 0.05 3.95 VV
CC
= 3.0 V to 3.6 VV
IN
= 4 V, V
CC
= 3.6 V or 0.0 V ±1 ±10I
IN
Input current µAV
IN
= 0 V, V
CC
= 3.6 V or 0.0 V ±1 ±10C
IN
Differential input capacitance V
I
= 0.4 sin (4E6 πt) + 0.5 V 1 pF
SUPPLY CURRENT
I
CCD
DC supply current No load 50 65 mA
(1) All typical values are at 25°C and with a 3.3-V supply.
6
Submit Documentation Feedback
www.ti.com
SWITCHING CHARACTERISTICS
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL1
SEL0
IN0+
IN0-
VCC
IN1+
IN1-
VCC
EN0
EN1
OUT0+
OUT0-
GND
OUT1+
OUT1-
GND
D or PW PACKAGE
(TOP VIEW)
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
SET
Input to SEL setup time Figure 5 1 0.5 nst
HOLD
Input to SEL hold time Figure 5 1.1 0.5 nst
SWITCH
SEL to switched output Figure 5 1.7 2.5 nst
PHKL
Disable time, high-level-to-known LOW Figure 4 2 2.5 nst
PKLH
Enable time, known LOW-to-high-level output Figure 4 2 2.5 nst
LHT
Differential output signal rise time (20% – 80%)
(1)
Figure 3 80 110 220 pst
HLT
Differential output signal fall time (20% – 80%)
(1)
Figure 3 80 110 220 psV
ID
= 200 mV, 50% duty cycle, V
CM
= 1.2 V,
15 30 ps650 MHzt
JIT
Added peak-to-peak jitter
V
ID
= 200 mV, PRBS = 2
23
–1 data patternand K28.5 (0011111010), 50 100 psV
CM
= 1.2 V at 1.3 GbpsV
ID
= 200 mV, 50% duty cycle,t
Jrms
Added random jitter (rms) 0.3 0.5 ps
RMSV
CM
= 1.2 V, 650 MHzt
PLHD
Propagation delay time, low-to-high-level output
(1)
V
CC
= 3.3 V, T
A
= 25°C, See Figure 3 400 750 1100 pst
PHLD
Propagation delay time, high-to-low-level output
(1)
V
CC
= 3.3 V, T
A
= 25°C, See Figure 3 400 750 1100 pst
skew
Pulse skew (|t
PLHD
– t
PHLD
|)
(2)
Figure 3 20 100 pst
CCS
Output channel-to-channel skew, splitter mode Figure 3 10 50 psf
MAX
Maximum operating frequency
(3)
1 GHz
(1) Input: V
IC
= 1.2 V, V
ID
= 200 mV, 50% duty cycle, 1 MHz, t
r
/t
f
= 500 ps(2) t
skew
is the magnitude of the time difference between the t
PLHD
and t
PHLD
of any output of a single device.(3) Signal generator conditions: 50% duty cycle, t
r
or t
f
≤100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% V
OD
≥300 mV.
7Submit Documentation Feedback
www.ti.com
PARAMETER MEASUREMENT INFORMATION
IN+
VID VOD
VIN-
VIN+
VOZ
VOY
IIN-
IIN+
IN+ +IN- VIC
2VOUT++VOUT-
2
IN-
OUT +
OUT -
1.4 V
1 V
tPLHD
0.4 V
0 V
VIN+
VIN-
VID
80%
tPHLD
20%
tHLT tLHT
+VOD 0 V
OUT+
OUT-
IN+
IN-
VID 1 pF
VIN-
VIN+
-0.4 V
VOUT-
50 Ω
VOUT+ VOD
-VOD Vdiff = (OUT+) - (OUT-)
50 Ω
VTT
VTT
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
Figure 1. Voltage and Current Definitions
Figure 2. Typical Termination for LVPECL Output Driver
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤0.25 ns, pulse-repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 3. Timing Test Circuit and Waveforms
8
Submit Documentation Feedback
www.ti.com
EN 3 V
1.5 V
0 V
0 V
tPHKL tPKLH
OUT+
OUT-
1 pF VOUT+
VOUT-
1 V or 1.4 V
1.2 V
EN
50 Ω
VTT
50 Ω
VTT
+VOD
-VOD Vdiff = (OUT+) - (OUT-)
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse-repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns, C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
Table 1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL RESULTING COMMON-APPLIED VOLTAGES
INPUT VOLTAGE MODE INPUT VOLTAGE
OUTPUT
(1)
V
IA
V
IB
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V H1.15 V 1.25 V –100 mV 1.2 V L4.0 V 3.9 V 100 mV 3.95 V H3.9 V 4. 0 V –100 mV 3.95 V L0.1 V 0.0 V 100 mV 0.05 V H0.0 V 0.1 V –100 mV 0.05 V L1.7 V 0.7 V 1000 mV 1.2 V H0.7 V 1.7 V –1000 mV 1.2 V L4.0 V 3.0 V 1000 mV 3.5 V H3.0 V 4.0 V –1000 mV 3.5 V L1.0 V 0.0 V 1000 mV 0.5 V H0.0 V 1.0 V –1000 mV 0.5 V L
(1) H = high level, L = low level
9Submit Documentation Feedback
www.ti.com
tSET tHOLD
tSWITCH
tSET tHOLD
tSWITCH
IN0 IN1
IN0
IN1
SEL
OUT
EN
IN1 IN0
IN0
IN1
SEL
OUT
EN
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
NOTE: t
SET
and t
HOLD
times specify that data must be in a stable state before and after mux control switches.
Figure 5. Input to Select for Both Rising and Falling Edge Setup and Hold Times
10
Submit Documentation Feedback
www.ti.com
TYPICAL CHARACTERISTICS
0
20
40
60
80
100
0 500 1000 1500 2000 2500
f − Frequency − MHz
− Supply Current − mAICC
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|VID| = 200 mV
Output = Loaded
600
675
750
825
900
−60 −40 −20 0 20 40 60 80 100
tpd − Propagation Delay Time − ps
TA − Free-Air Temperature − °C
VCC = 3 − 3.6 V,
VIC = 1.2 V,
|VID| = 300 mV
Input = 1 MHz
tPLH
tPHL
0
5
10
15
20
25
30
0 100 200 300 400 500 600 700
f − Frequency − MHz
Peak-to-Peak Jitter − ps
VCC = 3.3 V,
TA = 25°C,
VIC = 400 mV,
Input = Clock
800 mV
500 mV
300 mV
0
15
20
25
30
0 100 200 300 400 500 600 700
10
5
500 mV
300 mV
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
Input = Clock
f − Frequency − MHz
Peak-to-Peak Jitter − ps
800 mV
0
10
20
30
40
50
60
0 200 400 600 800 1000 1200 1400
500 mV
800 mV
Data Rate − Mbps
Peak-to-Peak Jitter − ps
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V
Input = PRBS 223-1
300 mV
0
10
20
30
40
50
60
0 200 400 600 800 1000 1200 1400
VCC = 3.3 V,
TA = 25°C,
VIC = 400 mV,
Input = PRBS 223−1 800 mV
Data Rate − Mbps
Peak-to-Peak Jitter − ps
300 mV
500 mV
0
10
20
30
40
50
60
70
0 200 400 600 800 1000 1200 1400
300 mV
800 mV
500 mV
Data Rate − Mbps
Peak-to-Peak Jitter − ps
VCC = 3.3 V,
TA = 25°C,
VIC = 3.3 V,
Input = PRBS 223−1
0
5
10
15
20
25
30
0 100 200 300 400 500 600 700
f − Frequency − MHz
Peak-to-Peak Jitter − ps
VCC = 3.3 V,
TA = 25°C,
VIC = 3.3 V,
Input = Clock
500 mV
800 mV 500 mV
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
SUPPLY CURRENT PROPAGATION DELAY TIME PEAK-TO-PEAK JITTERvs vs vsFREQUENCY FREE-AIR TEMPERATURE FREQUENCY
Figure 6. Figure 7. Figure 8.
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsDATA RATE FREQUENCY DATA RATE
Figure 9. Figure 10. Figure 11.
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vsFREQUENCY DATA RATE
Figure 12. Figure 13.
11Submit Documentation Feedback
www.ti.com
500
580
660
740
820
900
0 250 500 750 1000 1250 1500 1750 2000
0
10
20
30
40
50
− Differential Output Voltage − mVVOD
f − Frequency − MHz
Period Jitter − ps
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|VID| = 200 mV
Added Random Jitter
20
50
80
110
140
170
200
230
0 500 1000 1500 2000 2500 3000 3500
Data Rate − Mbps
Peak-to-Peak Jitter − ps
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|VID| = 200 mV
Input = PRBS 223−1
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE PEAK-TO-PEAK JITTERvs vsFREQUENCY DATA RATE
Figure 14. Figure 15.
12
Submit Documentation Feedback
www.ti.com
APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
3.3 V or 5 V SN65LVCP23
3.3 V
50 Ω
50 Ω
A
B
50 Ω 50 Ω
VTT
VTT = VCC -2 V
ECL
3.3 V SN65LVCP23
3.3 V
50 Ω
50 Ω
A
B
50 Ω
CML
50 Ω
3.3 V
3.3 V
3.3 V 3.3 V
50 Ω A
B
50 Ω
ECL
VTT VTT = VCC -2 V
1.5 kΩ1.1 kΩ
3.3 V
SN65LVCP23
3.3 V or 5 V 3.3 V
50 Ω
50 Ω
A
B
100 Ω
LVDS
SN65LVCP23
SN65LVCP23
SLLS554E – NOVEMBER 2002 – REVISED MAY 2006
Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Figure 17. Current-Mode Logic (CML)
Figure 18. Single-Ended (LVPECL)
Figure 19. Low-Voltage Differential Signaling (LVDS)
13Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVCP23D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVCP23PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Sep-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVCP23DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVCP23PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVCP23DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVCP23PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated