www.fairchildsemi.com
REV. 1.0.4 5/31/01
Features
• Precision buffered 5V reference (±0.5%)
• Current-input gain modulator reduces external
components and improv es noise immunity
• Programmable ramp compensation circuit
• 1A peak current totem-pole output drive
• Overv oltage comparator helps prev ent output voltage
“runaway”
• Wide common mode range in current sense comparators
for better noise immunity
• Large oscillator amplitude for better noise immunity
Description
The ML4812 is designed to optimally facilitate a peak
current control boost type power factor correction system.
Special care has been taken in the design of the ML4812 to
increase system noise immunity. The circuit includes a
precision reference, gain modulator , error amplifier, ov er-
voltage protection, ramp compensation, as well as a high
current output. In addition, start-up is simplified by an under-
voltage lockout circuit with 6V hysteresis.
In a typical application, the ML4812 functions as a current
mode regulator. The current which is necessary to terminate
the cycle is a product of the sinusoidal line voltage times the
output of the error amplifier which is regulating the output
DC voltage. Ramp compensation is programmable with an
external resistor, to provide stable operation when the duty
cycle exceeds 50%.
Block Diagram
(Pin Configuration Shown is for DIP Version)
5V
OVP
ISENSE
GM OUT
EA OUT
ISINE
RAMP COMP
CT
RT
ERROR
AMP
IEA
OSC 1kΩ
UNDER
VOLTAGE
LOCKOUT
SHDN
OUT
PWR GND
VREF
VCC
GND
CLOCK
VCC
EA–
32V
5
1
2
10
12
11
14
13
15
9
3
4
6
7
16
8
+
–
5V
+
–
5V
+
–
–
5V
S
R
Q
Q
GAIN MODULATOR
ML4812
Power Factor Controller
ML4812 PRODUCT SPECIFICATION
2
REV. 1.0.4 5/31/01
Pin Configuration
Pin Description
Number Name Function
1 I
SENSE
Input from the current sense transformer to the non-inverting input of the PWM
comparator.
2 GM OUT Output of gain modulator. A resistor to ground on this pin converts the current to a
voltage. This pin is clamped to 5V and tied to the inverting input of the PWM comparator.
3 EA OUT Output of error amplifier.
4EA–Inverting input to error amplifier.
5 OVP Input to over voltage comparator.
6 I
SINE
Current gain modulator input.
7 RAMP
COMP Buffered output from the oscillator ramp (C
T
). A resistor to ground sets the current which
is internally subtracted from the product of I
SINE
and I
EA
in the gain modulator.
8R
T
Oscillator timing resistor pin. A 5V source sets a current in the external resistor which is
mirrored to charge C
T
.
9 CLOCK Digital clock output.
10 SHDN A TTL compatible low level on this pin turns off the output.
11 PWR
GND Return for the high current totem pole output.
12 OUT High current totem pole output.
13 V
CC
Positive Supply for the IC.
14 V
REF
Buffered output for the 5V voltage reference.
15 GND Analog signal ground.
16 C
T
Timing capacitor for the oscillator.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ISENSE
GM OUT
EA OUT
EA–
OVP
ISINE
RAMP COMP
RT
CT
GND
VREF
VCC
OUT
PWR GND
SHDN
CLOCK
Top View
ML4812
16-Pin PDIP (P16)
Top View
ML4812
20-Pin PLCC (Q20)
EA OUT
EA–
NC
OVP
ISINE
VREF
VCC
NC
OUT
PWR GND
GM OUT
ISENSE
NC
CT
GND
RAMP COMP
RT
NC
CLOCK
SHDN
4
5
6
7
8
18
17
16
15
14
3212019
910111213
ML4812 PRODUCT SPECIFICATION
3
REV. 1.0.4 5/31/01
Absolute Maximum Ratings
1
Note:
1. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Operating Conditions
Supply Current (I
CC
) 30mA
Output Current Source or Sink (OUT) DC 1.0A
Output Energy (capacitive load per cycle) 5µJ
Gain Modulator I
SINE
Input (I
SINE
) 1.2mA
Error Amp Sink Current (EA OUT) 10mA
Oscillator Charge Current 2mA
Analog Inputs (I
SENSE
, EA–, OVP) –0.3V to 5.5V
Junction Temperature 150°C
Storage Temperature Range –65°C to 150°C
Lead Temperature (soldering 10 sec.) 260°C
Thermal Resistance (
θ
JA
)
20-Pin PLCC
16-Pin PDIP 60°C/W
65°C/W
Temperature Range
ML4812CX 0°C to 70°C
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01
4
Electrical Characteristics
Unless otherwise specified, V
CC
= 15V , R
T
= 14k
Ω
, C
T
= 1000pF, T
A
= Operating Temperature Range (Notes 1, 2).
Parameter Conditions Min. Typ. Max. Units
Oscillator
Initial Accuracy T
J
= 25°C 91 98 105 kHz
Voltage Stability 12V < V
CC
< 18V 0.3 %
Temperature Stability 2 %
Total Variation Line, temperature 90 108 kHz
Ramp Valley to Peak 3.3 V
R
T
Voltage 4.8 5.0 5.2 V
Discharge Current (R
T
open) T
J
= 25°C, V
CT
= 2V 7.8 8.4 9.0 mA
V
CT
= 2V 7.3 8.4 9.3 mA
Clock Out Voltage Low RL = 16k
Ω
0.2 0.5 V
Clock Out Voltage High RL = 16k
Ω
3.0 3.5 V
Reference
Output Voltage T
J
= 25°C, I
O
= 1mA 4.95 5.00 5.05 V
Line Regulation 12V < V
CC
< 25V 2 20 mV
Load Regulation 1mA < IO < 20mA 2 20 mV
Temperature Stability 0.4 %
Total Variation Line, load, temp. 4.9 5.1 V
Output Noise Voltage 10Hz to 10kHz 50 µV
Long Term Stability T
J
= 125°C, 1000 hours 5 25 mV
Short Circuit Current V
REF
= 0V –30 –85 –180 mA
Error Amplifier
Input Offset Voltage ±15 mV
Input Bias Current –0.1 –1.0 µA
Open Loop Gain 1 < V
EA OUT
< 5V 60 75 dB
PSRR 12V < V
CC
< 25V 60 75 dB
Output Sink Current V
EA OUT
= 1.1V, V
EA–
= 6.2V 2 12 mA
Output Source Current V
EA OUT
= 5.0V, V
EA
– = 4.8V –0.5 –1.0 mA
Output High Voltage I
EA OUT
= –0.5mA, V
EA
– = 4.8V 5.3 5.5 V
Output Low Voltage I
EA OUT
= 1mA, V
EA
– = 6.2V 0.5 1.0 V
Unity Gain Bandwidth 1.0 MHz
Gain Modulator
I
SINE
Input Voltage I
SINE
= 500µA 0.4 0.7 0.9 V
Output Current (GM OUT) I
SINE
= 500µA, EA– = V
REF
– 20mV 430 470 510 µA
I
SINE
= 500µA, EA– = V
REF
+ 20mV 3 10 µA
I
SINE
= 1mA, EA– = V
REF
– 20mV 860 940 1020 µA
I
SINE
= 500µA, EA– = V
REF
– 20mV,
I
RAMP COMP
= 50µA 455 µA
Bandwidth 200 kHz
PSRR 12V < V
CC
< 25V 70 dB
ML4812 PRODUCT SPECIFICATION
5
REV. 1.0.4 5/31/01
Notes:
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. V
CC
is raised above the Startup Threshold first to activate the IC, then returned to 15V.
OVP Comparator
Input Offset Voltage Output Off –25 +5 mV
Hysteresis Output On 95 105 115 mV
Input Bias Current –0.3 –3µA
Propagation Delay 150 ns
PWM Comparator: I
SENSE
Input Offset Voltage ±15 mV
Input Offset Current ±1 µA
Input Common Mode Range –0.2 5.5 V
Input Bias Current –2–10 µA
Propagation Delay 150 ns
I
LIMIT
Trip Point V
GM OUT
= 5.5V 4.8 5 5.2 V
Output
Output Voltage Low I
OUT
= –20mA 0.1 0.4 V
I
OUT
= –200mA 1.6 2.2 V
Output Voltage High I
OUT
= 20mA 13 13.5 V
I
OUT
= 200mA 12 13.4 V
Output Voltage Low in UVLO I
OUT
= –5mA, V
CC
= 8V 0.1 0.8 V
Output Rise/Fall Time C
L
= 1000pF 50 ns
Shutdown V
IH
2.0 V
V
IL
0.8 V
I
IL
, V
SHDN
= 0V –1.5 mA
IIH, V
SHDN
= 5V 10 µA
Under-Voltage Lockout
Startup Threshold 15 16 17 V
Shutdown Threshold 9 10 11 V
V
REF
Good Threshold 4.4 V
Supply
Supply Current Start-Up, V
CC
= 14V, T
J
= 25°C 0.8 1.2 mA
Operating, T
J
= 25°C2025mA
Internal Shunt Zener Voltage I
CC
= 30mA 25 30 34 V
Electrical Characteristics
(Continued)
Unless otherwise specified, V
CC
= 15V , R
T
= 14k
Ω
, C
T
= 1000pF, T
A
= Operating Temperature Range (Notes 1, 2).
Parameter Conditions Min. Typ. Max. Units
ML4812 PRODUCT SPECIFICATION
6
REV. 1.0.4 5/31/01
Functional Description
Oscillator
The ML4812 oscillator charges the external capacitor (CT)
with a current (ISET) equal to 5/RSET. When the capacitor
voltage reaches the upper threshold, the comparator changes
state and the capacitor discharges to the lower threshold
through Q1. While the capacitor is discharging, Q2 provides
a high pulse.
The Oscillator period can be described by the following
relationship:
where:
and:
TOSC TRAMP TDEADTIME
+=
VOUT VIN
1D
ON
–
--------------------=
TDEADTIME CTVRAMPVALLEYTOPEAK
×8.4mA ISET
–
-------------------------------------------------------------------------=
Figure 1. Oscillator Block Diagram
Figure 2. Oscillator Timing Resistance vs. Frequency
Figure 3. Output Saturation Voltage vs. Output Current
10SYNC Q2
Q1
9RT
16CT
EXTERNAL
CLOCK
+
-
5.6V
ISET
8.4mA
CT
RT
ISET
CSYNC
RSYNC
CLOCK
tD
RAMP V ALLEY
RAMP PEAK
V(CT)
10
RT (kΩ)
OSCILLATOR FREQUENCY (kHz)
10 100 1000
8
5
3
2
1
MAXIMUM DUTY CYCLE (%)
10nF
20nF
5nF 2nF
1nF 85%
80%
70%
90%
15
14
13
3
2
1
0
OUTPUT SATURATION VOLTAGE (V)
OUTPUT CURRENT (mA)
0 200 400 800
600
VCC VCC = 15V
80µs PULSED LOAD
120Hz RATE
GND
SOURCE SATURATION
LOAD T O GROUND
SINK SATURATION
LOAD T O VCC
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01 7
5V
EA–
4
3
–
+
8V
0.5mA
EA OUT
AVOL, OPEN LOOP GAIN (dB)
FREQUENCY (Hz)
10 1k 1M
100 10k 10M100k
100
80
60
40
20
0
-20
EXCESS PHASE (degrees)
0
-30
-60
-90
-120
-150
-180
GAIN
PHASE
6
2
7
16 CT
RAMP COMP
GM OUT
ISINE
ERROR CURRENT
9V
5V
IRAMP COMP
ISINE × ERROR CURRENT
– IRAMP COMP/2
500
400
300
200
100
0
MULTIPLE OUTPUT CURRENT (µA)
ERROR AMP OUTPUT VOLTAGE (V)
SINE INPUT CURRENT (µA)
0 200 300 500400100
4.5
4.0
3.5
3.0
2.5
2.0
1.5
Output Driver Stage
The ML4812 output driver is a 1A peak output high speed
totem pole circuit designed to quickly dri v e capaciti v e loads,
such as power MOSFET gates. (Figure 3)
Error Amplifier
The ML4812 error amplifier is a high open loop gain, wide
bandwidth, amplifier.(Figures 4-5)
Gain Modulator
The ML4812 gain modulator is of the current-input type to
provide high immunity to the disturbances caused by high
power switching. The rectified line input sine wa v e is con-
verted to a current via a dropping resistor. In this way, small
amounts of ground noise produce an insignificant effect on
the reference to the PWM comparator. The output of the gain
modulator is a current of the form: IOUT is proportional to
ISINE ↔ IEA, where ISINE is the current in the dropping
resistor, and IEA is a current proportional to the output of the
error amplifier. When the error amplifier is saturated high,
the output of the gain modulator is approximately equal to
the ISINE input current. The gain modulator output current is
con v erted into the reference voltage for the PWM compara-
tor through a resistor to ground on the gain modulator out-
put. The gain modulator output is clamped to 5V to provide
current limiting.
Ramp compensation is accomplished by subtracting 1/2 of
the current flowing out of RAMP COMP through a buffer
transistor driven by CT which is set by an external resistor.
Under V oltage Lockout
On power-up the ML4812 remains in the UVLO condition;
output low and quiescent current low. The IC becomes oper-
ational when VCC reaches 16V. When VCC drops below
10V, the UVLO condition is imposed. During the UVLO
condition, the 5V VREF pin is “off”, making it usable as a
“flag” for starting up a downstream PWM conv erter.
Figure 4. Error Amplifier Configuration
Figure 5. Error Amplifier Open-Loop Gain and
Figure 6. Gain Modulator Block Diagram
Figure 7. Gain Modulator Linearity
Phase vs Frequency
ML4812 PRODUCT SPECIFICATION
8REV. 1.0.4 5/31/01
Typical Applications
Input Inductor (L1) Selection
The central component in the regulator is the input boost
inductor. The value of this inductor controls v arious critical
operational aspects of the regulator. If the value is too low,
the input current distortion will be high and will result in low
power factor and increased noise at the input. This will
require more input filtering. In addition, when the value of
the inductor is low the inductor dries out (runs out of current)
at low currents. Thus the power factor will decrease at lower
power le v els and/or higher line voltages. If the inductor
value is too high, then for a giv en operating current the
required size of the inductor core will be large and/or the
required number of turns will be high. So a balance must be
reached between distortion and core size.
One more condition where the inductor can dry out is ana-
lyzed below where it is shown to be maximum duty cycle
dependent.
For the boost con v erter at steady state:
Where DON is the duty cycle [TON/(TON + TOFF)]. The
input boost inductor will dry out when the following condi-
tion is satisfied:
or
VINDRY: voltage where the inductor dries out.
VOUT: output DC voltage.
Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver during
the OFF time. The net result is that the inductor dries out.
Figure 8. Under-Voltage Lockout Block Diagram
Figure 9a. Total Supply Current vs. Supply Voltage
Figure 9b. Supply Current (ICC) vs. Temperature
Figure 10. Reference Load Regulation
VOUT VIN
1D
ON
–
--------------------=(1)
VIN t() VOUT
<1D
ON
–()×(2)
VINDRY 1D
ON max()–[]=V
OUT
×(3)
ENABLE
VREF
VREF
GEN.
9V
INTERNAL
BIAS
5V VREF
VCC
–
+
ICC (mA)
VCC (V)
03020 4010
25
20
15
10
5
0
25
20
15
10
5
0
SUPPLY CURRENT (mA)
TEMPERATURE (degrees)
–60 20 60 140100–20
–40 40 80 1200
OPERATING CURRENT
STARTUP
∆VREF (mV)
IREF (mA)
0 40 100
20 60 12080
0
-4
-8
-12
-16
-20
-24
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01 9
The recommended maximum duty cycle is 95% at 100KHz
to allow time for the input inductor to dump its energy to
the output capacitors. For example, if: VOUT = 380V and
DON (max) = 0.95, then substituting in (3) yields VINDRY
= 20V. The effect of drying out is an increase in distortion at
low voltages.
For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
wa v eform, i.e. as the input v oltage sweeps from zero v olts to
a maximum value equal to its peak so does the current.
The load of the power factor regulator is usually a switching
power supply which is essentially a constant power load. As
a result, an increase in the input voltage will be offset by a
decrease in the input current.
By combining the ideas set forth abov e, some ground rules
can be obtained for the selection and design of the input
inductor:
Step 1: Find minimum operating current.
then:
Step 2: Choose a minimum current at which point the
inductor current will be on the ver ge of drying out. For this
example 40% of the peak current found in step 1 was chosen.
then:
Step 3: The value of the inductance can no w be found using
previously calculated data.
The inductor can be allowed to decrease in value when the
current sweeps from minimum to maximum value. This
allows the use of smaller core sizes. The only requirement is
that the ramp compensation must be adequate for the lower
inductance value of the core so that there is adequate com-
pensation at high current.
Step 4: The presence of the ramp compensation will change
the dry out point, but the value found above can be consid-
ered a good starting point. Based on the amount of power
factor correction the above value of L1 can be optimized
after a few iterations.
Gapped Ferrites, Molypermalloy, and Powdered Iron cores
are typical choices for core material. The core material
selected should hav e a high saturation point and acceptable
losses at the operating frequency.
One ferrite core that is suitable at around 200W is the
#4119PL00-3C8 made by Philips Components (Ferroxcube).
This ungapped core will require a total gap of 0.180" for this
application.
Oscillator Component Selection
The oscillator timing components can be calculated by using
the following expression:
For example:
Step 1: At 100kHz with 95% duty cycle TOFF = 500ns
calculate CT using the following formula:
Step 2: Calculate the required v alue of the timing resistor.
Current Sense and Slope (Ramp)
Compensation Component Selection
Slope compensation in the ML4812 is provided internally.
Rather than adding slope to the nonin v erting input of the
PWM comparator, it is actually subtracted from the voltage
present at the inv erting input of the PWM comparator . The
amount of slope compensation should be at least 50% of the
downslope of the inductor current during the off time, as
reflected to the in v erting input of the PWM comparator. Note
that slope compensation is required only when the inductor
current is continuous and the duty cycle is more than 50%.
The downslope of the inductor current at the ver ge of
discontinuity can be found using the expression gi v en below:
The downslope as reflected to the input of the PWM
comparator is giv en by:
IIN min()
PEAK 1.414 PIN
×min()
VIN max()
-------------------------------------------=
PIN min()50W=
VIN max()260V=
(4)
IIN min()
PEAK 0.272A=
ILDRY 100mA=
L1 VINDRY DON max()×
ILDRY fOSC
×
-------------------------------------------------------20V 0.95×
100mA 100KHz×
---------------------------------------------- 2mH===
(5)
fOSC 1.36
RTCT
×
--------------------= (6)
CTTOFF IDIS
×
VOSC
----------------------------- 1000 p F== (7)
(8)
RT1.36
fOSC CT
×
------------------------- 1.36
100KHz 100pF×
------------------------------------------- 13.6kΩ== =
choose RT = 14kΩ
diL
dt
--------VOUT VINDRY
–
L
----------------------------------------- 380V 20V–
2mH
------------------------------ 0.18A µs⁄===
(9)
SPWM VOUT VINDRY
–
L
----------------------------------------- RS
NC
-------== (10)
SPWM 380V 20V–
2mH
------------------------------= 100
80
---------
×0.225V µs⁄=
ML4812 PRODUCT SPECIFICATION
10 REV. 1.0.4 5/31/01
Where RS is the current sense resistor and NC is the turns
ratio of the current transformer (T1) used. In general, current
transformers simplify the sensing of switch currents (espe-
cially at high power levels where the use of sense resistors is
complicated by the amount of power they hav e to dissipate).
Normally the primary side of the transformer consists of a
single turn and the secondary consists of several turns of
either enameled magnet wire or insulated wire. The diameter
of the ferrite core used in this example is 0.5" (SPANG/Mag-
netics F41206-TC). The rectifying diode at the output of the
current transformer can be a 1N4148 for secondary currents
up to 75mA average.
Sense FETs or resistive sensing can also be used to sense the
switch current. The sensed signal has to be amplified to the
proper level before it is applied to the ML4812.
The v alue of the ramp compensation (SCPWM) as seen at the
in v erting terminal of the PWM comparator is:
The required value for RSC can therefore be found by equat-
ing: SCPWM = ASC x SPWM, where ASC is the amount of
slope compensation and solving for RSC. The value of
GM OUT depends on the selection of RAMP COMP.
The peak of the inductor current can be found approximately
by:
Selection of NC which depends on the maximum switch
current, assume 4A for this example is 80 turns.
Where RS is the sense resistor, and VCLAMP is the current
clamp at the inv erting input of the PWM comparator . This
clamp is internally set to 5V. In actual application it is a good
idea to assume a value less than 5V to avoid unwanted cur-
rent limiting action due to component tolerances. In this
application, VCLAMP was chosen as 4.9V.
Having calculated RS, the value SPWM and of RSC can now
be calculated:
The following values were used in the calculation:
RM = 28.8kΩASC = 0.7
RT = 14kΩCT = 1nF
Voltage Regulation Components
The values of the voltage regulation loop components are
calculated based on the operating output voltage. Note that
voltage safety regulations require the use of sense resistors
that ha v e adequate v oltage rating. As a rule of thumb if 1/4W
resistors are chosen, two of them should be used in series.
The input bias current of the error amplifier is approximately
0.5µA, therefore the current av ailable from the v oltage sense
resistors should be significantly higher than this value. Since
two 1/4W resistors hav e to be used the total power rating is
1/2W. The operating power is set to be 0.4W then with 380V
output voltage the value can be calculated as follows:
Choose two 178kΩ, 1% connected in series. Then R2 can be
calculated using the formula below:
Choose 4.75kΩ, 1%. One more critical component in the
voltage re gulation loop is the feedback capacitor for the error
amplifier. The voltage loop bandwidth should be set such
that it rejects the 120Hz ripple which is present at the output.
If this ripple is not adequately attenuated it will cause distor-
tion on the input current wav eform. Typical bandwidths
range anywhere from a few Hertz to 15Hz. The main com-
promise is between transient response and distortion. The
feedback capacitor can be calculated using the following
formula:
SCPWM 2.5 RM
×
RTCT
×R×SC
-------------------------------------= (11)
RPVIN max()
PEAK
ISINE PEAK()
--------------------------------------- 260 1.414×
0.5mA
---------------------------- 750 k Ω===
(12)
RMVCLAMP RP
×
VIN PEAK()
-----------------------------------4.9 750kΩ×
90 1.414×
------------------------------- 28.8kΩ===
(13)
ILPEAK 1.414 PPOUT
×
VIN RMS()
------------------------------------ 1.414 200×
90
---------------------------- 3.14A===
(14)
RSVCLAMP NC
×
ILPEAK
------------------------------------4.9 80×
4
------------------- 1 0 0 Ω=== (15)
RSC 2.5 RM
×
ASC SPWM RTCT
×××
-----------------------------------------------------------=
RSC 2.5 28.8kΩ×
0.7 0.225 106
×()14K 1nF×××
--------------------------------------------------------------------------------33kΩ==
(16)
R1380V()
20.4W⁄360kΩ== (17)
R2VREF R1
×
VOUT VREF
–
---------------------------------- 5V 356kΩ×
380V 5V–
------------------------------- 4.747kΩ===(18)
CF1
3.142 R1BW××
------------------------------------------=
CF1
3.142 356kΩ2Hz××
------------------------------------------------------ 0.44µF==
(19)
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01 11
Overvoltage Protection (OVP) Components
The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to a
lev el where the power components are safe to operate. Ten to
fifteen volts above VOUT is generally a good setpoint. This
sets the maximum transient output v oltage to about 395V. By
choosing the high v oltage side resistor of the OVP circuit the
same way as abov e i.e. R4 = 356K then R5 can be calculated
as:
Choose 4.53kΩ, 1%. Note that R1, R2, R4 and R5 should be
tight tolerance resistors such as 1% or better.
Controller Shutdown
The ML4812 provides a shutdown pin which could be used
to shutdown the IC. Care should be taken when this pin is
used because power supply sequencing problems could arise
if another regulator with its own bootstrapping follows the
ML4812. In such a case a special circuit should be used to
allow for orderly start up. One way to accomplish this is by
using the reference voltage of the ML4812 to inhibit the
other controller IC or to shut down its bias supply current.
Off-line Start-up and Bias Supply Generation
The ML4812 can be started using a “bleed resistor” from the
high voltage bus. After the voltage on VCC exceeds 16V, the
IC starts up. The energy stored on the 330µF, C15, capacitor
supplies the IC with running power until the supplemental
winding on L1 can provide the power to sustain operation.
The values of the start-up resistor R10 and capacitor C15
may need to be optimized depending on the application. The
charging wa v eform for the secondary winding of L1 is an
in v erted chopped sinusoid which reaches its peak when the
line voltage is at its minimum. In this example, C9 = 0.1µF,
C15 = 330µF, D8 = 1N4148, R10 = 39kΩ, 2W.
Enhancement Circuit
The power factor enhancement circuit shown in Figure 12 is
described in detail in Application Note 11. It improves the
power factor and lowers the input current harmonics. Note
that the circuit meets IEC 1000-3-2 specifications (with the
enhancement) on the harmonics by a large margin while cor-
recting the input power factor to better than 0.99 under most
steady state operating conditions.
Construction and Layout Tips
High frequency power circuits require special care during
breadboard construction and layout. Double sided printed
circuit boards with ground plane on one side are highly rec-
ommended. All critical switching leads (power FET, output
diode, IC output and ground leads, bypass capacitors) should
be kept as small as possible. This is to minimize both the
transmission and pick-up of switching noise.
There are two kinds of noise coupling; inductiv e and capaci-
tiv e. As the name implies inductiv e coupling is due to fast
changing (high di/dt) circulating switching currents. The
main source is the loop formed by Q1, D5, and C3–C4.
Therefore this loop should be as small as possible, and the
abov e capacitors should be good high frequency types.
The second form of noise coupling is due to fast changing
voltages (high dv/dt). The main source in this case is the
drain of the power FET. The radiated noise in this case can
be minimized by insulating the drain of the FET from the
heatsink and then tying the heatsink to the source of the FET
with a high frequency capacitor (CH in Figure 12).
The IC has two ground pins named PWR GND and Signal
GND. These two pins should be connected together with a
very short lead at the printed circuit board exit point. In
general grounding is very important and ground loops should
be avoided. Star grounding or ground plane techniques are
preferred.
Magnetics Tips
L1 — Main Inductor
As shown in Table 1, one of several toroidal cores can be
used for L1. The T184-40 core above is the most economi-
cal, but has lower inductance at high current. This would
yield higher ripple current and require more line EMI filter-
ing. The value for RSC (slope compensation resistor on
RAMP COMP) was calculated for the T225-8/90 and should
be recalculated for other inductor characteristics. The vari-
ous core manufacturers hav e a range of applications litera-
ture a v ailable. A gapped ferrite core can also be used in place
of the powdered iron core. One such core is a Philips Com-
ponents (Ferroxcube) core #4229PL00-3C8. This is an
ungapped core. Using 145 turns of #24 AWG wire, a total air
gap of 0.180" is required to give a total inductance of about
2mH. Since 1/2 of the gap will be on the outside of the core
and 1/2 the gap on the inside, putting a 0.09" spacer in the
center will yield a 0.180" total gap. To prev ent leakage fields
R5VREF R4
×
VOVP VREF
–
---------------------------------- 5V 356kΩ×
395V 5V–
------------------------------- 4.564kΩ=== (20)
Table 1. Toroidal Cores (L1)
Material Manufacturer Part # Turns (#24AWG)
Powdered Iron Micrometals T225-8/90 200
Powdered Iron Micrometals T184-40 120
Molypermalloy SPANG (Mag. Inc.) 58076-A2 (high flux) 180
ML4812 PRODUCT SPECIFICATION
12 REV. 1.0.4 5/31/01
from generating RFI, a shorted turn of copper tape should be
wrapped around the gap as shown in Figure 11. For produc-
tion, a gapped center leg can be ordered from most core ven-
dors, eliminating the need for the external shorted copper
turn when using a potentiometer core.
Figure 11. Copper Foil Shorted Turn
T1 — Sense Transformer
In addition to the core type mentioned in the parts list, the
following Siemens cores should be suitable for substitution
and may be more readily av ailable in Europe.
The N27 material is for high frequency and will work better
abov e 100KHz but both are adequate. In addition, Philips
Components (Ferroxcube) core 768T188-3C8 can be used.
Please also refer to the list of core vendors below
SPANG/Magnetics Inc. 1 (800) 245-3984, or (412) 282-8282
Micrometals 1 (800) 356-5977
Philips Components (914) 247-2064
COPPER FOIL
SHORTED TURN
0.09" GAP
Material Size Code Part #
N27 R16/6.3 B64290-K45-X27
N30 R16/6.3 B64290-K45-X830
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01 13
Figure 12. Typical Application 200W Power Factor Correction Circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
90 TO
260 VAC AC IN
P1
FUSE F1
5A 250V
L
N
C1
1µF
630V
D1
1N5406
D2
1N5406
D3
1N5406
RGMOUT
27kΩ
D10
1N5406
OPTIONAL
ENHANCEMENT
CKT.
R12
1K
C17
Q3C19
+
D13
D12
D11
R3
22kΩCF
D4
1N5406
R2A
10kΩ
R2B
3.9kΩR5B
3.9kΩ
R5A
10kΩ
R1B
180kΩR4B
180kΩRPB
150kΩ
RPA
360kΩ
R4A
180kΩ
12
NP
NS
R10
39kΩ
2W
RSC
33kΩ
RT
7.5kΩ
ML4812
IC1
C16
100µF
25V
+
D9D8
Q2
KA7815
CT 2nF
C15 P3*
C10
1µF
330µF
25V VCC
D5 MUR860
OFF-LINE START-UP
AND BIAS SUPPLY
C18
R11
33kΩC11
1nF
D6T1
A
B
RS
100
C9
0.1µFC8
0.1µF
RG
10
+
–
Q1
FQP9N50 HEATSINK
CH
6.8nF
R7
150kΩ
1W
R6
150kΩ
1W
C3
6.8nF
1kV
C4
1µF
630V
C5
680µF
200V
C6
680µF
200V
P2
VOUT 380 VDC
** SEE NOTES BELOW
NOTES:
1. ALL UNSPECIFIED DIODES ARE 1N4148.
2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT.
3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V.
4. ADJUST R2A AND R5A WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS.
Q3 = PN2222
P3 IS USED AT INITAL TURN-ON TO
CHECK THE IC FOR PROPER OPERATION.
APPLY ≈ 16VDC.
FIXED RESISTORS CAN BE USED FOR THE SENSING
COMPONENTS. BELOW ARE 1% STANDARD
RESISTORS THAT WILL FORCE THE CORRECT
OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178kΩ 1%,
R2B = 4.75 1%, R5B = 4.53kΩ 1%.
USE JUMPERS INSTEAD OF R2A AND R5A (POTS).
FOR HIGHER POWER USE MORE VCC DECOUPLING.
2µF OR MORE BE REQUIRED AT 1KW LEVELS.
*
**
***
R13
22kΩ
R1A
180kΩ
L1
***
+
–
+
ML4812 PRODUCT SPECIFICATION
14 REV. 1.0.4 5/31/01
Table 2. Component Values/Bill of Materials for Figure 12
Note:
1. All resistors 1/4W unless otherwise specified. Some reference designators are skipped (e.g. C2, C12, etc.) and do not appear
on the schematic. These designators were used in previous revisions of the board and are not used on this revision.
Additional information on key components is included in the attached appendix.
Reference Description
C1, C4 1µF, 630V Film (250VAC)
C3, CH6.8nF, 1KV Ceramic disk
C5, C6 680µF, 200V Electrolytic
C8, C9 0.1µF, 50V Ceramic
C10, C19 1µF, 50V Ceramic
C11 0.001µF, 50V Ceramic
C15 330µF, 25V Electrolytic
C16 100µF, 25V Electrolytic
C17 10µF, 25V Electrolytic
CF0.47µF, 50V Ceramic
CT0.002µF, 50V Ceramic
D1, D2, D3, D4, D10 1N5406 (Fairchild)
D5 MUR860 (Fairchild)
D6, D8, D9, D11, D12, D13 1N4148 (Fairchild)
F1 5A, 250V 3AG with clips
IC1 ML4812CP (Fairchild)
L1 2mH, 4A IPEAK (see note)
Q1 FQP9N50 (Fairchild)
Q2 KA7815 (Fairchild)
Q3 PN2222 (Fairchild)
R1A, R1B, R4A, R4B 180kΩ
R2A, R5A 10kΩ TRIMPOT BOURNS 3299 or equivalent
R2B, R5B 3.9kΩ
R3, R13 22kΩ
R6, R7, RPB 150kΩ
R10 39kΩ, 2W
R11 33kΩ
R12 1kΩ
RG 10Ω
RM 27kΩ
RPA, R15 360kΩ
RS 100kΩ
RSC 33kΩ
RT 7.5kΩ
T1 SPANG F41206-TC NS = 80, NP = 1 (see note)
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01 15
Figure 13. 1kW Input Power, Power Factor Correction Circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
C12
1µF
630V
C10
680µF
250V
C11
680µF
250V
GND
VOUT
C9
15µF
630V
C8
15µF
630V
D5 FFPF30U60S
R4
150K
1W
R5
150K
1W
–
FQA24N50
GND
1T
Q2
FQA24N50
Q1
T1
D4
80T
C14
1µF
***
RG1
3
RG2
3
C7
0.1µF
C4
0.1µF
RS
22Ω
C5
1nF
VCC
CT 2.2nF
R3
33K
R722K
IC1
ML4812
RT
6.2K
RSC
51K
L1
566µH
RPA
360K
RPB
150K
R4A
360K
R4B
180K
R1B
180K
R1A
180K
CF
R5A
5K
R5B
3K
R2B
3K
R2A
5K
RM
27K
D1
1N5406
BRIDGE
RECTIFIER
C3
1µF
500V
C2
1µF
500V
C1
1µF
500V
FUSE F1
15A 250V
L
AC
IN
N
R1 R2
330K 22K R6 C13
10µF
GND
VCC
Q3
D2
VZ
3.5V
+
ENHANCEMENT CIRCUIT SEE TEXT PN2222
**
C6
1µF
NOTES:
1. ALL UNSPECIFIED DIODES ARE 1N4148.
2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT.
3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V.
4. ADJUST R
2A
AND R
5A
WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS.
Q
3
= PN2222
AT INITIAL TURN-ON TO CHECK
THE IC FOR PROPER OPERATION,
APPLY ≈ 16VDC.
FIXED RESISTORS CAN BE USED FOR THE SENSING
COMPONENTS. BELOW ARE 1% STANDARD
RESISTORS THAT WILL FORCE THE CORRECT
OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178kΩ 1%,
R2B = 4.75Ω 1%, R5B = 4.53kΩ 1%.
USE JUMPERS INSTEAD OF R2A AND R5A (POTS).
FOR HIGHER POWER USE MORE V
CC
DECOUPLING.
*
**
***
PRODUCT SPECIFICATION ML4812
REV. 1.0.4 5/31/01 16
Mechanical Dimensions
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID 0.295 - 0.325
(7.49 - 8.26)
0.740 - 0.760
(18.79 - 19.31)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
16
0º - 15º
1
0.055 - 0.065
(1.40 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.02 MIN
(0.50 MIN)
(4 PLACES)
Package: P16
16-Pin PDIP
0.100 - 0.110
(2.54 - 2.79)
PIN 1 ID
SEATING PLANE
0.385 - 0.395
(9.78 - 10.03)
0.350 - 0.356
(8.89 - 9.04)
0.013 - 0.021
(0.33 - 0.53)
0.165 - 0.180
(4.19 - 4.57)
1
0.350 - 0.356
(8.89 - 9.04)
0.385 - 0.395
(9.78 - 10.03)
6
11
16 0.290 - 0.330
(7.36 - 8.38)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
0.009 - 0.011
(0.23 - 0.28)
0.026 - 0.032
(0.66 - 0.81)
0.042 - 0.048
(1.07 - 1.22)
0.042 - 0.056
(1.07 - 1.42)
0.200 BSC
(5.08 BSC)
Package: Q20
20-Pin PLCC
0.146 - 0.156
(3.71 - 3.96)
0.050 BSC
(1.27 BSC)
ML4812 PRODUCT SPECIFICATION
5/31/01 0.0m 002
Stock#DS30004812
2001 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
Part Number Temperature Range Package
ML4812CP 0°C to 70°C Molded PDIP (P16)
ML4812CQ 0°C to 70°C Molded PLCC (Q20 )
