FN8388
Rev.5.00
Nov 9, 2017
ISL28025
Precision Digital Power Monitor with Real Time Alerts
DATASHEET
FN8388 Rev.5.00 Page 1 of 52
Nov 9, 2017
The ISL28025 is a bidirectional high-side and low-side digital
current sense and voltage monitor with a serial interface. The
device monitors power supply current and voltage, which
provides the digital results along with calculated power. The
ISL28025 provides tight accuracy of less than 0.1% for both
voltage and current monitoring.
The VCC power can either be externally supplied or internally
regulated, which allows the ISL28025 to handle a
common-mode input voltage range from 0V to 60V. The wide
range permits the device to handle telecom, automotive and
industrial applications with minimal external circuitry.
An 8-bit voltage DAC enable DC/DC converter output voltage
margining (20 Pin QFN) Fault indication includes Bus Voltage
window and over-current fast fault logic indication. The
ISL28025 includes an integrated temperature sensor for
monitoring.
The ISL28025 serial interface is PMBus compatible and
operates down to 1.2V. It draws an average current of just
1.3mA and is available in the space saving 16 ball WLCSP
package. It is also available in a 20 lead QFN 4x4 (1.85SQmm
EPAD)The parts operate across the full industrial temperature
range from -40°C to +125°C.
Related Literature
• For a full list of related documents, visit our website
-ISL28025 product page
Features
• Bus voltage sense range . . . . . . . . . . . . . . . . . . . . . . 0V to 60V
• Voltage gain error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05%
• Current gain error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05%
• High or low (RTN) side sensing
• Bidirectional current sensing
• Auxiliary low voltage input channel
•∆∑ADC, 16-bit native resolution
• Programmable averaging modes
• Internal 3.3V regulator
• Internal temperature sense
• Over-voltage/undervoltage and current fault monitoring with
500ns detection delay
• 8-bit voltage output DAC (20 Pin QFN)
•I
2C/SMBus/PMBus interface that handles 1.2V supply
• 55 I2C slave addresses
Applications
• Data processing servers
• DC power distribution
• Telecom equipment
• Portable communication equipment
• DC/DC and AC/DC converters
• Automotive power
•Many I
2C ADC with alert applications
LOAD
I2C
SMBUS
A1
SCL
SDA
VINP
GND
ADC
16-Bit
A0
ISL28025
VCC
VINM
VBUS
SMBALERT1
A2
Vmcu
GND
GPIO/Int
SDA
SCL
R_pullUp
R_pullUp
MCU
SMBALERT2
(ECLK WLCSP)
I2CVCC
3.3V
Vreg
Vreg_in
Vreg_Out
AuxV
TEMP
SENSE
PMBus
REG
MAP
SW MUX
FROM 1.8V TO 5.5V
VOUT
FB
ISL9110
3.3V
BUCK/
BOOST
En
PG
GND,
PGND
MODE
PVIN
Lo
VIN
1µF
LX2
LX1
10µF
RSH
DAC_OUT
(QFN)
DAC(8‐BIT)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
ISL28025
FN8388 Rev.5.00 Page 2 of 52
Nov 9, 2017
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions 16 PIN WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions 20 lead QFN 4x4 (1.85SQmm EPAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Packet Error Correction (PEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IC Device Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Global IC Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Primary and Auxiliary Channel Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Measurement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Threshold Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SMB Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
External Clock Control (16 Pin WLCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Voltage Margin / DAC_OUT (20 Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SMBus/I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SMBus and PMBus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Group Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Fast Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overranging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Shunt Resistor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A Trace as a Sense Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Lossless Current Sensing (DCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Package Outline Drawing WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ISL28025
FN8388 Rev.5.00 Page 3 of 52
Nov 9, 2017
Block Diagram
FIGURE 2. BLOCK DIAGRAM
FIR AND
DIGITAL
LOGIC
I2C
SM BUS
PM BUS
A0
16
A1
SMBCLK
SMBDAT
OSC
SMBALERT1
VINP
VINM
VBUS
GND
ADC 16-
BIT REG MAP
REF
TEMP
SENSE
OV_TEMP_SET
OC_SET
VBUS_S
3.3V INTERNAL
POWER
CLOCK
UV_SET
REG
VIN_M
VIN_P
DAC_OUT
(20 Pin QFN)
DAC (8-BIT)
SW Mux
OC
DAC
OV/
TEMP
DAC
UV
DAC
I2CVCC
SMBALERT2
LS
LS
CM = 0 to 60V
A2
AUXV
VREG_IN
VREG_OUT VCC
DIGITAL FILTER
0, 2, 4, 8µS
DIV
VBUS_S
Temp_V
VBUS_S
Temp_V
ONLY FOR PRI CHL
EXT_CLK
(16 Pin WLCSP)
{
PRIMARY CH
Ordering Information
PART NUMBER PART
MARKING
VBUS OPTION
(V)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant) PKG. DWG. #
ISL28025FR12Z (Notes 3, 4) 280 25R12Z 12 - 20 lead QFN 4x4 (1.85SQmm EPAD) L20.4x4J
ISL28025FR12Z-T (Notes 1, 2, 3) 280 25R12Z 12 6k 20 lead QFN 4x4 (1.85SQmm EPAD) L20.4x4J
ISL28025FR12Z-T7A (Notes 1, 2, 3) 280 25R12Z 12 250 20 lead QFN 4x4 (1.85SQmm EPAD) L20.4x4J
ISL28025FI12Z-T (Notes 1, 2, 3) 2512 12 3k 16 Ball WLCSP W4x4.16C
ISL28025FI12Z-T7A (Notes 1, 2, 3) 2512 12 250 16 Ball WLCSP W4x4.16C
ISL28025FI60Z-T (Notes 1, 2, 3) 2560 60 3k 16 Ball WLCSP W4x4.16C
ISL28025FI60Z-T7A (Notes 1, 2, 3) 2560 60 250 16 Ball WLCSP W4x4.16C
ISL28025EVKIT1Z Evaluation Kit
ISL28025EVAL1Z Evaluation Board
NOTES:
1. Refer to TB347 for details on reel specifications.
2. These Pb-free WLCSP packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball
terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP packaged products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the product information page for the ISL28025. For more information on MSL, see TB363.
4. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the P-free requirements of IPC/JEDEC J STD-020.
ISL28025
FN8388 Rev.5.00 Page 4 of 52
Nov 9, 2017
Pin Configuration
ISL28025
TOP VIEW
1.85SQmm
EPAD
A
B
C
D
4
GND
VREG_OUT
VCCI2CVCC
3
VINM
SMBALERT2/
ECLK
A0
SMBDAT
2
VINP
A2A1 SMBCLK
1
VBUS
VREG_IN AUXV
SMBALERT1
ISL28025FI -- 16 Pin (BALL) 0.5mm PITCH WLCSP ISL28025FR -- 20 lead QFN 4x4 (1.85SQmm EPAD)
VREG_IN
VINP
VINM
VREG_OUT
VCC
SMBCLK
SMBDAT
NC
SMBALERT1
SMBALERT2
VBUS
GND
AUXV
DAC_OUT
NC
I2CVCC
A2
A1
A0
GND
1
2
3
4
5
15
14
13
12
11
20 19 18 17 16
678910
Pin Descriptions 16 Ball WLCSP
16 PIN
WLCSP PIN NAME TYPE/DIR PIN DEFINITION
A1 VREG_OUT Power Voltage regulator output. Connect a proper decoupling capacitor to this pin
A2 VINM Analog Input Current sense minus input
A3 VINP Analog Input Current sense plus input
A4 VBUS Power VBus voltage sense
B1 I2CVCC Power I2C level shifter power supply. Connect this pin to the VCC pin if level shifters are not used
B2 VCC Power Chip power supply
B3 VREG_IN Power Voltage regulator input. Connect this pin to ground if a voltage regulator is not used
B4 AUXV Analog Input Auxiliary port single-ended input
C1 A0 Digital Input I2C address input
C2 A1 Digital Input I2C address input
C3 A2 Digital Input I2C address input
C4 SMBCLK Digital Input SMBus/I2C clock input
D1 GND Power Ground
D2 SMBALERT2/ECLK Digital Input/Output External ADC clock input or CPU interrupt signal. It is used as a CPU interrupt signal only when
this pin is not configured as external clock input
D3 SMBALERT1 Digital Output SMBus Alert1, open collector output
D4 SMBDAT Digital Input SMBus/I2C data
ISL28025
FN8388 Rev.5.00 Page 5 of 52
Nov 9, 2017
Pin Descriptions 20 Lead QFN 4x4 (1.85SQmm EPAD)
PIN NUMBER PIN NAME TYPE/DIR PIN DEFINITION
1 VBUS Power VBUS voltage sense
2GND PowerGround
3 AUXV Analog Input Auxiliary port single-ended input
4 DAC_OUT Analog Output DAC voltage output
5NC FloatNo Connection
6 SMBCLK Digital Input SMBus/I2C clock input
7 SMBDAT Digital Input/Output SMBus/I2C data
8NC FloatNo Connection
9 SMBALERT1 Digital Output SMBus Alert1, open-drain output
10 SMBALERT2 Digital Output CPU interrupt signal
11 GND Power Ground
12 A0 Digital Input SMBus/I2C address input
13 A1 Digital Input SMBus/I2C address input
14 A2 Digital Input SMBus/I2C address input
15 I2CVCC Power I2C level shifter power supply. Connect this pin to the VCC pin if a level shifter is not used
16 VCC Power Chip power supply
17 VREG_OUT Power Voltage regulator output. Connect a proper decoupling capacitor to this pin
18 VINM Analog Input Current sense minus input
19 VINP Analog Input Current sense plus input
20 VREG_IN Power Voltage regulator input. Connect this pin to ground if a voltage regulator is not used
EPAD NEG SUBSTRATE GND or most negative voltage
ISL28025
FN8388 Rev.5.00 Page 6 of 52
Nov 9, 2017
TABLE 1. DPM PORTFOLIO COMPARISON - ISL28022 vs ISL28023 vs ISL28025 (Dual Package)
DESCRIPTION
BASIC DIGITAL
POWER MONITOR
FULL FEATURE
DIGITAL POWER MONITOR
DIGITAL POWER MONITOR
DUAL PACKAGE OPTIONS
PART NUMBER ISL28022 ISL28023 ISL28025
PACKAGE MSOP10, QFN16 QFN24 WLCSP-16 / QFN20
Temperature Range -40°C to +125°C -40°C to +125°C -40°C to +125°C
0V to 60V Input Range 0V to 60V Opt 1: 0V to 60V
Opt 2: 0V to 16V
Opt 1: 0V to 60V WLCSP-16 only
Opt 2: 0V to 16V
ADC 16-bit 16-bit 16-bit
+25°C Gain Error 0.30% 0.25% 0.25%
Current Measure LSB Step 10µV 2.5µV 2.5µV
+25°C Offset 75µV 30µV 30µV
Primary Differential Shunt Input X X X
Channel Independent Bus Voltage X X X
LV Aux Differential Shunt Input X
Channel Independent Bus Voltage X X
VBus LSB Step Low Voltage Bus 0.25mV 0.25mV
High Voltage Bus 4mV 1mV/0.25mV 1mV/0.25mV
External Temperature Sensor Input X
HV Internal Regulator (3.3VOUT)XX
Fast OC/OV/UV Alert Outputs 2 Outputs 2 Outputs
Margin DAC XQFN20
Internal Temperature Sensor X X
User Select Conversion Mode/Sample Rate X X X
Peak Min/Max Current Registers X X
Slave Address Locations 16 Addresses 55 Addresses 55 Addresses
I2C Level Translators XX
PMBus XX
I2C/SMBus X X X
High Speed (3.4MHz) I2C Mode X X X
External Clock Input X X WLCSP-16
Power Shutdown Mode X X X
ISL28025
FN8388 Rev.5.00 Page 7 of 52
Nov 9, 2017
Absolute Maximum Ratings Thermal Information
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0V
I2C_VCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0V
VBUS (ISL28025FI60), REG_IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63V
VBUS (ISL28025FI12, ISL28025FR12) . . . . . . . . . . . . . . . . . . . . . . 16.684V
Common-Mode Input Voltage (VINP, VINM). . . . . . . . . . . . . . . . . . . . . . . 63V
Differential Input Voltage (VINP, VINM) . . . . . . . . . . . . . . . . . . . . . . . . . ±63V
AUXV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC - GND
Input Voltage (Digital Pins) . . . . . . . . . . . . . . . (GND - 0.3) to I2CVCC + 0.3V
Output Voltage (Digital Pins) . . . . . . . . . . . . . . (GND - 0.3) to I2CVCC + 0.3V
Output Current (VREG_OUT, DAC_OUT (20 Pin QFN)). . . . . . . . . . . . . 10mA
Open Drain Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Open Drain Voltage (SMBALERT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Latch-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA (at +125°C)
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
16 Ball WLCSP (Notes 5, 6). . . . . . . . . . . . . . . 80 1
20 lead QFN 4x4 (1.85SQmm EPAD)(Notes 5, 6)40 2.5
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is taken at the package top center. or bottom thermal pad/PCB though hole array.
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP - VINM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNIT
PRIMARY CHANNEL
VSHUNT Measurement Range
(VINP to VINM)
VSHUNT 0±81.91mV
1LSB Step Shunt Voltage Step_shunt 2.5 µV
VSHUNT Offset Voltage Vshunt_vos ±2.5 ±50 µV
VSHUNT Offset Voltage vs Temperature Vshunt_TC T = -40°C to +125°C ±0.04 ±0.3 µV/°C
VSHUNT Vos vs Common-Mode Vshunt_CMRR ISL28025FI60Z
VBUS = 0V to 60V
±0.2 ±2 µV/V
ISL28025FI12Z, ISL28025FR12Z
VBUS = 0V to 16.384V
±0.2 ±2 µV/V
VSHUNT Vos vs Power Supply Vshunt_PSRR VCC = ±10% of VCC nominal ±0.45 µV/V
VIN Input Leakage Current Ivin VIN = VSHUNT input path selected, OC
detector disabled
15 20 µA
VIN = VSHUNT input path selected, OC
detector enabled
30 40 µA
VIN = VSHUNT input path disabled, OC
detector disabled
0.05 0.1 µA
Usable Bus Voltage Measurement Range VBUS ISL28025FI60Z 0 60 V
ISL28025FI12Z, ISL28025FR12Z 0 16.384 V
1LSB Step Bus Voltage Step_Vbus ISL28025FI60Z 1 mV
ISL28025FI12Z, ISL28025FR12Z 0.25 mV
ISL28025
FN8388 Rev.5.00 Page 8 of 52
Nov 9, 2017
VBUS Offset Voltage Vbus_vos ISL28025FI60Z -20 ±1 20 mV
ISL28025FI12Z, ISL28025FR12Z -5 ±0.25 5 mV
VBUS Offset Voltage vs Temperature Vbus_TC ISL28025FI60Z; T = -40°C to +125°C ±4 ±100 µV/°C
ISL28025FI12Z, ISL28025FR12Z;
T = -40°C to +125°C
±1 ±100 µV/°C
VBUS Voltage Coefficient Vbus_Vco 50 ppm/V
VBUS Vos vs Power Supply Vbus_PSRR ISL28025FI60Z;
VCC = ±10% of VCC nominal
±500 µV/V
ISL28025FI12Z, ISL28025FR12Z
VCC = ±10% of VCC nominal
±125 µV/V
Input Impedance VBUS Zin_Vbus ISL28025FI60Z 600 kΩ
ISL28025FI12Z, ISL28025FR12Z 150 kΩ
AUX CHANNEL
Usable AVXV Voltage Measurement
Range
Vauxv 0 VCC V
1LSB Step AUXV Voltage Step_auxv 100 µV
VAUXV Offset Voltage Vauxv_vos ±0.3 ±4 mV
VAUXV Offset Voltage vs Temperature Vauxv_TC T = -40°C to +125°C ±0.2 ±22 µV/°C
VAUXV Vos vs Power Supply Vauxv_PSRR VCC = ±10% of VCC nominal ±1 mV/V
Auxv Input Impedance Zin_auxv Input path selected 200 kΩ
Input path disabled 10 MΩ
ADC PARAMETERS
ADC Resolution 16 Bits
Primary Shunt Voltage Gain Error ±0.05 ±0.25 %
T = -40°C to +125°C 0 ±60 ppm/°C
Primary Bus Voltage Gain Error ±0.05 ±0.25 %
T = -40°C to +125°C 10 ±70 ppm/°C
Aux Bus Voltage Gain Error ±0.05 ±0.25 %
T = -40°C to +125°C 10 ±65 ppm/°C
Differential Nonlinearity ±1 LSB
ADC TIMING
ADC Conversion Time Resolution ts Power-Up ADC[2:0] = 0h 64 70.4 µs
ADC[2:0] = 1h 128 140.8 µs
ADC[2:0] = 2h 256 281.6 µs
ADC[2:0] = 3h 512 563.2 µs
ADC[2:0] = 4, 5h 1.024 1.126 ms
ADC[2:0] = 6, 7h 2.048 2.253 ms
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP - VINM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNIT
ISL28025
FN8388 Rev.5.00 Page 9 of 52
Nov 9, 2017
THRESHOLD DETECTORS
Overvoltage (OV) VBUS Threshold Voltage
Range
Vbus_Thres_Rng[2:0] = ALL 25 125 % of FS
Overvoltage (OV) VBUS Threshold DAC
Step Size
Vbus_Thres_Rng[2:0] = ALL 1.56 % of FS
Undervoltage (UV) VBUS Threshold Voltage
Range
Vbus_Thres_Rng[2:0] = ALL 0 100 % of FS
Undervoltage (UV) VBUS Threshold DAC
Step Size
Vbus_Thres_Rng[2:0] = ALL 1.56 % of FS
VBUS Threshold Detector Full-Scale
Settings
ISL28025FI60Z
Vbus_Thres_Rng[2:0] = 0; OT_SEL = 0 48 V
Vbus_Thres_Rng[2:0] = 1; OT_SEL = 0 24 V
Vbus_Thres_Rng[2:0] = 2; OT_SEL = 0 12 V
Vbus_Thres_Rng[2:0] = 3; OT_SEL = 0 5 V
Vbus_Thres_Rng[2:0] = 4; OT_SEL = 0 3.3 V
Vbus_Thres_Rng[2:0] = 5; OT_SEL = 0 2.5 V
VBUS Threshold Detector Full-Scale
Settings
ISL28025FI12Z, ISL28025FR12Z
Vbus_Thres_Rng[2:0] = 0; OT_SEL = 0 12 V
Vbus_Thres_Rng[2:0] = 1; OT_SEL = 0 6 V
Vbus_Thres_Rng[2:0] = 2; OT_SEL = 0 3 V
Vbus_Thres_Rng[2:0] = 3; OT_SEL = 0 2.5 V
Vbus_Thres_Rng[2:0] = 4; OT_SEL = 0 0.825 V
Vbus_Thres_Rng[2:0] = 5; OT_SEL = 0 0.625 V
Over-Temperature Threshold Detector
Range
OT_SEL = 1 -40 135 °C
Over-Temperature Threshold Detector
Resolution Error
±5 °C
Overcurrent (OC) VSHUNT Threshold
Voltage Range
OCRNG = ALL 25 125 % of FS
Overcurrent (OC) VSHUNT Threshold DAC
Step Size
OCRNG = ALL 1.56 % of FS
VSHUNT Threshold Detector Full-Scale
Settings
OCRNG = 0 80 mV
OCRNG = 1 40 mV
MARGINING DAC, ANALOG OUTPUT (20 Pin QFN)
Resolution 8Bits
DNL ±1 LSB
INL MDAC[7:0] = 0 to 256 ±3 LSB
Gain Error DAC_MS[2:0] = 0 ±2.5 %
Offset Error DAC_MS[2:0] = 0 ±2 mV
Output Voltage 0.055 2*Vms V
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP - VINM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNIT
ISL28025
FN8388 Rev.5.00 Page 10 of 52
Nov 9, 2017
DAC Mid-Scale VMS DAC_MS[2:0] = 0 0.4 V
DAC_MS[2:0] = 1 0.5 V
DAC_MS[2:0] = 2 0.6 V
DAC_MS[2:0] = 3 0.7 V
DAC_MS[2:0] = 4 0.8 V
DAC_MS[2:0] = 5 0.9 V
DAC_MS[2:0] = 6 1.0 V
DAC_MS[2:0] = 7 1.2 V
Slew Rate 1V/µs
Output Current 1mA
Short-Circuit Current DAC_OUT = VCC 17 mA
DAC_OUT = GND 4.2 mA
Start-Up Time 100 µs
VOLTAGE REGULATOR SPECIFICATION
Input Voltage at REG_IN 4.5 60 V
Output Regulation Voltage 3.18 3.3 3.35 V
Line Regulation VIN 4.5V to 60V 53 150 µV/V
Load Regulation ILOAD = 3.3mA to 6mA 0.2 1.4 mV/mA
Capacitance Drive 0.01 10 µF
Output Short-Circuit T = -40°Cto+125°C 10 mA
Maximum Load Current T = -40°Cto+125°C 6 mA
Start-Up Time 1ms
TEMPERATURE SENSOR
Temperature Sensor Measurement Range -40 125 °C
Temperature Accuracy T = +25°C +3.2 °C
Temperature Resolution 0.5 °C
Measurement Time 0.5 ms
SMBus/I2C INTERFACE SPECIFICATIONS
SMBDAT and SMBCLK Input Buffer Low
Voltage
VIL -0.3 0.3 x
I2CVCC
V
SMBDAT and SMBCLK Input Buffer High
Voltage
VIH 0.7 x
I2CVCC
I2CVCC +
0.3
V
SMBDAT and SMBCLK Input Buffer
Hysteresis
Hysteresis 0.05 x
I2CVCC
V
SMBDAT Output Buffer Low Voltage,
Sinking 3mA
VOL I2CVCC = 5V, IOL = 3mA 0 0.02 0.4 V
SMBDAT and SMBCLK Pin Capacitance CPIN TA = +25°C, f = 1MHz, I2CVCC = 5V,
VIN =0V, V
OUT = 0V
10 pF
SMBCLK Frequency fSMBCLK 400 kHz
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP - VINM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNIT
ISL28025
FN8388 Rev.5.00 Page 11 of 52
Nov 9, 2017
Pulse Width Suppression Time at SMBDAT
and SMBCLK Inputs
tIN Any pulse narrower than the maximum
specification is suppressed
50 ns
SMBCLK Falling Edge to SMBDAT Output
Data Valid
tAA SMBCLK falling edge crossing 30% of
I2CVCC, until SMBDAT exits the 30% to
70% of I2CVCC window
900 ns
Time the Bus Must be Free Before the
Start of a New Transmission
tBUF SMBDAT crossing 70% of I2CVCC
during a STOP condition, to SMBDAT
crossing 70% of I2CVCC during the
following START condition
1300 ns
Clock Low Time tLOW Measured at the 30% of I2CVCC
crossing
1300 ns
Clock High Time tHIGH Measured at the 70% of I2CVCC
crossing
600 ns
START Condition Set-Up Time tSU:STA SMBCLK rising edge to SMBDAT falling
edge. Both crossing 70% of I2CVCC
600 ns
START Condition Hold Time tHD:STA From SMBDAT falling edge crossing
30% of I2CVCC to SMBCLK falling edge
crossing 70% of I2CVCC
600 ns
Input Data Set-Up Time tSU:DAT From SMBDAT exiting the 30% to 70%
of VCC window, to SMBCLK rising edge
crossing 30% of I2CVCC
100 ns
Input Data Hold Time tHD:DAT From SMBCLK falling edge crossing
30% of I2CVCC to SMBDAT entering the
30% to 70% of I2CVCC window
20 900 ns
STOP Condition Set-Up Time tSU:STO From SMBCLK rising edge crossing
70% of I2CVCC, to SMBDAT rising edge
crossing 30% of I2CVCC
600 ns
STOP Condition Hold Time tHD:STO From SMBDAT rising edge to SMBCLK
falling edge. Both crossing 70% of
I2CVCC
600 ns
Output Data Hold Time tDH From SMBCLK falling edge crossing
30% of I2CVCC, until SMBDAT enters
the 30% to 70% of I2CVCC window
0ns
SMBDAT and SMBCLK Rise Time tRFrom 30% to 70% of I2CVCC 20 + 0.1 x
Cb
300 ns
SMBDAT and SMBCLK Fall Time tFFrom 70% to 30% of I2CVCC 20 + 0.1 x
Cb
300 ns
Capacitive Loading of SMBDAT or
SMBCLK
Cb Total on-chip and off-chip 10 400 pF
SMBDAT and SMBCLK Bus Pull-Up
Resistor Off-Chip
RPU Maximum is determined by tR and tF
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~ 20kΩ
1kΩ
POWER SUPPLY
Power Supply Voltage at VCC Vvcc 3.0 3.3 5.5 V
Power Supply Voltage at I2CVCC Vi2cvcc f = DC to 400kHz 1.2 3.3 5.5 V
Only ADC in Conversion mode All other blocks are disabled 690 830 µA
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP - VINM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNIT
ISL28025
FN8388 Rev.5.00 Page 12 of 52
Nov 9, 2017
Only ADC in Idle Mode All other blocks are disabled 640 705 µA
Only Threshold Detectors All three detectors are active 760 945 µA
Fully Enabled Chip Current All functional blocks enabled 1000 1260 µA
Fully Disabled Chip Current All functional blocks disabled 5 15 µA
Voltage Regulator Ivreg_in Vreg_in = 4.5V to 60V; RLOAD = open 26 35 µA
I2C Supply Current Ii2cvcc SMBCLK = 100kHz; I2CVCC = 3.3V 15 µA
I2C Idle Supply Current Ii2cvcc_pd Input signals are static 100 nA
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Compliance to datasheet limits is assured by one or
more of the following methods: production test, characterization and design.
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP - VINM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNIT
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified.
FIGURE 3. PRIMARY VSHUNT VOS FIGURE 4. PRIMARY VSHUNT VOS vs VCC
FIGURE 5. PRIMARY VSHUNT VOS TC (-40°C TO +125°C) FIGURE 6. PRIMARY VSHUNT VOS vs TEMPERATURE
0
1
2
3
4
5
6
7
-50.0
-37.5
-25.0
-12.5
0
12.5
25.0
37.5
50.0
VOS (µV)
HITS
-50
-40
-30
-20
-10
0
10
20
30
40
50
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
VOS (µV)
T = +125°C
T = -40°C
T = +25°C
0
1
2
3
4
5
6
7
8
-0.300
-0.225
-0.150
-0.075
0
0.075
0.150
0.225
0.300
VOS TC (µV/°C)
HITS
-40
-20
0
20
40
60
80
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
VOS (µV)
VCC = 5V
VCC = 3V
VCC = 3.3V
ISL28025
FN8388 Rev.5.00 Page 13 of 52
Nov 9, 2017
FIGURE 7. PRIMARY VSHUNT CMRR, CMV = (0V TO 60V) FIGURE 8. PRIMARY VSHUNT CMRR vs TEMPERATURE
(CMV = 0V TO 60V)
FIGURE 9. PRIMARY VSHUNT VOS vs CMV FIGURE 10. PRIMARY VSHUNT AC CMRR vs FREQUENCY
FIGURE 11. PRIMARY VSHUNT COMMON-MODE RANGE FIGURE 12. SMBALERT CURRENT DRIVES
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
1
2
3
4
5
6
-500
-375
-250
-125
0
125
250
375
500
PRIMARY CMRR (nV/V)
HITS
-500
-400
-300
-200
-100
0
100
200
300
400
500
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
CMRR (nV/V)
-20
-15
-10
-5
0
5
10
15
20
0 8 16 24 32 40 48 56 64
CMV (V)
VOS (µV)
90
95
100
105
110
115
120
125
130
10 100 1k 10k 100k
FREQUENCY (Hz)
CMRR (dB)
TIME = 0.128ms
TIME = 2.048ms
TIME = 1.024ms
TIME = 0.512ms
TIME = 0.256ms
TIME = 0.64ms
35
45
55
65
75
85
95
-80 -70 -60 -50 -40 -30 -20 -10 0
CMV (mV)
VMEAS (mVP-P)
VINPUT = 80mVP-P SINE WAVE
TO CMV = 60V
FREQUENCY = 100Hz
ADC TIMING = 64µs
0
20
40
60
80
100
120
140
160
180
0.01 0.1 1 10
CURRENT LOAD (mA)
ABS (CHANGE IN VOLTAGE) (mV)
SMBALERT1
SINK
SMBALERT2
SOURCE
SMBALERT2
SINK
ISL28025
FN8388 Rev.5.00 Page 14 of 52
Nov 9, 2017
FIGURE 13. PRIMARY VSHUNT ADC GAIN ERROR FIGURE 14. PRIMARY VSHUNT ADC GAIN ERROR TC
FIGURE 15. PRIMARY VSHUNT MEASUREMENT ERROR vs INPUT FIGURE 16. PRIMARY VSHUNT MEASUREMENT ERROR vs
TEMPERATURE
FIGURE 17. PRIMARY VSHUNT BANDWIDTH vs ADC TIMING FIGURE 18. PRIMARY VSHUNT AND VBUS vs FREQUENCY
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
1
2
3
4
5
6
7
8
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
GAIN ERROR (%)
HITS
0
1
2
3
4
5
6
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
VSHUNT GAIN ERROR TC (ppm/°C)
HITS
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08
VINPUT (V)
MEASUREMENT ERROR (%)
VCC = 5V
VCC = 3V + 3.3V
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
MEASUREMENT ERROR (%)
VCC = 5V
VCC = 3V
VCC = 3.3V
-15
-13
-11
-9
-7
-5
-3
-1
1
10 100 1k 10k 100k
FREQUENCY (Hz)
GAIN (dB)
TIME = 2.048ms
TIME = 1.024ms
TIME = 0.512ms
TIME = 0.256ms
TIME = 0.128ms
50mVP-P SINE WAVE
TIME = 0.64ms
-15
-13
-11
-9
-7
-5
-3
-1
1
10 100 1k 10k 100k
FREQUENCY (Hz)
GAIN (dB)
PRIMARY VBUS
PRIMARY VSHUNT
TIME = 0.64ms
ISL28025
FN8388 Rev.5.00 Page 15 of 52
Nov 9, 2017
FIGURE 19. PRIMARY VBUS VOS FIGURE 20. PRIMARY VBUS VOS vs VCC
FIGURE 21. PRIMARY VBUS VOS TC FIGURE 22. PRIMARY VBUS VOS vs TEMPERATURE
FIGURE 23. PRIMARY VBUS ADC GAIN ERROR FIGURE 24. PRIMARY VBUS ADC GAIN ERROR TC
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
1
2
3
4
5
6
7
8
9
10
-20
-15
-10
-5
0
5
10
15
20
VOS (mV)
HITS
VINPUT = 25mV
-20
-15
-10
-5
0
5
10
15
20
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
VOS (mV)
T = +125°C
T = +25°C
T = -40°C
VINPUT = 25mV
0
2
4
6
8
10
12
-100
-75
-50
-25
0
25
50
75
100
VOS TC (µV/C)
HITS
VINPUT = 25mV
-20
-15
-10
-5
0
5
10
15
20
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
VOS (mV)
VCC = 5V
VCC = 3V
VINPUT = 25mV
VCC = 3.3V
0
1
2
3
4
5
6
7
8
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
GAIN ERROR (%)
HITS
ISL28025-12 (1V TO 16V)
ISL28025-60 (12V TO 60V)
0
1
2
3
4
5
6
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
GAIN ERROR TC (ppm/C)
HITS
ISL28025-60
(12V TO 60V) ISL28025-12 (1V TO 16V)
ISL28025
FN8388 Rev.5.00 Page 16 of 52
Nov 9, 2017
FIGURE 25. PRIMARY VBUS MEASUREMENT ERROR vs INPUT FIGURE 26. PRIMARY VBUS MEASUREMENT ERROR vs TEMPERATURE
FIGURE 27. AUXILIARY VBUS BANDWIDTH vs ADC TIMING FIGURE 28. AUXILIARY VSHUNT AND VBUS vs FREQUENCY
FIGURE 29. AUXILIARY VBUS VOS FIGURE 30. AUXILIARY VBUS VOS vs VCC
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
0 8 16243240485664
VINPUT (V)
MEASUREMENT ERROR (%)
VCC (12) = 5V
VCC (12) = 3V
VCC (12) = 3.3V
VCC (60) = 3V
VCC (60) = 5V
VCC (60) = 3.3V
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
MEASUREMENT ERROR (%)
VCC (12) = 5V
VCC (12) = 3V
VCC (12) = 3.3V
VCC (60) = 5V
VCC (60) = 3V
VCC (60) = 3.3V
-15
-13
-11
-9
-7
-5
-3
-1
1
10 100 1k 10k 100k
FREQUENCY (Hz)
GAIN (dB)
TIME = 0.256ms
TIME = 0.128ms
TIME = 0.64ms
TIME = 2.048ms
TIME = 1.024ms
TIME = 0.512ms
-15
-13
-11
-9
-7
-5
-3
-1
1
10 100 1k 10k 100k
FREQUENCY (Hz)
GAIN (dB)
AUX V
BUS
TIME = 0.64ms
0
2
4
6
8
10
12
-5.00
-3.75
-2.50
-1.25
0
1.25
2.50
3.75
5.00
VOS (mV)
HITS
VINPUT = 25mV
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
VOS (mV)
T = -40°C
T = +125°C
T = +25°C
VINPUT = 25mV
ISL28025
FN8388 Rev.5.00 Page 17 of 52
Nov 9, 2017
FIGURE 31. AUXILIARY VBUS VOS TC FIGURE 32. AUXILIARY VBUS VOS vs TEMPERATURE
FIGURE 33. AUXILIARY VBUS ADC GAIN ERROR FIGURE 34. AUXILIARY VBUS ADC GAIN ERROR TC
FIGURE 35. AUXILIARY VBUS MEASUREMENT ERROR vs INPUT FIGURE 36. AUXILIARY VBUS MEASUREMENT ERROR vs
TEMPERATURE
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
2
4
6
8
10
12
-20
-15
-10
-5
0
5
10
15
20
VOS TC (µV/°C)
HITS
VINPUT = 25mV
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
VOS (mV)
VCC = 3.3V
VCC = 5V
VCC = 3V
VINPUT = 25mV
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
GAIN ERROR (%)
HITS
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
VAUXSHUNT GAIN ERROR TC (ppm/°C)
HITS
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 0.51.01.52.02.53.03.54.04.55.05.5
AUX V (V)
MEASUREMENT ERROR (%)
VCC = 5V
VCC = 3V VCC = 3.3V
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
MEASUREMENT ERROR (%)
VCC = 3V
VCC = 3.3V
VCC = 5V
ISL28025
FN8388 Rev.5.00 Page 18 of 52
Nov 9, 2017
FIGURE 37. SUPPLY CURRENT vs TEMPERATURE FIGURE 38. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE
FIGURE 39. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 40. SUPPLY CURRENT vs SUPPLY VOLTAGE
(POWER-DOWN MODES)
FIGURE 41. PRIMARY VSHUNT BIAS CURRENT vs TEMPERATURE FIGURE 42. PRIMARY VSHUNT BIAS CURRENT vs TEMPERATURE
(POWER-DOWN MODE)
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
200
400
600
800
1000
1200
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
MODE = Nrml + OC
MODE = Nrml + OV MODE = Nrml
MODE = Nrml + UV
0
10
20
30
40
50
60
70
80
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
MODE = ADC PD,
MODE = PD
0
200
400
600
800
1000
1200
3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
MODE = Nrml + OC
MODE = Nrml + UV
MODE = Nrml + OV MODE = Nrml
0
1
2
3
4
5
6
7
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
SUPPLY CURRENT (µA)
MODE = ADC PD,
MODE = PD
-9.8
-9.6
-9.4
-9.2
-9.0
-8.8
-8.6
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
BIAS CURRENT (µA)
MODE = Nrml + OC
MODE = Nrml
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
BIAS CURRENT (µA)
MODE = PD,
MODE = ADCPD
ISL28025
FN8388 Rev.5.00 Page 19 of 52
Nov 9, 2017
FIGURE 43. PRIMARY VSHUNT BIAS CURRENT OFFSET vs
TEMPERATURE
FIGURE 44. PRIMARY VSHUNT BIAS CURRENT OFFSET vs
TEMPERATURE (POWER-DOWN MODE)
FIGURE 45. PRIMARY VSHUNT BIAS CURRENT vs COMMON-MODE
VOLTAGE
FIGURE 46. PRIMARY VSHUNT BIAS CURRENT vs COMMON-MODE
VOLTAGE (POWER-DOWN MODES)
FIGURE 47. PRIMARY VSHUNT OFFSET CURRENT vs COMMON-MODE
VOLTAGE
FIGURE 48. PRIMARY VSHUNT OFFSET CURRENT vs COMMON-MODE
VOLTAGE (POWER DOWN MODES)
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
-140
-120
-100
-80
-60
-40
-20
0
20
40
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
OFFSET CURRENT (nA)
MODE = Nrml + OC
MODE = Nrml
-35
-30
-25
-20
-15
-10
-5
0
5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
OFFSET CURRENT (nA)
MODE = PD
MODE = ADCPD
-12
-10
-8
-6
-4
-2
0
0 8 16 24 32 40 48 56 64
CMV (V)
BIAS CURRENT (µA)
MODE = Nrml
MODE = Nrml + OC
-0.007
-0.006
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0 8 16 24 32 40 48 56 64
CMV (V)
BIAS CURRENT (µA)
MODE = PD
MODE = ADC PD
-40
-35
-30
-25
-20
-15
-10
-5
0
5
0 8 16 24 32 40 48 56 64
CMV (V)
OFFSET CURRENT (nA)
MODE = Nrml + OC
MODE = Nrml
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
0 8 16 24 32 40 48 56 64
CMV (V)
OFFSET CURRENT (nA)
MODE = PD
MODE = ADC PD
ISL28025
FN8388 Rev.5.00 Page 20 of 52
Nov 9, 2017
FIGURE 49. VREG OUTPUT VOLTAGE DISTRIBUTION FIGURE 50. VREG OUTPUT vs TEMPERATURE
FIGURE 51. VREG OUTPUT vs INPUT VOLTAGE FIGURE 52. VREG OUTPUT vs CURRENT LOAD
FIGURE 53. VREG INPUT CURRENT vs INPUT VOLTAGE FIGURE 54. VREG INPUT CURRENT vs TEMPERATURE
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
1
2
3
4
5
6
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
3.40
VREG (V)
HITS
3.20
3.25
3.30
3.35
3.40
3.45
3.50
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
VREG OUTPUT (V)
ILOAD = 0mA
ILOAD = 3mA
ILOAD = 6mA
3.20
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
3.40
0 8 16 24 32 40 48 56 64
VREG INPUT (V)
VREG OUTPUT (V)
-25
-20
-15
-10
-5
0
0.1 1 10 100
ILOAD (mA)
VREG CHANGE (mV)
2
3
4
5
6
7
8
0 8 16 24 32 40 48 56 64
VREG INPUT VOLTAGE (V)
IREG (µA)
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
IREG (µA)
ISL28025
FN8388 Rev.5.00 Page 21 of 52
Nov 9, 2017
FIGURE 55. INTERNAL TEMPERATURE SENSOR ACCURACY FIGURE 56. INTERNAL TEMPERATURE ACCURACY vs VCC
FIGURE 57. INTERNAL TEMPERATURE ACCURACY AT T = +25°C FIGURE 58. OV OR UV OR OC ALERT RESPONSE TIME
FIGURE 59. PRIMARY SHUNT STABILITY: STDEV vs ACQUISITION
TIME
FIGURE 60. PRIMARY SHUNT STABILITY: RANGE vs ACQUISITION
TIME
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
-2
-1
0
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
VCC = 5VVCC = 3V VCC = 3.3V
Teqn_3.3 = 1.681*10-10 * Tmeas5 - 7.98 * 10-8
* Tmeas4 - 2.2* 10-6 * Tmeas3 + 3.834* 10-4
* Tmeas2 + 1.003 * Tmeas1 + 3.068
V
CC
= 3V
-5
-4
-3
-2
-1
0
1
2
3
4
5
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
TEMPERATURE (°C)
T = +125°C
T = +25°C
T = -40°C
0
1
2
3
4
5
6
7
8
-5.00
-3.75
-2.50
-1.25
0
1.25
2.50
3.75
5.00
TEMPERATURE (°C)
HITS
-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
TIME (µs)
INPUT
SMBALERT
0
10
20
30
40
50
60
70
80
50 250 450 650 850 1050 1250 1450 1650 1850 2050
ADC TIMING (µs)
SAMPLE SIZE = 1024
SIGMA OF MEASUREMENT (µV)
0
50
100
150
200
250
300
350
400
450
500
50 250 450 650 850 1050 1250 1450 1650 1850 2050
ADC TIMING (µs)
SAMPLE SIZE = 1024
RANGE OF MEASUREMENT (µV)
ISL28025
FN8388 Rev.5.00 Page 22 of 52
Nov 9, 2017
Functional Description
Overview
The ISL28025 is a digital current, voltage and power monitoring
device for high and low-side power monitoring in positive and
negative voltage applications.
The Digital Power Monitor (DPM) requires an external shunt
resistor to enable current measurements. The shunt resistor
translates the bus current to a voltage. The DPM measures the
voltage across the shunt resistors and reports the measured
value out digitally using an I2C interface. A register within the
DPM is reserved to store the value of the shunt resistor. The
stored current sense resistor value allows the DPM to output a
current value to an external digital device.
The ISL28025 can monitor the voltage, current and power of a
power supply rail. The ISL28025 has an additional low voltage
read to measure a voltage after the rail has been regulated. The
primary channel will allow and measure voltages from 0V to 60V
or from 0V to 16.384V, depending on the option of the ISL28025.
The auxiliary channel can tolerate and measure voltage from 0V
to VCC.
The ISL28025 has continuous fault detection for the primary
channel. The DPM can be configured to set an alert in the
instance of an overvoltage, undervoltage and/or overcurrent
event. The response time of the alert is 500ns from the event.
The ISL28025 has a temperature sensor with fault detection.
An 8-bit margin DAC, controllable through I2C communication, is
incorporated into the DPM. The voltage margining feature allows
for the adjustment of the regulated voltage to the load. The
margin DAC can help in proving the load robustness versus the
applied supply voltage.
The ISL28025 offers a 3.3V voltage regulator that can be used to
power the chip in addition to low power peripheral circuitry. The
DPM has an I2C power pin that allows the I2C master to set the
digital communication supply voltage to the chip. The operating
supply voltage for the DPM ranges from 3V to 5.5V. The device
will accept I2C supply voltages between 1.2V and 5.5V.
The ISL28025 accepts SMBus protocols up to 3.4MHz. The
device is PMBus compliant up to 400MHz. The device has Packet
Error Code (PEC) functionality. The PEC protocol uses an 8-bit
Cyclic Redundance Check (CRC-8) represented by the polynomial
x8+x2+x1+1. The ISL28025 can be configured for up to 55
unique slave addresses using three address select bits. The large
amount of addressing allows 55 parts to communicate on a
single I2C bus. It also gives the designer the flexibility to select a
unique address when another slave address conflicts with the
DPM on the same I2C bus.
Functional Pin Descriptions
VBUS
VBUS is the power bus voltage input pin. The pin should be
connected to the desired power supply bus to be monitored. The
voltage range for the pin is from 0V to 60V or 0V to 16V
depending on the ISL28025 version.
VINP
VINP is the shunt voltage monitor positive input pin. The pin
connects to the most positive voltage of the current shunt
resistor. The voltage range for the pin is from 0V to 60V or 0V to
16V depending on the ISL28025 version. The maximum
measurable voltage differential between VINP and VINM is
80mV.
VINM
VINM is the shunt voltage monitor negative input pin. The pin
connects to the most negative voltage of the current shunt
resistor. The voltage range for the pin is from 0V to 60V or 0V to
16V depending on the ISL28025 version. The maximum
measurable voltage differential between VINP and VINM is
80mV.
FIGURE 61. PRIMARY SHUNT STABILITY: STDEV vs INTERNAL
AVERAGING
FIGURE 62. PRIMARY SHUNT STABILITY: RANGE vs INTERNAL
AVERAGING
Typical Performance Curves TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, Auxv = 3V, conversion time;
Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. (Continued)
0
2
4
6
8
10
12
0 40 80 120 160 200 240 280 320 360 400 440 480 520
INTERNAL AVERAGING
SAMPLE SIZE = 1024
ADC TIMING = 2.048ms
SIGMA OF MEASUREMENT (µV)
0
5
10
15
20
25
30
35
0 40 80 120 160 200 240 280 320 360 400 440 480 520
INTERNAL AVERAGING
SAMPLE SIZE = 1024
ADC TIMING = 2.048ms
RANGE OF MEASUREMENT (µV)
ISL28025
FN8388 Rev.5.00 Page 23 of 52
Nov 9, 2017
AUXV
AUXV is the power bus voltage input pin. The pin should be
connected to the desired power supply bus to be monitored. The
voltage range for the pin is from 0V to VCC.
VCC
VCC is the positive supply voltage pin. VCC is an analog power
pin. VCC supplies power to the device. The allowable voltage
range is from 3V to 5.5V.
I2CVCC
I2CVCC is the positive supply voltage pin. I2CVCC is an analog
power pin. I2CVCC supplies power to the digital communication
circuitry, I2C, of the device. The allowable voltage range is from
1.2V to 5.5V.
GND
GND is the device ground pin. For single supply systems, the pin
connects to system ground. For dual supply systems, the pin
connects to the negative voltage supply in the system.
VREG_IN
VREG_IN is the voltage regulator input pin. The operable input
voltage range to the regulator is 4.5V to 60V.
VREG_OUT
VREG_OUT is the voltage regulator output pin. The regulated
output voltage of 3.3V is sourced from the VREG_OUT pin.
DAC_OUT (20PIN QFN)
DAC_OUT is the margin DAC output pin. The output of the DAC
voltage ranges from 0V to 2.4V. The voltage DAC is controlled
through internal registers.
ADDRESS PINS (A0, A1, A2)
A0, A1 and A2 are address selectable pins. The address pins are
I2C/SMBus slave address select pins that are multilogic
programmable for a total of 55 different address combinations.
There are four selectable levels for the address pins, I2CVCC,
GND, SCL/SMBCLK and SDA/SMBDAT. See Table 48 on page 40
for more details in setting the slave address of the device.
SMBDAT
SDA/SMBDAT is the serial data input/output pin. SDA/SMBDAT
is a bidirectional pin used to transfer data to and from the device.
The pin is an open-drain output and may be wired with other
open-drain/collector outputs. The input buffer is always active
(not gated). The open-drain output requires a pull-up resistor for
proper functionality. The pull-up resistor should be connected to
I2CVCC of the device.
SMBCLK
SCL/SMBCLK is the serial clock input pin. The SCL/SMBCLK
input is responsible for clocking in all data to and from the
device. The input buffer on the pin is always active (not gated).
The input pin requires a pull-up resistor to I2CVCC of the device.
SMBALERT PINS (SMBALERT1, SMBALERT2)
The SMBALERT pins are output pins. The SMBALERT1 is an
open-drain output and requires a pull-up resistor to a power
supply up to 24V. The SMBALERT2 has a push/pull output stage.
The SMBALERT pins are fault acknowledgment pins. The pin can
be connected to peripheral circuitry to halt operations when a
fault event occurs.
ECLK (16 PIN WLCSP)
ECLK is the External clock pin. ECLK is an input pin. The pin
provides a connection to the system clock. The system clock is
connected to the ADC. The acquisitions rate of the ADC can be
varied through the ECLK pin. The pin functionality is set through a
control register bit.
TABLE 2. ISL28025 REGISTER DESCRIPTIONS
REGISTER
ADDRESS
(HEX) REGISTER NAME FUNCTION
POWER ON RESET
VALUE (HEX)
NUMBER
OF BYTES
ACCESS
TYPE PAGE
IC DEVICE DETAILS
19 CAPABILITY PMBus Supportability B0 1 R 26
20 VOUT_MODE Describes the ADC Read Back Format 40 1 R 26
99 PMBUS_REV PMBus Revision 22 1 R 26
AD IC_DEVICE_ID Device ID 49534C3238303235 8 R 26
AE IC_DEVICE_REV Device Revision and Silicon Version 000002 3 R 26
GLOBAL IC CONTROLS
12 RESTORE_DEFAULT_ALL Soft Reset N/A 0 W 27
01 OPERATION Turns the Device On and Off 80 1 R/W 27
PRIMARY AND AUXILIARY CHANNEL CONTROLS
D2 SET_DPM_MODE Configures the ISL28025 0A 1 R/W 27
D3 DPM_CONV_STATUS Indicates the Status of a Conversion N/A 1 R 28
D4 CONFIG_ICHANNEL Shunt Inputs (Primary and Auxiliary) Configuration 0387 2 R/W 28
ISL28025
FN8388 Rev.5.00 Page 24 of 52
Nov 9, 2017
38 IOUT_CAL_GAIN Calibration that Enables Primary Current Measurements 0000 2 R/W 29
D5 CONFIG_VCHANNEL Bus Inputs (Primary and Auxiliary) Configuration 0387 2 R/W 29
D7 CONFIG_PEAK_DET Enables Primary Channel Current Peak Detector 00 1 R/W 29
MEASUREMENT REGISTERS
D6 READ_VSHUNT_OUT Primary Shunt Measurement Value 0000 2 R 30
8B READ_VOUT Primary Bus Measurement Value 0000 2 R 30
8C READ_IOUT Primary Current Measurement Value 0000 2 R 30
D8 READ_PEAK_MIN_IOUT Primary Current Maximum Measurement Value 7FFF 2 R 30
D9 READ_PEAK_MAX_IOUT Primary Current Minimum Measurement Value 8001 2 R 30
96 READ_POUT Primary Power Measurement Value 0000 2 R 30
E1 READ_VOUT_AUX Auxiliary Bus Measurement Value 0000 2 R 30
8D READ_TEMPERATURE_1 Internal Temperature Measurement Value 0000 2 R 30
THRESHOLD DETECTORS
DA VOUT_OV_THRESHOLD_SET Overvoltage/Over-Temperature Threshold Configuration 003F 2 R/W 31
DB VOUT_UV_THRESHOLD_SET Undervoltage Threshold Configuration 00 1 R/W 31
DC IOUT_OC_THRESHOLD_SET Overcurrent Threshold Configuration 003F 2 R/W 32
SMB ALERT
DD CONFIG_INTR Configure the Behavior of the Interrupts 0000 2 R/W 34
DE FORCE_FEEDTHR_ALERT Configure the Path of the Interrupt Signal 00 1 R/W 35
1B SMBALERT_MASK Alert Mask for the SMBALERT1 Pin N/A 2 R/W 37
DF SMBALERT2_MASK Alert Mask for the SMBALERT2 Pin N/A 1 R/W 37
03 CLEAR_FAULTS Clears All Faults N/A 0 W 35
7A STATUS_VOUT Alert Bits Related to the Primary Bus 00 1 R/W 35
7B STATUS_IOUT Alert Bit Related to the Primary Shunt 00 1 R/W 35
7D STATUS_TEMPERATURE Alert Bit Related to Temperature 00 1 R/W 35
7E STATUS_CML Alert Bits Related to Communication Errors 00 1 R/W 36
78 STATUS_BYTE Alert Bits Related to Temperature and Device Status 00 1 R/W 36
79 STATUS_WORD Alert Bits Related to all Primary Inputs 0000 2 R/W 36
VOLTAGE MARGIN -- DAC OUT (20 Pin QFN)
E4 CONFIG VOL MARGIN Configures the Margin DAC 00 1 R/W 37
E3 SET VOL MARGIN Value to Load the Margin DAC 80 1 R/W 37
EXTERNAL CLOCK CONTROL (16 Pin WLCSP)
E5 CONFIG_EXT_CLK Configures External Clock; Enable/Disable SMBALERT2 00 1 R/W 37
TABLE 2. ISL28025 REGISTER DESCRIPTIONS (Continued)
REGISTER
ADDRESS
(HEX) REGISTER NAME FUNCTION
POWER ON RESET
VALUE (HEX)
NUMBER
OF BYTES
ACCESS
TYPE PAGE
ISL28025
FN8388 Rev.5.00 Page 25 of 52
Nov 9, 2017
Communication Protocol
The DPM chip communicates with the host using PMBus
commands. PMBus command structure is an industry SMBus
standard for communicating with power supplies and converters.
All communications to and from the chip use the SMBCLK and
SMBDAT to communicate to the DPM master. The SMB pins
require a pull-up resistor to enable proper operation. The default
logic state of the communication pins are high when the bus is in
an idle state.
The SMBus standard is a variant of the I2C communication
standard with minor differences with timing and DC parameters.
SMBus supports Packet Error Corrections (PEC) for data integrity
certainty. The PMBus is the standardization of the SMBus
register designation. The standardization is specific to power and
converter devices.
The DPM employs the following command structures from the
I2C communication standard.
1. Send Byte
2. Write Byte/Word
3. Read Byte/Word
4. Read Block
5. Write Block
Packet Error Correction (PEC)
PEC is often used in environments where data being transferred
to and from the device can be compromised. Applications where
the device is connected by way of a cable is common use of PEC.
The cable’s integrity may be compromised resulting in error
transactions between the master and the device. The ISL28025
uses an 8-bit cyclic redundance check (CRC-8). Figure 63 shows
an example of a flow algorithm for CRC-8 protocol. FIGURE 63. ALGORITHM TO CALCULATE A CRC8 (PEC) BYTE VALUE
Public Function crc8Decode(binStr As String) As Byte
Dim crc8(0 To 7) As Byte, index As Byte, doInvert As Byte
The input to the subroutine is a binary string consisting of
the slave address, the register address and data inputted to or received from the part.
Anything inputted into or received from the device is part of the binary string (binStr)
to be calculated by this routine.
Clear the crc8 variable. This variable is used to return the PEC value.
For index = 0 To UBound(crc8)
crc8(index) = 0
Next index
index = 0
While index <> (Len(binStr))
index = index + 1
The If statement below reads the binary value of each bit in the binary string (binStr).
If Mid(binStr, index, 1) = "1" Then
doInvert = 1 Xor crc8(7)
Else
doInvert = 0 Xor crc8(7)
End If
crc8(7) = crc8(6)
crc8(6) = crc8(5)
crc8(5) = crc8(4)
crc8(4) = crc8(3)
crc8(3) = crc8(2)
crc8(2) = crc8(1) Xor doInvert
crc8(1) = crc8(0) Xor doInvert
crc8(0) = doInvert
Wend
crc8Decode = 0
For index = 0 To 7 'This assembles the crc8 value in byte form.
crc8Decode = crc8(index) * 2 ^ index + crc8Decode
Next index ‘crc8Decode is returned from this routine.
End Function
ISL28025
FN8388 Rev.5.00 Page 26 of 52
Nov 9, 2017
IC Device Details
0X19 CAPABILITY (R)
The capability register is a read only byte register that describes
the supporting communication standard by the DPM chip.
The DPM chip supports Packet Error Correction (PEC) protocol.
The maximum PMBus bus speed that the DPM supports is
400kHz. The DPM supports a higher speed option that is not
compliant to the PMBus standard. The higher speed option is
discussed later in the datasheet. The DPM chip has SMB alert
pins, which supports SMB alert commands.
0X20 VOUT MODE (R)
The VOUT Mode register is a readable byte register that describes
the method to calculate read back values from the DPM such as
voltage, current, power and temperature. The value for the
register is 0x40. The register value represents a direct data read
back format. For unsigned registers such as VBUS, the register
value is calculated using Equation 1.
Otherwise, Equation 2 is used for signed readings.
where n is the bit position within the register value. Bit_Val is the
value of the bit either 1 or 0.
0X99 PMBUS REV (R)
The PMBUS Rev register is a readable byte register that describes
the PMBUS revision that the DPM is compliant to.
PMBUS Rev part 1 is a PMBus specification pertaining to
electrical transactions and hardware interface. PMBUS Rev
part 2 specification pertains to the command calls used to
address the DPM.
A nibble of 0000 translates to revision 1.0 of either PMBUS
revision. A nibble of 0001 equals 1.1 of either PMBus revision.
0XAD IC DEVICE ID (BR)
The IC Device ID is a block readable register that reports the
device product name being addressed. The product ID that is
stored in the register is “ISL28025”. Each character is stored as
an ASCII number. A 0x30 equals ASCII “0”. A 0x49 translates to
an ASCII “I”. Figure 65 illustrates the convention for performing a
block read.
0XAE IC_DEVICE_REV (BR)
The IC Device Revision is a block readable register that reports
back the revision number of the silicon and the version of the
silicon. The register is three bytes in length.
TABLE 3. 0x19 CAPABILITY REGISTER DEFINITION
BIT
NUMBER D7 D[6:5] D4 D[3:0]
Bit Name PEC Max Bus Speed SMB Alert
Support
N/A
Default
Value
1 01 1 0000
(EQ. 1)
Register Value
0
15
n
Bit_Val
n2n
(EQ. 2)
Register Value
0
14
n
Bit_Val
n2n
Bit_Val
15 215
TABLE 4. 0x99 PMBUS REV REGISTER DEFINITION
BIT
NUMBER D[7:4] D[3:0]
Bit Name PMBUS Rev Part I PMBUS Rev Part II
Default
Value
0010 0010
TABLE 5. 0xAE IC DEVICE REV REGISTER DEFINITION
BIT NUMBER D[23:12] D[11] D[10:0]
Bit Name N/A Silicon Version Silicon Revision
Default Value 0000 0011 0000 0 0000 0000 0010
ISL28025
FN8388 Rev.5.00 Page 27 of 52
Nov 9, 2017
SILICON VERSION D[11]
Data Bit 11 of the IC Revision register reports the version of the
silicon.
Global IC Controls
0X12 RESET DEFAULT ALL (S)
The Restore Default All register is a send byte command that
restores all registers to the default state defined in Table 2 on
page 23.
0X01 OPERATION (R/W)
The Operation register is a read/write byte register that controls
the overall power-up state of the chip. Data Bit 7 of the register
configures the power status of chip. The power status is defined
in Table 7. Yellow shading in the table is the default setting of the
bit at power-up.
Primary and Auxiliary Channel Controls
0XD2 SET DPM MODE (R/W)
The Set DPM Mode is a read/write byte register that controls the
data acquisition behavior of the chip.
ADC ENABLE D[6]
Data Bit 6 of the Set DPM Mode register controls the ADC power
state within the DPM chip. At power-up, the ADC is powered up
and is available to take data.
ADC STATE D[5]
Data Bit 5 of the Set DPM Mode register controls the ADC state.
The idle state of the ADC does not acquire data from any input of
the DPM. Normal operating mode has the ADC acquiring data in
a systematic way.
POST TRIGGER STATE D[4]
Data Bit 4 of the Set DPM Mode register controls the post ADC
state once an acquisition has been made in the trigger mode.
ADC MODE TYPE D[3]
Data Bit 3 of the Set DPM Mode register controls the behavior of
the ADC to either triggered or continuous. The continuous mode
has the ADC continuously acquiring data in a systematic manner
described by data bits [2:0] in the SET DPM MODE register. The
triggered mode instructs the ADC to make an acquisition
described by data bits [2:0]. The beginning of a triggered cycle
starts once writing to the Set DPM Mode register commences.
The trigger mode is useful for reading a single measurement per
acquisition cycle.
TABLE 6. D[11] SILICON VERSION BIT DEFINED
D4 STATUS
0 60V
112V
TABLE 7. 0x01 OPERATION REGISTER BIT 7 DEFINED
D7 STATUS
0 Power-Down
1Normal Operation
TABLE 8. 0xD2 SET DPM MODE REGISTER DEFINITION
BIT
NUMBER D[7] D6 D[5] D[4] D[3] D[2:0]
Bit Name N/A ADC
Enable
ADC
State
Post
Trigger
State
ADC
Mode
Type
Operating
Mode
Default
Value
0000 1010
TABLE 9. 0xD2 SET DPM MODE REGISTER BIT 6 DEFINED
D6 ADC PD
0Normal Mode
1ADC Powered Down
TABLE 10. 0xD2 SET DPM MODE REGISTER BIT 5 DEFINED
D5 ADC STATE
0Normal State
1ADC in Idle State
TABLE 11. 0xD2 SET DPM MODE REGISTER BIT 4 DEFINED
D4 ADC TRIGGER STATE
0Idle Mode after a Trigger Measurement
1PD Mode after a Trigger Measurement
TABLE 12. 0xD2 SET DPM MODE REGISTER BIT 3 DEFINED
D3 ADC MODE TYPE
0 Trigger
1Continuous
ISL28025
FN8388 Rev.5.00 Page 28 of 52
Nov 9, 2017
OPERATING MODE D[2:0]
The Operating Mode bits of the Set DPM Mode register control
the state machine within the chip. The state machine globally
controls the overall functionality of the chip. Table 13 shows the
various measurement states the chip can be configured to, as
well as the mode bit definitions to achieve a desired
measurement state. The shaded row is the default setting upon
power-up.
0XD3 DPM CONVERSION STATUS (R)
The DPM conversion status register is a readable byte register
that reports the status of a conversion when the DPM is
programmed in the trigger mode.
CNVR: CONVERSION READY D[1]
The Conversion Ready bit indicates when the ADC has finished a
conversion and has transferred the reading(s) to the appropriate
register(s). The CNVR is operable only when the ADC state is set
to trigger. The CNVR is in a low state when the conversion is in
progress. When the CNVR bit transitions from a low state to a
high state and remains at a high state, the conversion is
complete. The CNVR initializes or reinitializes when writing to the
Set DPM Mode register.
OVF: MATH OVERFLOW FLAG D[0]
The Math Overflow Flag (OVF) bit is set to indicate the current and
power data being read from the DPM is overranged and
meaningless.
0XD4 CONFIGURE ICHANNEL (R/W)
The Configure ICHANNEL register is a read/write word register
that configures the ADC measurement acquisition settings for
the primary and auxiliary voltage shunt inputs.
SHUNT VOLTAGE CONVERSION TIME D[2:0]
The Shunt Voltage Conversion Time bits set the acquisition speed
of the ADC when measuring the primary voltage shunt channel of
the DPM. The primary voltage shunt channel has independent
timing control bits allowing for the primary voltage shunt channel
to have a unique acquisition time with the respect to other
channels within the DPM. Table 16 is a list of the selectable
voltage shunt ADC time settings. The shaded row indicates the
default setting.
TABLE 13. 0xD2 SET DPM MODE REGISTER BITS 2 TO 0 DEFINED
D[2:0] MEASUREMENT INPUT
0Primary Channel Shunt Voltage
1Primary Channel VBUS Voltage
2Primary Shunt and VBUS Voltages
3Do Not Select
4Auxiliary Channel VBUS Voltage
5Do Not Select
6Internal Temperature
7All
TABLE 14. 0xD3 DPM CONVERSION STATUS REGISTER DEFINITION
BIT NUMBER D[7:2] D[1] D[0]
Bit Name N/A CNVR OVF
Default
Value
000
TABLE 15. 0xD4 CONFIGURE ICHANNEL REGISTER DEFINITION
BIT
NUMBER D[15:7] D[13:10] D[9:7] D[6:3] D[2:0]
Bit
Name
N/A N/A N/A Primary
Shunt
Sample
AVG
Primary
Shunt
Conversion
Time
Default
Value
00 00 00 11 1 000 0 111
TABLE 16. PRIMARY VSHUNT CONVERSION TIMES DEFINED
Config_Ichannel: D[2:0] CONVERSION TIME
0 0 0 64µs
0 0 1 128µs
0 1 0 256µs
0 1 1 512µs
10X 1.024ms
1 1 X 2.048ms
ISL28025
FN8388 Rev.5.00 Page 29 of 52
Nov 9, 2017
SHUNT VOLTAGE SAMPLE AVERAGE D[6:3]
The Shunt Voltage Sample Average bits set the number of
averaging samples for a unique sampling time. The DPM records
all samples and outputs the average resultant to the voltage
shunt register. Table 17 defines the list of selectable averages
the DPM can be set to. The shaded row indicates the default
setting.
0X38 IOUT CALIBRATION GAIN (R/W)
The IOUT Calibration Gain register is a read/write word register
that is used to calculate current and power measurements for
the primary channel of the DPM. When the register is
programmed, the DPM calculates the current and power based
on the primary channels VBUS and VSHUNT measurements. The
calculation resultant is stored in the READ_IOUT and READ_POUT
registers.
The calibration register value can be calculated as follows:
1. Calculate the full-scale current range that is desired. This can
be calculated using Equation 3.
Rshunt is the value of the shunt resistor. VshuntFS is the full
scale range of the primary channel, which equals 80mV.
2. From the current full-scale range, the current LSB can be
calculated using Equation 4. Current full-scale is the outcome
from Equation 3.
ADCres is the resolution of shunt voltage reading. The output
of the ADC is a signed 15 bit binary number. Therefore, the
ADCres value equals 215 or 32768.
From Equation 4, the calibration resistor value can be calculated
using Equation 5. The resolution of the math that is processed
internally in the DPM is 2048 or 11 bits of resolution. The VSHUNT
LSB is set to 2.5µV. Equation 5 yields a 15-bit binary number that
can be written to the calibration register. The calibration register
format is represented in Table 18.
0XD5 CONFIGURE VCHANNEL (R/W)
The Configure VCHANNEL register is a read/write word register
that configures the ADC measurement acquisition settings for
the primary and auxiliary voltage bus inputs.
The ADC configuration of the sampling average and conversion
time settings for VBUS and AuxV channels have the same setting
choices as the VSHUNT primary and auxiliary channels.
0XD7 CONFIGURE PEAK DETECTOR (R/W)
The Configure Peak Detector register is a read/write byte register
that toggles the minimum and maximum current tracking
feature. A Peak Detect Enable bit setting of 1 enables the current
peak detect feature of the DPM. The feature is discussed in more
detail in the “0xD8 Read Peak Min IOUT (R) 0xD9 Read Peak Max
Iout (R)” section.
TABLE 17. PRIMARY VSHUNT NUMBER OF SAMPLES TO AVERAGE
DEFINED
AVG[3:0] CONVERTER AVERAGES
0 0 0 0 1
0 0 0 1 2
0 0 1 0 4
0 0 1 1 8
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 512
1 0 1 0 1024
1 0 1 1 2048
1 1 X X 4096
(EQ. 3)
Current FS
Vshunt FS
Rshunt
(EQ. 4)
Current LSB
Current FS
ADC res
TABLE 18. 0x38 IOUT_CAL_GAIN DEFINITION
BIT
NUMBER D[15] D[14:0]
Bit Name N/A IOUT_CAL_GAIN
Default
Value
0 000 0000 0000 0000
TABLE 19. 0xD5 CONFIGURE VCHANNEL REGISTER DEFINITION
BIT
NUMBER D[15:14] D[13:10] D[9:7] D[6:3] D[2:0]
Bit Name N/A AuxV
Sample
AVG
AuxV
Conversion
Time
VBUS
Sample
AVG
VBUS
Conversion
Time
Default
Value
00 00 00 11 1 000 0 111
TABLE 20. 0xD7 CONFIGURE PEAK DETECTOR REGISTER DEFINITION
BIT NUMBER D[7:1] D[0]
Bit Name N/A Peak Detect Enable
Default
Value
0000 000 0
(EQ. 5)
CalRegval integer
Math res VshuntLSB
CurrentLSB Rshunt

CalRegval integer 0.00512
CurrentLSB Rshunt

ISL28025
FN8388 Rev.5.00 Page 30 of 52
Nov 9, 2017
Measurement Registers
0XD6 READ VSHUNT OUT (R)
The Read VSHUNT Out register is a readable word register that
stores the signed measured digital value of the primary VSHUNT
input of the DPM. Using Equation 2 to calculate the integer value
of the register, Equation 6 calculates the floating point measured
value for the primary VSHUNT channel.
VSHUNT(LSB) is the numerical weight of each level for the VSHUNT
channel, which equals 2.5µV.
0X8B READ VOUT (R)
The Read VOUT register is a readable word register that stores the
unsigned measured digital value of the primary VBUS input of the
DPM. Using Equation 1 to calculate the integer value of the
register, Equation 7 calculates the floating point measured value
for the primary VBUS channel.
VBUS(LSB) is the numerical weight of each level for the VBUS
channel. The VBUS(LSB) equals 1mV for the 60V version of the
DPM and 250µV for the 12V version of the DPM.
0X8C READ IOUT (R)
The Read IOUT register is a readable word register that stores the
signed measured digital value of the current passing through the
primary channel’s shunt. The register uses the measured value
from VSHUNT and the IOUT_CAL_GAIN register. Equation 8 yields
the current for the primary channel.
The Registervalue is calculated using Equation 2. The CurrentLSB
is calculated using Equation 4.
0XD8 READ PEAK MIN IOUT (R)
0XD9 READ PEAK MAX IOUT (R)
The Read Peak Min/Max IOUT registers are readable word
registers that store the minimum and maximum current value of
an averaging cycle for the current passing through the primary
shunt.
The min/max current tracking is enabled by setting the Peak
Detect Enable bit in the CONFIG_PEAK_DET (0xD7) register. The
current peak detect feature only works for the current register.
At the conclusion of each primary channel current, the DPM will
record and store the minimum and maximum values of the
current measured. The feature operates for both the trigger and
continuous modes. Disabling the Peak Detector Enable bit will
turn off the feature as well as clear the Read Peak Min/Max IOUT
registers.
0X96 READ POUT (R)
The Read POUT register is a signed readable word register that
reports the digital value of the power from the primary channel.
The register uses the values from READ_IOUT and
READ_VSHUNT_OUT registers to calculate the power.
The units for the power register are in watts. The power can be
calculated using Equation 9.
The Registervalue is calculated using Equation 2 on page 26. The
PowerLSB can be calculated from Equation 10.
The VBUS(LSB) equals 1mV for the 60V version of the DPM and
250µV for the 12V version of the DPM. The CurrentLSB is the
value yielded from Equation 4.
0XE1 READ VOUT AUX (R)
The Read VOUT Aux register is a readable word register that
stores the unsigned measured digital value of the auxiliary VBUS
input of the DPM. Using Equation 1 on page 26 to calculate the
integer value of the register, Equation 11 calculates the floating
point measured value for the auxiliary VBUS channel.
VBUS(LSB) is the numerical weight of each level for the auxiliary
VBUS channel. The auxiliary VBUS(LSB) equals 100µV. The voltage
range for the auxiliary VBUS is 0 to VCC.
0X8D READ TEMPERATURE (R)
The Read Temperature register is a readable word register that
reports out the internal temperature of the chip. The register is a
16-bit signed register. Bit 15 of the register is the signed bit. The
register value can be calculated using Equation 12.
n is the bit position within the register value. Bit_Val is the value
of the bit either 1 or 0. The register value multiplied by 0.016
yields the internal temperature reading in degrees Celsius (°C).
FIGURE 66. THE ISL28025 TRACKS MINIMUM AND MAXIMUM
AVERAGE CURRENT READINGS
(EQ. 6)
VSHUNT Registervalue VSHUNT LSB
=
(EQ. 7)
VBUS Registervalue VBUS LSB
=
(EQ. 8)
Current Registervalue CurrentLSB
=
(EQ. 9)
Power Registervalue PowerLSB 40000=
(EQ. 10)
PowerLSB CurrentLSB VBUS LSB
=
(EQ. 11)
VBUS Registervalue VBUS LSB
=
(EQ. 12)
Register Value
0
14
n
Bit_Val
n2n
Bit_Val
15 215
ISL28025
FN8388 Rev.5.00 Page 31 of 52
Nov 9, 2017
Threshold Detectors
The DPM has three integrated comparators that allow for real
time fault detection of overvoltage, undervoltage for the primary
VBUS input, and overcurrent detection for the primary VSHUNT
input. An over-temperature detection is available by multiplexing
the input to the overvoltage comparator.
0XDA VOUT OV THRESHOLD SET (R/W)
The VOUT OV Threshold Set register is a read/write word register
that controls the threshold voltage level to the overvoltage
comparator. The description of the functionality within this
register is found in Table 21.
The compared reference voltage level to the OV comparator is
generated from a 6-bit DAC. The 6-bit DAC has four or six voltage
ranges to improve detection voltage resolution for a specific
voltage range.
OV_OT_SEL D[9]
The OV_OT_SEL bit configures the multiplexer to the input of the
OV comparator to compare for over-temperature or overvoltage.
Setting the OV_OT_SEL to a 1 configures the OV comparator to
detect an over-temperature condition.
VBUS_THRES_RNG D[8:6]
The Vbus_Thres_Rng bits set the threshold voltage range for the
overvoltage and undervoltage DACs. There are six selectable
ranges for the 60V version of the DPM. Only four selectable
ranges for the 12V version of the DPM. Table 22 defines the
range settings for the VBUS threshold detector. The yellow shaded
row denotes the default setting.
The temperature threshold reference level has one range setting,
which equals +125°C at full scale.
VBUS_OV_OT_SET D[5:0]
The Vbus_OV_OT_Set bits control the voltage/temperature level
to the input of the OV comparator. The LSB of the DAC is 1.56%
of the full-scale range chosen using the Vbus_Thres_Rng bits. For
the temperature feature, the LSB for the temperature level is
5.71°C. The mathematical range is -144°C to +221.4°C.
The overvoltage range starts at 25% of the full-scale range
chosen using the Vbus_Thres_Rng bits and ends at 125% of the
chosen full-scale range. The same range applies to the
temperature measurements.
Table 23 defines an abbreviated breakdown to set the OV/OT
comparator level. The shaded row is the default condition.
0XDB VOUT UV THRESHOLD SET (R/W)
The VOUT UV Threshold Set register is a read/write byte register
that controls the threshold voltage level to the undervoltage
comparator. The description of the functionality within this
register is found in Table 24.
The compared reference voltage level to the UV comparator is
generated from a 6-bit DAC. The 6-bit DAC has 4 to 6 voltage
FIGURE 67. SIMPLIFIED BLOCK DIAGRAM OF THE THRESHOLD
FUNCTIONS WITHIN THE DPM
TABLE 21. 0xDA VOUT OV THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER D[15:10] D[9] D[8:6] D[5:0]
Bit Name N/A OV_OT
SEL
Vbus_Thres_Rng Vbus_OV_OT_Set
Default
Value
0000 00 0 0 00 11 1111
TABLE 22. Vbus_Thres_Rng BITS DEFINED
Vbus_Thres_Rng: D[8:6]
Vbus_12V
(RANGE)
Vbus_60V
(RANGE)
0 0 0 12 48
001 624
010 312
0111.255
1 0 0 X 3.3
1 0 1 X 2.5
TABLE 23. Vbus_OV_OT_Set BITS DEFINED
Vbus_OV_OT_Set: D[5:0]
OV THRESHOLD
VALUE
OT THRESHOLD
VALUE
00 0000 25% of FS -144
00 0001 (25 + 1.56)% of FS -138.3
00 0010 (25 + 3.12)% of FS -132.6
............... .................... ....................
11 1101 (125 to 4.68)% of FS 210
11 1110 (125 to 3.12)% of FS 215.7
11 1111 (125 to 1.56)% of FS 221.4
ISL28025
FN8388 Rev.5.00 Page 32 of 52
Nov 9, 2017
ranges that are determined by the Vbus_Thres_Rng bits in the
VOUT OV Threshold Set register.
VBUS_UV_SET D[4:0]
The Vbus_UV_Set bits control the undervoltage level to the input
of the UV comparator. The LSB of the DAC is 1.56% of the
full-scale range chosen using the Vbus_Thres_Rng bits.
The undervoltage ranges from 0% to 100% of the full-scale range
set by the Vbus_Thres_Rng bits.
Table 25 defines an abbreviated breakdown to set the
undervoltage comparator levels. The shaded row is the default
condition.
0XDC IOUT OC THRESHOLD SET (R/W)
The IOUT OC Threshold Set register is a read/write word register
that controls the threshold current level to the overcurrent
comparator. The description of the functionality within this
register is found in Table 26.
The overcurrent threshold is defined through the VSHUNT reading.
The product of the current through the shunt resistor defines the
VSHUNT voltage to the DPM. The current through the shunt
resistor is directly proportional the VSHUNT voltage measured by
the DPM. An overvoltage threshold for VSHUNT is the same as an
overcurrent threshold.
IOUT_ DIR D[9]
The Iout_Dir bit controls the polarity of the VSHUNT voltage
threshold. The bit functionality allows an overcurrent threshold to
be set for currents flowing from VINP to VINM and the reverse
direction. Table 27 defines the range settings for the VBUS
threshold detector. The yellow shaded row denotes the default
setting.
VSHUNT_THRES_RNG D[6]
The Vshunt_Thres_Rng bit sets the overvoltage threshold range
for the overcurrent DAC. The selectable VSHUNT range improves
the overvoltage threshold resolution for lower full-scale current
applications. Table 28 defines the range settings for the VBUS
threshold detector. The yellow shaded row denotes the default
setting.
VSHUNT_OC_SET D[5:0]
The Vshunt_OC_Set bits control the VSHUNT voltage level to the
input of the OC comparator. The LSB of the DAC is 1.56% of the
full-scale range chosen using the Vshunt_Thres_Rng bits.
The overvoltage range starts at 25% of the full-scale range
chosen using Vbus_Thres_Rng bits and ends at 125% of the
chosen full-scale range.
SMB Alert
The DPM has two alert pins (SMBALERT1, SMBALERT2) to alert
the peripheral circuitry that a failed event has occurred.
SMBALERT1 output is an open drain allowing the user the
flexibility to connect the alert pin to other components requiring
different logic voltage levels than the DPM. The SMBALERT2 has
a push/pull output stage for driving pins with logic voltage levels
TABLE 24. 0xDB VOUT UV THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER D[7:6] D[5:0]
Bit Name N/A Vbus_UV_Set
Default
Value
00 00 0000
TABLE 25. Vbus_UV_Set BITS DEFINED
Vbus_UV_Set: D[5:0] UV THRESHOLD VALUE
00 0000 0%
00 0001 1.56% of FS
00 0010 3.12% of FS
............... ....................
11 1101 (100 to 4.68)% of FS
11 1110 (100 to 3.12)% of FS
11 1111 (100 to 1.56)% of FS
TABLE 26. 0xDC IOUT OC THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER D[15:10] D[9] D[8:7] D[6] D[5:0]
Bit Name N/A Iout_Dir N/A Vshunt
Thres
Rng
Vshunt_OC_Set
Default
Value
0000 00 0 0 0 0 11 1111
TABLE 27. Vbus_Thres_Rng BITS DEFINED
Iout_Dir: D[9]
CURRENT
DIRECTION
0VINP to VINM
1VINM to VINP
TABLE 28. Vshunt_Thres_Rng BIT DEFINED
Vshunt_Thres_Rng: D[6]
VSHUNT
(RANGE)
080mV
1 40mV
TABLE 29. Vshunt_OC_Set BITS DEFINED
Vshunt_OC_Set: D[5:0] OC THRESHOLD VALUE
00 0000 25% of FS
00 0001 (25 + 1.56)% of FS
00 0010 (25 + 3.12)% of FS
............... ....................
11 1101 (125 to 4.68)% of FS
11 1110 (125 to 3.12)% of FS
11 1111 (125 to 1.56)% of FS
ISL28025
FN8388 Rev.5.00 Page 33 of 52
Nov 9, 2017
equal to the voltage applied to the I2CVCC pin. The push/pull
output is useful for driving peripheral components that require
the DPM to source and sink a current. The alert pins are
commonly connected to an interrupt pin of a microcontroller or
an enable pin of a device.
The SMBALERT registers control the functionality of the
SMBALERT pins. The threshold comparators are the inputs to the
SMBALERT registers. The output are the SMBALERT pins.
Figure 68 is a simple functional block diagram of the SMB Alert
features.
FIGURE 68. SIMPLIFIED BLOCK DIAGRAM OF THE SMBALERT FUNCTIONS WITHIN THE DPM
ISL28025
FN8388 Rev.5.00 Page 34 of 52
Nov 9, 2017
0XDD CONFIGURE INTERRUPTS (R/W)
The Configure Interrupt register is a read/write word register that
controls the behavior of the two SMBALERT pins. The definition
of the control bits within the Configure Interrupt register is
defined in Table 30.
ALERT2_FEEDTHR D[14:12]
The Alert2_FeedThr bits determine whether the bit from each
alert comparator is digitally conditioned or not. The alert
comparators, digital filters and latching bits are the same for
both SMBALERT channels. Table 31 defines the functionality of
the Alert2_FeedThr bits.
ALERT1_FEEDTHR D[11:9]
The Alert1_FeedThr bits determine whether the bit from each
alert comparator is digitally conditioned or not. The alert
comparators, digital filters and latching bits are the same for
both SMB alert channels. Table 32 defines the functionality of
the Alert1_FeedThr bits.
OC_FIL D[8:7]
The OC_FIL bits control the digital filter for the overcurrent
circuitry. The digital filter will prevent short duration events from
passing to the output pins. The filter is useful in preventing high
frequency power glitches from triggering a shutdown event. The
filter time delay ranges from 0µs to 8µs. An 8µs filter setting
requires an error event to be at least 8µs in duration before
passing the result to the SMBALERT pins. There is one OC digital
filter for both SMBALERT pins. Configuring OC_FIL bits will
change the OC digital filter setting for both SMBALERT pins. See
Table 33 for the filter selections.
UV_FIL D[6:5]
The UV_FIL bits control the digital filter for the undervoltage
circuitry. The digital filter will prevent short duration events from
passing to the output pins. The filter is useful in preventing high
frequency power glitches from triggering a shutdown event. The
filter time delay ranges from 0µs to 8µs. An 8µs filter setting
requires an error event to be at least 8µs in duration before
passing the result to the SMBALERT pins. There is one UV digital
filter for both SMBALERT pins. Configuring UV_FIL bits will
change the UV digital filter setting for both SMBALERT pins. See
Table 33 for the filter selections.
OV_FIL D[4:3]:
The OV_FIL bits control the digital filter for the overvoltage
circuitry. The digital filter will prevent short duration events from
passing to the output pins. The filter is useful in preventing high
frequency power glitches from triggering a shutdown event. The
filter time delay ranges from 0µs to 8µs. An 8µs filter setting
requires an error event to be at least 8µs in duration before
passing the result to the SMBAlert pins. There is one OV digital
filter for both SMB alert pins. Configuring OV_FIL bits will change
the OV digital filter setting for both SMB alert pins. See Table 33
for the filter selections.
OC_EN D[2]
The OC_EN enable bit controls the power to the overcurrent DAC
and comparator. Setting the bit to 1 enables the overcurrent
circuitry.
OV_EN D[1]
The OV_EN enable bit controls the power to the overvoltage DAC
and comparator. Setting the bit to 1 enables the overvoltage
circuitry.
UV_EN D[0]
The UV_EN enable bit controls the power to the undervoltage DAC
and comparator. Setting the bit to 1 enables the undervoltage
circuitry.
TABLE 30. 0xDD CONFIGURE INTERRUPT REGISTER DEFINITION
BIT
NUMBER
D
[15]
D
[14:12]
D
[11:9]
D
[8:7]
D
[6:5]
D
[4:3]
D
[2]
D
[1]
D
[0]
Bit Name N/A ALERT2
FeedTh
ALERT1
FeedTh
OC
FIL
OV
FIL
UV
FIL
OC
EN
OV
EN
UV
EN
Default
Value
0 000 000 0 0 00 0 0 0 0 0
TABLE 31. Alert2_FeedThr BITS DEFINED
Alert2_FeedThr Bits
D[14:12] BIT VALUE FUNCTIONALITY
D[14] 0 0 OV/OT Digitally Conditioned
1OV/OT Pass Through
D[13] 1 0 UV Digitally Conditioned
1UV Pass Through
D[13] 2 0 OC Digitally Conditioned
1OC Pass Through
TABLE 32. Alert1_FeedThr BITS DEFINED
Alert1_FeedThr Bits
D[11:9] BIT VALUE FUNCTIONALITY
D[11] 0 0 OV/OT Digitally Conditioned
1OV/OT Pass Through
D[10] 1 0 UV Digitally Conditioned
1UV Pass Through
D[9] 2 0 OC Digitally Conditioned
1OC Pass Through
TABLE 33. DIGITAL GLITCH FILTER SETTINGS DEFINED
OC_FIL D[8:7]
UV_FIL D[6:5]
OV_FIL D[4:3]
FILTER TIME
(µs)
0 0 0
01 2
10 4
11 8
ISL28025
FN8388 Rev.5.00 Page 35 of 52
Nov 9, 2017
0XDE FORCE FEED-THROUGH ALERT REGISTER (R/W)
The Force Feed-through Alert Register is a read/write byte
register that controls the polarity of the interrupt. The definition
of the control bits within the Force Feed-through Alert register is
defined in Table 34.
A2POL D[3], A2POL D[2]
The AxPOL bits control the polarity of an interrupt. A2POL bit
defines the SMBALERT2 pin active interrupt state. A1POL bit
defines the SMBALERT1 pin active interrupt state. Table 35
defines the functionality of the bit.
FORCEA2 D[1], FORCEA1 D[0]
The FORCEAx bits allow the user to force an interrupt by setting
the bit. FORCEA2 bit controls the SMBALERT2 pin state.
FORCEA1 bit controls the SMBALERT1 pin state. Table 36 defines
the functionality of the bit.
0X03 CLEAR FAULTS (S)
The Clear Faults register is a send byte command that clears all
faults pertaining to the status registers. Upon execution of the
command, the status registers returns to the default state
defined in Table 2 on page 23.
0X7A STATUS VOUT (R/W)
The Status VOUT register is a read/write byte register that reports
over and undervoltage warnings for the VBUS input.
VOUT OV WARNING D[6]
The VOUT OV Warning bit is set to 1 when an overvoltage fault
occurs on the VBUS input. The VBUS overvoltage threshold is set
from the VOUT OV Threshold Set register. In the event of a VBUS
overvoltage condition, the VOUT OV Warning is latched to 1.
Writing a 1 to the VOUT OV Warning bit will clear the warning
resulting in a bit value equal to 0.
VOUT UV WARNING D[5]
The VOUT UV Warning bit is set to 1 when an undervoltage fault
occurs on the VBUS input. The VBUS undervoltage threshold is set
from the VOUT UV Threshold Set register. In the event of a VBUS
undervoltage condition, the VOUT UV Warning is latched to 1.
Writing a 1 to the VOUT UV Warning bit will clear the warning
resulting in a bit value equal to 0.
0X7B STATUS IOUT (R/W)
The Status IOUT register is a read/write byte register that reports
an overcurrent warning for the VSHUNT input.
IOUT OC WARNING D[5]
The IOUT OC Warning bit is set to 1 when an overcurrent fault
occurs on the VSHUNT input. The VSHUNT overcurrent threshold is
set from the IOUT OC Threshold Set register. In the event of a
VSHUNT overcurrent condition, the IOUT OC Warning is latched
to 1. Writing a 1 to the IOUT OC Warning bit will clear the warning
resulting in a bit value equal to 0.
0X7D STATUS TEMPERATURE (R/W)
The Status Temperature register is a read/write byte register that
reports an over-temperature warning initiated from the internal
temperature sensor.
TABLE 34. 0xDE FORCE FEED-THROUGH ALERT REGISTER DEFINITION
BIT
NUMBER D[7:4] D[3] D[2] D[1] D[0]
Bit Name N/A A2POL A1POL FORCE A2 FORCE A1
Default
Value
0000 0 0 0 0
TABLE 35. AxPol BIT DEFINED
A2POL D[3], A1POL D[2]
INTERRUPT
ACTIVE STATE
0low
1high
TABLE 36. FORCEAx BIT DEFINED
FORCEA2 D[1], FORCEA1 D[0]
INTERRUPT
STATUS
0Normal
1 Interrupt Forced
TABLE 37. 0x7A STATUS VOUT REGISTER DEFINITION
BIT NUMBER D[7] D[6] D[5] D[4:0]
Bit Name N/A VOUT OV
Warning
VOUT UV
Warning
N/A
Default
Value
0 0 0 0 0000
TABLE 38. 0x7B STATUS IOUT REGISTER DEFINITION
BIT NUMBER D[7] D[6] D[5] D[4:0]
Bit Name N/A N/A IOUT OC
Warning
N/A
Default
Value
0 0 0 0 0000
TABLE 39. 0x7D STATUS TEMPERATURE REGISTER DEFINITION
BIT NUMBER D[7] D[6] D[5] D[4:0]
Bit Name N/A OT
Warning
N/A N/A
Default
Value
0 0 0 0 0000
ISL28025
FN8388 Rev.5.00 Page 36 of 52
Nov 9, 2017
OT WARNING D[6]
The OT Warning bit is set to 1 when an over-temperature fault
occurs from the internal temperature sensor. The
over-temperature threshold is set from the VOUT OV Threshold
Set register. In the event of an over-temperature condition, the OT
Warning bit is latched to 1. Writing a 1 to the OT Warning bit will
clear the warning resulting in a bit value equal to 0.
0X7E STATUS CML (R/W)
The Status CML register is a read/write byte register that reports
warnings and errors associated with communications, logic, and
memory.
USCMD D[7]
The USCMD bit is set to 1 when an unsupported command is
received from the I2C master. Reading from an undefined
register is an example of an action that would set the USCMD bit.
The USCMD bit is a latched bit. Writing a 1 to the USCMD bit
clears the warning resulting in a bit value equal to 0.
USDATA D[6]
The USDATA bit is set to 1 when an unsupported data is received
from the I2C master. Writing a word to a byte register is an
example of an action that would set the USDATA bit. The USDATA
bit is a latched bit. Writing a 1 to the USDATA bit clears the
warning resulting in a bit value equal to 0.
PECERR D[5]
The PECERR bit is set to 1 when a Packet Error Check (PEC) event
has occurred. Writing the wrong PEC to the DPM is an example of
an action that would set the PECERR bit. The PECERR bit is a
latched bit. Writing a 1 to the PECERR bit clears the warning
resulting in a bit value equal to 0.
COMERR D[1]
The COMERR bit is set to 1 for communication errors that are not
handled by the USCMD, USDATA and PECERR errors. Reading
from a write only register is an example of an action that would
set the COMERR bit. The COMERR bit is a latched bit. Writing a 1
to the COMERR bit clears the warning resulting in a bit value
equal to 0.
0X78 STATUS BYTE (R/W)
The Status Byte register is a read/write byte register that is a
hierarchical register to the Status Temperature and Status CML
registers. The Status Byte registers bits are set if an
over-temperature or a CML error has occurred.
BUSY D[7]
The BUSY bit is set to 1 when the DPM is busy and unable to
respond. The BUSY bit is a latched bit. Writing a 1 to the BUSY bit
clears the warning resulting in a bit value equal to 0.
TEMPERATURE D[2]
The Temperature bit is set to 1 when an over-temperature fault
occurs from the internal temperature sensor. This bit is the same
action bit as the OT Warning bit in the Status Temperature
register. The over-temperature threshold is set from the VOUT OV
Threshold Set register. In the event of an over-temperature
condition, the Temperature bit is latched to 1. Writing a 1 to the
Temperature bit will clear the warning resulting in a bit value
equal to 0.
CML D[1]
The CML bit is set to 1 when any errors occur within the Status
CML register. There are four Status CML error bits that can set
the CML bit. The CML bit is a latched bit. Writing a 1 to the CML
bit clears the warning resulting in a bit value equal to 0.
0X79 STATUS WORD (R/W)
The Status Word register is a read/write word register that is a
hierarchical register to the Status VOUT, Status IOUT and Status
Byte registers. The Status Word registers bits are set when any
errors previously described occur. The register generically reports
all errors.
VOUT D[15]
The VOUT bit is set to 1 when any errors occur within the Status
VOUT register. Whether either or both an undervoltage or
overvoltage fault occurs, the VOUT bit will be set. The VOUT bit is a
latched bit. Writing a 1 to the VOUT bit clears the warning
resulting in a bit value equal to 0.
IOUT D[14]:
The IOUT bit is set to 1 when an overcurrent fault occurs. This bit
is the same action bit as the IOUT OC Warning bit in the Status
IOUT register. In the event of an overcurrent condition, the IOUT bit
is latched to 1. Writing a 1 to the IOUT bit will clear the warning
resulting in a bit value equal to 0.
TABLE 40. 0x7E STATUS CML REGISTER DEFINITION
BIT
NUMBER D[7] D[6] D[5] D[4:2] D[1] D[0]
Bit Name USCMD USDATA PECERR N/A COMERR N/A
Default
Value
0 0 0 0 00 0 0
TABLE 41. 0x78 STATUS BYTE REGISTER DEFINITION
BIT NUMBER D[7] D[6:3] D[2] D[1] D[0]
Bit Name BUSY N/A Temperature CML N/A
Default
Value
0 000 0 0 0 0
TABLE 42. 0x79 STATUS WORD REGISTER DEFINITION
BIT NUMBER D[15] D[14] D[13:8] D[7:0]
Bit Name VOUT IOUT N/A See Status Byte
Default
Value
0 0 00 0000 0000 0000
ISL28025
FN8388 Rev.5.00 Page 37 of 52
Nov 9, 2017
0X1B SMBALERT MASK (BR/BW)
0XDF SMBALERT2 MASK (BR/BW)
The SMBALERT registers are block read/write registers that
mask error conditions from electrically triggering the respective
SMBALERT pin.
The SMBALERT can mask bits of any of the status registers.
Masking lower level bits prevents the hierarchical bit from being
set. For example, a COMERR bit being masked will not set the
CML bit of the Status Byte register.
To mask a bit, the first data byte is the register address of the
bit(s) to be masked. The second and third data bytes are the
masking bits of the register. A masking bit of 1 prevents the
signal from triggering an interrupt.
All alert bits are masked as the default state for both the SMB
alert pins. The master needs to send instructions to unmask the
alert bits.
As an example, a user would like to allow the COMERR bit to
trigger a SMBALERT2 interrupt while masking the rest of the
alerts within the Status CML register. The command that is sent
from the master to the DPM is the slave address, SMBALERT2
register address, Status CML register address and the mask bit
value. In a hexadecimal format, the data sent to the DPM is as
follows; 0x80 DF 7E FD.
To read the mask status of any alert register, write a four byte
command, without PEC, consisting of the slave address of the
device, the SMB mask register address, the number of bytes to
be read back and the register address of the mask to be read.
Once the write command has commenced, a read command
consisting of the device slave address and the register address of
the SMB mask will return the mask of the desired alert register.
As an example, a user would like to read the status of the Status
Byte register. The first command sent to the DPM is in
hexadecimal bytes is 0x82 1B 01 78. The second command is a
standard read. The slave address is 0x83 (0x82 + read bit set)
and the register address is 0x1B.
SMBALERT1 RESPONSE ADDRESS
The SMBALERT1 pin of each ISL28025 device is commonly
shared to a single GPIO pin of the microcontroller. The
SMBALERT1 pin is an open drain allowing for multiple devices to
be OR’ed to a single GPIO pin.
The SMBALERT1 Response Address command reports the slave
address of the device that has triggered alert. The SMB Respond
Address command is shown in Figure 69.
The alert response address is 0x18. In the event of multiple
alerts pulling down the GPIO line, the alert respond command
will return the lowest slave address that is connected to the I2C
bus. Upon clearing the lowest slave address alert, the alert
command will return the lowest slave address of the remaining
alerts that are activated.
The alert response is operable when the interrupt active state is
forced low by the device at the SMBALERT1 pin. Changing
SMBALERT1 interrupt polarity or forcing an interrupt will enable
the alert response. By design the open drain of the SMBALERT1
pin allows for ANDing of the interrupt via a pull-up resistor. The
alert response command is valid for only the SMBALERT1 pin.
The alert response command will return a 0x19 when there are
no errors detected.
External Clock Control (16 Pin WLCSP)
The DPM has an external clock feature that allows the chip to be
synchronized to an external clock. The feature is useful in limiting
the number of clocks running asynchronously within a system.
0XE5 CONFIGURE EXTERNAL CLOCK (R/W)
The Configure External Clock register is a read/write byte register
that controls the functionality of the external clock feature.
EXTCLK_EN D[7]
The ExtClk_EN bit enables the external clock feature. The
ExtClk_En default bit setting is 0 or disabled. A bit setting of 1
disables the internal oscillator of the DPM and connects circuitry
such that the system clock is routed from the external clock pin.
SMBALERT2_OEN D[6]
The SMBALERT2_OEN bit within the Configure External Clock
register either enables or disables the buffer that drives the
SMBALERT2 pin.
EXTCLKDIV D[3:0]
The EXTCLKDIV bits control an internal clock divider that is useful
for fast system clocks. The internal clock frequency from pin to
chip is represented in Equation 13.
fEXTCLK is the frequency of the signal driven to the External Clock
pin. ClkDiv is the decimal value of the clock divide bits.
FIGURE 69. THE COMMAND STRUCTURE OF THE SMBALERT
RESPONSE ADDRESS
Alert Response
Address
SRd APA Device Address
1 7 1 1 8 1 1
1
SAlert Response
Address Rd A Device Address A PEC A P
1 7 1 1 8 1 1 1
1
8
TABLE 43. 0xE5 CONFIGURE EXTERNAL CLOCK REGISTER DEFINITION
BIT NUMBER D[7] D[6] D[5:4} D[3:0]
Bit Name ExtCLK_EN SMBLALERT2OEN N/A EXTClkDIV
Default
Value
0 0 00 0000
TABLE 44. SMBALERT2_OEN BIT DEFINED
SMBALERT_OEN SMBALERT2 STATUS
0Disabled
1Enabled
(EQ. 13)
freq internal
fEXTCLK
ClkDiv 8()8
ISL28025
FN8388 Rev.5.00 Page 38 of 52
Nov 9, 2017
Voltage Margin / DAC_OUT (20 Pin QFN)
The voltage margining feature within the DPM is commonly used
as a means to test the robustness of a system. The voltage DAC
from the DPM is connected to a summation circuit allowing the
voltage sourced from the DAC to raise or lower the overall voltage
supply to system. A simplified block diagram is illustrated in
Figure 70.
The voltage margining feature can be used to improve accuracy
of the voltage applied to the load of a system. For nonfeedback
driving applications, the sense resistor used to measure current
to the load reduces the voltage to the load. The voltage drop from
the sense resistor can be a large percentage with respect to the
supply voltage for point of load applications.
0XE4 CONFIGURE VOL MARGIN (R/W)
The Configure VOL Margin register is a read/write byte register
that controls the functionality of the voltage margin DAC.
MDAC_HS D[5:3]
The MDAC_HS bits control the half-scale output voltage from the
margin DAC. There are 8 half-scale voltages the margin DAC can
be programmed to. Table 46 lists the selections.
The voltage at the DAC_OUT is the value of the MDAC_HS setting
when the Set VOL Margin register equals 0x80.
LOAD D[2]
The Load bit programs the Set VOL Margin register to the DAC.
The DAC is programmed when the Load bit is programmed from
a 0 to a 1.
DAC_OEN D[1]
The DAC_OEN bit either enables or disables the output of the
margin DAC. Setting the bit to a 1 connects the output of the
margin DAC to the DAC_OUT pin.
DAC_EN D[0]
The DAC_EN bit either enables or disables the margin DAC
circuitry. Setting the bit to a 1 powers up the margin DAC, making
it operational to use.
0XE3 SET VOL MARGIN (R/W)
The Set VOL Margin register is an unsigned read/write byte
register that controls the output voltage of the margin DAC
referenced to the half-scale setting.
The full-scale voltage is twice the half-scale range minus the DAC
LSB for the margin DAC half-scale range. A half-scale setting of
1.0V has a full-scale setting of 1.992V. The LSB for the margin
DAC is a function of the half-scale setting. Using Equation 14, the
LSB for the margin DAC is calculated as;
MDACHS is the half-scale setting for the voltage DAC.
The VOL margin register value for programming the DAC to a
specific voltage is calculated using Equation 15.
The value for VOUTdesired ranges from 0V to two times the
MDACHS value minus one MDACLSB.
FIGURE 70. SIMPLIFIED BLOCK DIAGRAM OF THE MARGIN DAC
FUNCTIONS WITHIN THE DPM
TABLE 45. 0xE4 CONFIGURE VOL MARGIN REGISTER DEFINITION
BIT NUMBER D[7:6] D[5:3] D[2] D[1] D[0]
Bit Name N/A MDAC_HS Load DAC_OEN DAC_EN
Default
Value
00 00 0 0 0 0
TABLE 46. MDAC_HS BITS DEFINED
MDAC_HS[2:0] HALF-SCALE VOLTAGE (V)
000 0.4
001 0.5
010 0.6
011 0.7
100 0.8
101 0.9
110 1.0
111 1.2
TABLE 47. 0xE3 SET VOL MARGIN REGISTER DEFINITION
BIT NUMBER D[7:0]
Bit Name MDAC[7:0]
Default
Value
0000 0000
TABLE 46. MDAC_HS BITS DEFINED
MDAC_HS[2:0] HALF-SCALE VOLTAGE (V)
(EQ. 14)
MDACLSB
2 MDACHS
28
2 MDACHS
256
MDACvalue integer
Voutdesired
MDAC
LSB
(EQ. 15)
ISL28025
FN8388 Rev.5.00 Page 39 of 52
Nov 9, 2017
SMBus/I2C Serial Interface
The ISL28025 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL28025 operates as a slave device in all
applications.
The ISL28025 uses two byte data transfer. All reads and writes
are required to use two data bytes. All communication over the
I2C interface is conducted by sending the MSB of each byte of
data first, followed by the LSB.
Protocol Conventions
For normal operation, data states on the SDA line can change
only during SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating START and STOP conditions (see
Figure 71). On power-up, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 71). A START condition is ignored
during the power-up sequence.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 71). A STOP condition at the end of a read
operation or at the end of a write operation places the device in its
standby mode.
FIGURE 71. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 72. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
ISL28025
FN8388 Rev.5.00 Page 40 of 52
Nov 9, 2017
SMBus and PMBus Support
The ISL28025 supports SMBus and PMBus protocol, which is a
subset of the global I2C protocol. SMBCLK and SMBDAT have the
same pin functionality as the SCL and SDA pins, respectively. The
SMBus operates at 100kHz. The PMBus protocol standardizes
the functionality of each register by address.
Device Addressing
Following a start condition, the master must output a slave address
byte. The 7 MSBs are the device identifiers. The A0, A1 and A2 pins
control the bus address (these bits are shown in Table 48). There
are 55 possible combinations depending on the A0, A1 and A2
connections.
TABLE 48. I2C SLAVE ADDRESSES
A2 A1 A0 SLAVE ADDRESS
GND GND GND 1000 000
GND GND I2CVCC 1000 001
GND GND SDA 1000 010
GND GND SCL 1000 011
GND I2CVCC GND 1000 100
GND I2CVCC I2CVCC 1000 101
GND I2CVCC SDA 1000 110
GND I2CVCC SCL 1000 111
GND SDA GND 1001 000
GND SDA I2CVCC 1001 001
GND SDA SDA 1001 010
GND SDA SCL 1001 011
GND SCL GND 1001 100
GND SCL I2CVCC 1001 101
GND SCL SDA 1001 110
GND SCL SCL 1001 111
I2CVCC GND GND 1010 000
............... .............. .............. ..................
I2CVCC SCL SCL 1011 111
SDA GND GND 1100 000
SDA GND VCC Do Not Use. Reserved
............... .............. .............. ..................
SDA SCL SCL 1101 111
SCL GND GND 1110 000
............... .............. .............. ..................
SCL SDA X Do Not Use. Reserved
SCL SCL X Do Not Use. Reserved
FIGURE 73. BYTE WRITE SEQUENCE (SLAVE ADDRESS INDICATED BY nnnn)
S
T
A
R
T
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM THE
MASTER
SIGNALS FROM
THE ISL28025
A
C
K
10nnn
WRITE
SIGNAL AT SDA nnn
ADDRESS
BYTE
S
T
O
P
DATA
BYTE
A
C
K
N
A
C
K
ISL28025
FN8388 Rev.5.00 Page 41 of 52
Nov 9, 2017
The last bit of the slave address byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 73).
After loading the entire slave address byte from the SDA bus, the
device compares with the internal slave address. Upon a correct
compare, the device outputs an acknowledge on the SDA line.
Following the slave byte is a one byte word address. The word
address is either supplied by the master device or obtained from
an internal counter. On power-up, the internal address counter is
set to address 00h, so a current address read starts at address
00h. When required, as part of a random read, the master must
supply the one word address bytes, as shown in Figure 74.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the registers, the slave byte must be “1nnnnnnx” in
both places.
Write Operation
A write operation requires a START condition, followed by a valid
identification byte, a valid Address byte, two data bytes, and a
STOP condition. The first data byte contains the MSB of the data,
the second contains the LSB. After each of the four bytes, the
device responds with an ACK. At this time, the I2C interface
enters a standby state.
Read Operation
A read operation consists of a three byte instruction, followed by
two data bytes (see Figure 74). The master initiates the operation
issuing the following sequence: A START, the identification byte
with the R/W bit set to “0”, an address byte, a second START and a
second identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL28025 responds with an ACK. Then the
ISL28025 transmits two data bytes as long as the master
responds with an ACK during the SCL cycle following the eighth bit
of the first byte. The master terminates the read operation (issuing
no ACK then a STOP condition) following the last bit of the second
data byte (see Figure 74).
The data bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
address byte in the read operation instruction and increments by
one during transmission of each pair of data bytes.
Group Command
The DPM has a feature that allows the master to configure the
settings of all DPM chips at once. The configuration command
for each device does not have to be same. Device 1 on an I2C bus
can be configured to set the voltage threshold of the OV
comparator while device 2 is configured for the acquisition time
of the VBUS input. To achieve the scenario described without
group command, the master sends two write commands, one to
each slave device. Each command sent from the master has a
start bit and a stop bit. The group command protocol
concatenates the two commands but replaces the stop bit of the
first command and the start bit of the second command with a
repeat start bit. The actions sent in a Group Command format
will execute once the stop bit has been sent. The stop bit signifies
the end of a packet.
The broadcast feature saves time in configuring the DPM as well
as measuring signal parameters in time synchronization. The
broadcast should not be used for DPM read backs. This will
cause all devices connected to the I2C bus to talk to the master
simultaneously.
FIGURE 74. READ SEQUENCE (SLAVE ADDRESS SHOWN AS nnnn)
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0 ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
SECOND READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
1nn nnnn 1nnnnnn
N
A
C
K
FIGURE 75. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES
D15 D14 D13 D10D12 D11 D9 D8
A0A7 A2A4 A3 A1
DATA BYTE 1
A6 A5
1nn n
nnR/W
n
WORD ADDRESS
D7 D6 D5 D2D4 D3 D1 D0
SLAVE ADDRESS
BYTE
DATA BYTE 2
ISL28025
FN8388 Rev.5.00 Page 42 of 52
Nov 9, 2017
Clock Speed
The device supports high-speed digital transactions up to
3.4Mbs. To access the high speed I2C feature, a master byte
code of 0000 1xxx is attached to the beginning of a standard
frequency read/write I2C protocol. The x in the master byte
signifies a do not care state. X can either equal a 0 or a 1. The
master byte code should be clocked into the chip at frequencies
equal or less than 400kHz. The master code command
configures the internal filters of the ISL28025 to permit data bit
frequencies greater than 400kHz. Once the master code has
been clocked into the device, the protocol for a standard
read/write transaction is followed. The frequency at which the
standard protocol is clocked in at can be as great as 3.4MHz. A
stop bit at the end of a standard protocol will terminate the high
speed transaction mode. Appending another standard protocol
serial transaction to the data string without a stop bit, will
resume the high speed digital transaction mode. Figure 76
illustrates the data sequence for the high speed mode. The
minimum I2C supply voltage when operating at clock speeds
400kHz is 1.8V.
Signal Integrity
A filter stage should be considered to limit the effects of
common-mode signals from bleeding into the measurement
made by the ADC. The filter attenuates the amplitude of the
unwanted signal to the noise level of the ISL28025. Figure 77 is
a simple filter example to attenuate unwanted signals.
Measuring large currents require low value sense resistors. A
large valued capacitor is required to filter low frequencies if the
shunt capacitor, CSH is connected directly in parallel to the sense
resistor, RSH. For more manageable capacitor values, it may be
better to directly connect the shunt resistor across the shunt
inputs of the ISL28025. The connection is illustrated in
Figure 77. A single pole filter constructed of 2 resistors, R1, and
RSH will improve capacitor value selections for low frequency
filtering.
R1 and C1 at both shunt inputs are single-ended low pass filters.
The value of the series resistor to the ISL28025 can be a larger
value than the shunt resistor, RSH. A larger series resistor to the
input allows for a lower cutoff frequency filter design to the
ISL28025. The ISL28025 inputs can source up to 20µA of
transient current in the measurement mode. The transient or
switching offset current can be as large as 10µA. The switching
offset current combined with the series resistance, R1, creates
an error offset voltage. A balance of the value of R1 and the
shunt measurement error should be achieved for this filter
design.
The common-mode voltage of the shunt input stage ranges from
0V to 60V. The capacitor voltage rating for C1 and CSH should
comply with the nominal voltage being applied to the input.
Fast Transients
An small isolation resistor placed between ISL28025 inputs and
the source is recommended. In hot swap or other fast transient
events, the amplitude of a signal can exceed the recommended
operating voltage of the part due to the line inductance. The
isolation resistor creates a low pass filter between the device and
the source. The value of the isolation resistor should not be too
large. A large value isolation resistor can effect the
measurement accuracy. The value of the isolation resistor
combined with the offset current creates an offset voltage error
at the shunt input. The input of the Bus channel is connected to
the top of a precision resistor divider. The accuracy of the resistor
divider determines the gain error of the Bus channel. The input
resistance of the Bus channel is 600kΩ. Placing an isolation
resistor of 10Ω will change the gain error of the Bus channel by
0.0016%.
FIGURE 76. BYTE TRANSACTION SEQUENCE FOR INITIATING DATA RATES ABOVE 400kbps
SIGNALS
FROM THE
MASTER
SIGNALS TO THE
ISL28025
SIGNAL AT
SDA
S
T
A
R
T
MASTER
CODE
SLAVE ADDRESS
IDENTIFICATION
BYTE
A
C
K
x
S
T
O
P
ADDRESS
BYTE
A
C
K
WRITE/READ
000 01xx
S
T
A
R
T
DATA
BYTE
DATA
BYTE
A
C
K
N
A
C
K
fclk ≤ 400kHz
fclk UP TO 3.4MHz
TERMINATES HS
MODE
x1nnnnnn
N
A
C
K
FIGURE 77. SIMPLIFIED FILTER DESIGN TO IMPROVE NOISE
PERFORMANCE TO THE ISL28025
LOAD
RSH
FROM
SOURCE
ISL28025
R1
R1
CSH
C1
C1
ISL28025
FN8388 Rev.5.00 Page 43 of 52
Nov 9, 2017
External Clock
An externally controlled clock allows measurements to be
synchronized to an event that is time dependent. The event could
be application generated, such as timing a current measurement
to a charging capacitor in a switch regulator application or the
event could be environmental. A voltage or current measurement
may be susceptible to crosstalk from a controlled source. Instead
of filtering the environmental noise from the measurement,
another approach would be to synchronize the measurement to
the source. The variability and accuracy of the measurement will
improve.
The ISL28025 has the functionality to allow for synchronization
to an external clock. The speed of the external clock combined
with the choice of the internal chip frequency division value
determines the acquisition times of the ADC. The internal system
clock frequency is 500kHz. The internal system clock is also the
ADC sampling clock. The acquisition times scale linearly from
500kHz. For example, an external clock frequency of 4.0MHz
with a frequency divide setting of 0 (internal divide by 8) results
in acquisition times that equals the internal oscillator frequency
when enabled. The ADC modulator is optimized for frequencies
of 500kHz. Operating internal clock frequencies beyond 500kHz
may result in measurement accuracy errors due to the modulator
not having enough time to settle.
Suppose an external clock frequency of 5.5MHz is applied with a
divide by 88 internal frequency setting, the system clock speed is
62.5kHz or 8x slower than internal system clock. The acquisition
times for this example will increase by 8. For a channel’s
conversion time setting of 2.048ms, the ISL28025 will have an
acquisition time of 256µs.
Figure 79 illustrates a simple mathematical diagram of the ECLK
pin internal connection. The external clock divide is controlled by
way of the EXTCLKDIV bit in register 0xE5.
Figure 80 illustrates how changing the system clock frequency
effects the measurement bandwidth (the ADC acquisition time).
The bandwidth of the external clock circuitry is 25MHz. Figure 81
shows the bandwidth of the external clock circuitry when the
external clock division bits equals to 0.
The external clock pin can accept signal frequencies above
25MHz by programming the system clock frequency, so that the
internal clock frequency is below 25MHz.
FIGURE 78. SIMPLIFIED SCHEMATIC OF THE ISL28025
SYNCHRONIZED TO A MCU SYSTEM CLOCK
LOAD
VOUT =
0.6 * (1+ R2/R1)
I2C
SMBUS
A1
SCL
SDA
VINP GND
ADC
16-Bit
SW MUX
PMBus
REG
MAP
A0
ISL28025
VCC
VINM
VBUS
FB
ISL85415
En
PG
GND
VCC,FS,SS
VIN
A2
Lo
PHASE
SYNC,COMP
1µF
0.1µF
BOOT
VIN = 4.5VÆ 36V
R2
R1
Vmcu
GND
GPIO/Int
SDA
GPIO SCL
R_pullUp
R_pullUp
MCU
I2CVCC
3.3V
Vreg
Vreg_in
Vreg_Out
VIN
RSH
AuxV
TEMP
SENSE
VIN
SMBALERT1
EXT CLK
GPIO
To ISL85415 SYNC
SYNC
FIGURE 79. EXTERNAL CLOCK MODE
FIGURE 80. MEASUREMENT BANDWIDTH vs EXTERNAL CLK
FREQUENCY
-15.5
-13.5
-11.5
-9.5
-7.5
-5.5
-3.5
-1.5
0.5
10 100 1k 10k 100k
FREQUENCY (Hz)
GAIN (dB)
FreqExtClk = 16MHz
ADC TIME SETTING
(CONFIG_ICHANNEL) = 0
ExtClkDiv = 4
ExtClkDiv = 0
ExtClkDiv = 1
ExtClkDiv = 14
ExtClkDiv = 3
ISL28025
FN8388 Rev.5.00 Page 44 of 52
Nov 9, 2017
Figure 82 illustrates the effects of dividing the external clock
frequency on the VSHUNT measurement accuracy.
Figures 81 and 82 were generated by applying a DC voltage to
the VSHUNT input and measuring the signal by way of an ADC
conversion.
Overranging
Do not operate the ISL28025 outside the set voltage range. In
the event of measuring a shunt voltage beyond the maximum set
range (80mV) and lower than the clamp voltage of the protection
diode (1V), the measured output reading may be within the
accepted range but will be incorrect.
Shunt Resistor Selection
In choosing a sense resistor, the following resistor parameters
need to be considered; the resistor value, resistor temperature
coefficient and resistor power rating.
The sense resistor value is a function of the full-scale voltage
drop across the shunt resistor and the maximum current
measured for the application. The maximum measurable range
for the VSHUNT input (VINP - VINM) of the ISL28025 is 80mV. The
ISL28025 allows the user to define a unique range other than
±80mV.
Once the voltage range for the input is chosen and the maximum
measurable current is known, the sense resistor value is
calculated using Equation 16.
In choosing a sense resistor, the sense resistor power rating
should be taken into consideration. The physical size of a sense
resistor is proportional to the power rating of the resistor. The
maximum power rating for the measurement system is
calculated as the Vshunt_range multiplied by the maximum
measurable current expected. The power rating equation is
represented in Equation 17.
A general rule of thumb is to multiply the power rating calculated
in Equation 17 by 2. This allows the sense resistor to survive an
event when the current passing through the shunt resistor is
greater than the measurable maximum current. The higher the
ratio between the power rating of the chosen sense resistor and
the calculated power rating of the system (Equation 17), the less
the resistor will heat up in high current applications.
The Temperature Coefficient (TC) of the sense resistor directly
degrades the current measurement accuracy. The surrounding
temperature of the sense resistor and the power dissipated by
the resistor will cause the sense resistor value to change. The
change in resistor temperature with respect to the amount of
current that flows through the resistor is directly proportional to
the ratio of the power rating of the resistor versus the power
being dissipated. A change in sense resistor temperature results
in a change in sense resistor value. Overall, the change in sense
resistor value contributes to the measurement accuracy for the
system. The change in a resistor value due to a temperature rise
can be calculated using Equation 18.
Temperature is the change in temperature in Celsius. RsenseTC
is the temperature coefficient rating for a sense resistor. Rsense
is the resistance value of the sense resistor at the initial
temperature.
FIGURE 81. EXTERNAL CLOCK BANDWIDTH vs MEASUREMENT
ACCURACY
FIGURE 82. EXTERNAL CLOCK vs EXTERNAL BIT VALUE
-8.5
-7.5
-6.5
-5.5
-4.5
-3.5
-2.5
-1.5
-0.5
0.5
0.01 0.1 1 10 100
ExtClk FREQUENCY (MHz)
GAIN (dB)
ExtDiv = 0; (FreqInt = FreqExtClk / 8)
-8.5
-7.5
-6.5
-5.5
-4.5
-3.5
-2.5
-1.5
-0.5
0.5
0 1 2 3 4 5 6 7 8 9 10111213141516
ExtClkDiv BIT VALUE
GAIN (dB)
ExtClk FREQUENCY = 45MHz
(EQ. 16)
Rsense
Vshunt_range
Imeas Max
(EQ. 17)
Pres_rating Vshunt_range Imeas Max
(EQ. 18)
Rsense Rsense Rsense TC
Temperature
ISL28025
FN8388 Rev.5.00 Page 45 of 52
Nov 9, 2017
Table 49 is a shunt resistor look-up table for select full-scale
current measurement ranges (ImeasMax). The table also
provides the minimum rating for each shunt resistor.
It can be difficult to readily purchase shunt resistor values for a
desired measurable current range. Either the value of the shunt
resistor does not exist or the power rating of the shunt resistor is
too low. To avoid this problem, use two or more shunt resistors in
parallel to set the desired current measurement range. For
example, an application requires a full-scale current of 100A with
a maximum voltage drop across the shunt resistor of 80mV.
From Table 49, this requires a sense resistor of 0.8mΩ, 8W
resistor. Assume the power ratings and the shunt resistor values
to chose from are 1mΩ4W, 2mΩ/4W and 4mΩ/4W.
Let’s use a 1mΩ and a 4mΩ resistor in parallel to create the
shunt resistor value of 0.8mΩ. Figure 83 shows an illustration of
the shunt resistors in parallel.
The power to each shunt resistor should be calculated before
calling a solution complete. The power to each shunt resistor is
calculated using Equation 19.
The power dissipated by the 1mΩ resistor is 6.4W. 1.6W is
dissipated by the 4mΩ resistor. 1.6W exceeds the rating limit of
1W for the 1mΩ sense resistor. Another approach would be to
use three shunt resistors in parallel as illustrated in Figure 84.
Using Equation 19, the power dissipated to each shunt resistor
yields 3.2W for the 2mΩ shunt resistors and 1.6W for the 4mΩ
shunt resistor. All shunt resistor are within the specified power
ratings.
Layout
The layout of a current measuring system is equally important as
choosing the correct sense resistor and the correct analog
converter. Poor layout techniques can result in severed traces,
signal path oscillations, and magnetic contamination, which all
contribute to poor system performance.
TRACE WIDTH
Matching the current carrying density of a copper trace with the
maximum current that will pass through is critical in the
performance of the system. Neglecting the current carrying
capability of a trace will result in a large temperature rise in the
trace, and the loss in system efficiency due to the increase in
resistance of the copper trace. In extreme cases, the copper
trace could be severed because the trace could not pass the
current. The current carrying capability of a trace is calculated
using Equation 20.
Imax is the largest current expected to pass through the trace. T
is the allowable temperature rise in Celsius when the maximum
current passes through the trace. TraceThickness is the thickness
of the trace specified to the PCB fabricator in mils. A typical
thickness for general current carrying applications (<100mA) is
0.5oz. copper or 0.7mils. For larger currents, the trace thickness
should be greater than 1.0oz. or 1.4mils. A balance between
thickness, width and cost needs to be achieved for each design.
The coefficient k in Equation 20 changes depending on the trace
location. For external traces, the value of k equals 0.048 while
for internal traces the value of k reduces to 0.024. The k values
and Equation 20 are stated per the ANSI IPC-2221(A) standards.
TABLE 49. SHUNT RESISTOR VALUES AND POWER RATINGS FOR
SELECT MEASURABLE CURRENT RANGES
RSENSE/PRATING VSHUNT RANGE (PGA SETTING)
ImeasMax 80mV
100µA 800Ω/8µW
1mA 80Ω/80µW
10mA 8Ω/800µW
100mA 800mΩ/8mW
500mA 160mΩ/40mW
1A 80mΩ/80mW
5A 16mΩ/400mW
10A 8mΩ/800mW
50A 1.6mΩ/4W
100A 0.8mΩ/8W
500A 0.16mΩ/40W
FIGURE 83. SIMPLIFIED SCHEMATIC ILLUSTRATING THE USE OF
TWO SHUNT RESISTORS TO CREATE A DESIRED SHUNT
VALUE
0.001
0.004
(EQ. 19)
PshuntRes
Vshunt_range
2
Rsense
FIGURE 84. INCREASING THE NUMBER OF SHUNT RESISTORS IN
PARALLEL TO CREATE A SHUNT RESISTOR VALUE
REDUCES THE POWER DISSIPATED BY EACH SHUNT
RESISTOR
0.002
0.004
0.002
(EQ. 20)
Trace width
Imax
kT0.44
1
0.725
Trace Thickness
ISL28025
FN8388 Rev.5.00 Page 46 of 52
Nov 9, 2017
TRACE ROUTING
It is always advised to make the distance between the voltage
source, sense resistor, and load as close as possible. The longer
the trace length between components will result in voltage drops
between components. The additional resistance will reduce the
efficiency of a system.
The bulk resistance, , of copper is 0.67µΩ/in or 1.7µΩ/cm at
+25°C. The resistance of trace can be calculated from
Equation 21.
Figure 85 illustrates each dimension of a trace.
For example, assume a trace has 2oz. of copper or 2.8mil
thickness, a width of 100mil and a length of 0.5in. Using
Equation 21, the resistance of the trace is approximately 2mΩ.
Assume 1A of current is passing through the trace. A 2mV
voltage drop would result from trace routing.
Current flowing through a conductor will take the path of least
resistance. When routing a trace, avoid orthogonal connections
for current bearing traces.
Orthogonal routing for high current flow traces will result in
current crowding, localized heating of the trace and a change in
trace resistance.
The utilization of arcs and 45° traces in routing large current flow
traces will maintain uniform current flow throughout the trace.
Figure 87 illustrates the routing technique.
CONNECTING SENSE TRACES TO THE CURRENT SENSE
RESISTOR
Ideally, a four terminal current sense resistor would be used as
the sensing element. Four terminal sensor resistors can be hard
to find in specific values and in sizes. Often a two terminal sense
resistor is designed into the application.
Sense lines are high impedance by definition. The connection
point of a high impedance line reflects the voltage at the
intersection of a current bearing trace and a high impedance
trace.
The high impedance trace should connect at the intersection
where the sense resistor meets the landing pad on the PCB. The
best place to make current sense line connection is on the inner
side of the sense resistor footprint. The illustration of the
connection is shown in Figure 88. Most of the current flow is at
the outer edge of the footprint. The current ceases at the point
the sense resistor connects to the landing pad. Assume the
sense resistor connects at the middle of the each landing pad,
this leaves the inner half of the each landing pad with little
current flow. With little current flow, the inner half of each
landing pad is classified as high impedance and perfect for a
sense connection.
FIGURE 85. ILLUSTRATION OF THE TRACE DIMENSIONS OF A STRIP
LINE TRACE
FIGURE 86. AVOID ROUTING ORTHOGONAL CONNECTIONS FOR
TRACES THAT HAVE HIGH CURRENT FLOWS.
(EQ. 21)
Rtrace Trace length
Trace width Trace thickness
TRACE
LENGTH
TRACE
WIDTH
TRACE
THICKNESS
CurrentFlow
FIGURE 87. USE ARCS AND 45° TRACES TO SAFELY ROUTE TRACES
WITH LARGE CURRENT FLOWS
CURRENTFLOW
CURRENTFLOW
ISL28025
FN8388 Rev.5.00 Page 47 of 52
Nov 9, 2017
Current sense resistors are often smaller than the width of the
traces that connect to the footprint. The trace connecting to the
footprint is tapered at a 45° angle to control the uniformity of the
current flow.
MAGNETIC INTERFERENCE
The magnetic field generated from a trace is directly proportional
to the current passing through the trace and the distance from
the trace the field is being measured at. Figure 89 illustrates the
direction the magnetic field flows versus current flow.
The equation in Figure 89 determines the magnetic field, B, the
trace generates in relation to the current passing through the
trace, I, and the distance the magnetic field is being measured
from the conductor, r. The permeability of air, µo, is 4 *10-7
H/m.
When routing high current traces, avoid routing high impedance
traces in parallel with high current bearing traces. One way of
limiting the magnetic interference from high current traces is to
closely route the paths connected to and from the sense resistor.
The magnetic fields will cancel outside the two traces and add
between the two traces. Figure 90 illustrates a magnetic field
insensitive layout.
If possible, do not cross traces with high current. If a trace
crossing cannot be avoided, cross the trace in an orthogonal
manner and the furthest layer from the current bearing trace.
The inference from the current bearing trace will be limited.
A Trace as a Sense Resistor
In previous sections, the resistance and the current carrying
capabilities of a trace were discussed. In high current sense
applications, a design may utilize the resistivity of a current
sense trace as the sense resistor. This section will discuss how to
design a sense resistor from a copper trace.
Suppose an application needs to measure current up to 200A.
The design requires the least amount of voltage drop for
maximum efficiency. The full-scale voltage range of 40mV is
chosen. From Ohm’s law, the sense resistor is calculated to be
200µΩ. The power rating of the resistor is calculated to be 8W.
Assume the PCB trace thickness of the board equals
2oz./2.8mils and the maximum temperature rise of the trace is
+20°C. Using Equation 20 on page 45, the calculated trace
width is 2.192in. The trace width, thickness and the desired
sense resistor value is known. Utilizing Equation 21 on page 46,
the trace length is calculated to be 1.832in.
FIGURE 88. CONNECTING THE SENSE LINES TO A CURRENT SENSE
RESISTOR
FIGURE 89. THE CONDUCTOR ON THE LEFT SHOWS THE MAGNETIC
FIELD FLOWING IN A CLOCKWISE DIRECTION FOR
CURRENTS FLOWING INTO THE PAGE. CURRENT FLOW
OUT OF THE PAGE HAS A COUNTER CLOCKWISE
MAGNETIC FLOW
SENSE
RESISTOR
SENSE TRACE
SENSE TRACE
LANDING PAD
LANDING PAD
CURRENT BEARING TRACE
CURRENT BEARING TRACE
B
oI
2 r
FIGURE 90. CLOSELY ROUTED TRACES THAT CONNECT TO THE
SENSE RESISTOR REDUCES THE MAGNETIC
INTERFERENCE SOURCED FROM THE CURRENT
FLOWING THROUGH THE TRACES
SENSE
RESISTOR
SENSE
TRACE
SENSE
TRACE
LANDING
PAD
LANDING
PAD
CURRENT
FLOW
CURRENT
FLOW
TO THE SENSE
RESISTOR
FROM THE
SENSE RESISTOR
Bto Bfrom
Bto Bfrom
Bto Bfrom
TO SENSE
CIRCUITRY
ISL28025
FN8388 Rev.5.00 Page 48 of 52
Nov 9, 2017
Figure 91 illustrates a layout example of a current sense resistor
defined by a PCB trace. The serpentine pattern of the resistor
reduces current crowding as well as limiting the magnetic
interference caused by the current flowing through the trace.
For the example discussed, the width of the trace in Figure 91
illustration would equal 2.192in and the length between the
sense lines equals 1.832in.
The width of the resistor is long for some applications. A means
of shortening the trace width is to connect two traces in parallel.
For calculation ease, assume the resistive traces are routed on
the outside layers of a PCB. Using Equations 20 and 21, the
width of the trace is reduced from 2.192in to 1.096in.
When using multiple layers to create a trace resistor, use
multiple vias to keep the trace potentials between the two
conductors the same. Vias are highly resistive compared to a
copper trace. Multiple vias should be employed to lower the
voltage drop due to current flowing through resistive vias.
Figure 92 illustrates a layout technique for a multiple layered
trace sense resistor.
Lossless Current Sensing (DCR)
A DCR sense circuit is an alternative to a sense resistor. The DCR
circuit utilizes the parasitic resistance of an inductor to measure
the current to the load. A DCR circuit remotely measures the
current through an inductor. The lack of components in series
with the regulator to the load makes the circuit lossless.
A properly matched DCR circuit has an equivalent circuit seen by
the ADC equals to Rdcr in Figure 93. Before deriving the transfer
function between the inductor current and voltage seen by the
ISL28025, let’s review the definition of an inductor and capacitor
in the Laplacian domain.
Xc is the impedance of a capacitor related to the frequency and
XL is the impedance of an inductor related to frequency. ω equals
to 2f. f is the chop frequency dictated by the regulator. Using
Ohm’s law, the voltage across the DCR circuit in terms of the
current flowing through the inductor is define in Equation 23.
[1] In Equation 23, Rdcr is the parasitic resistance of the
inductor. The voltage drop across the inductor (Lo) and the
resistor (Rdcr) circuit is the same as the voltage drop across
the resistor (Rsen) and the capacitor (Csen) circuit.
Equation 24 defines the voltage across the capacitor (Vcsen)
in terms of the inductor current (IL).
The relationship between the inductor load current (IL) and the
voltage across capacitor simplifies if the following component
selection holds true;
FIGURE 91. ILLUSTRATES A LAYOUT EXAMPLE OF A CURRENT
SENSE RESISTOR MADE FROM A PCB TRACE
FIGURE 92. ILLUSTRATES A LAYOUT EXAMPLE OF A MULTIPLE
LAYER TRACE RESISTOR
CURRENTFLOWIN
CURRENTFLOWOUT
SENSENEG(‐)
SENSEPOS(+)
Thelengthofthe
tracebetweenthe
twosenselines
definesthesense
resistorvalue.
TOP
BOTTOM
TRACE
TRACE
VIA
VIA
TRACE
VIA
(A) CROSS SECTION VIEW (B) TOP VIEW
PCB
PCB
FIGURE 93. SIMPLIFIED CIRCUIT EXAMPLE OF A DCR
VINP
VINM
LO Rdcr
Csen
Rsen
DCR CIRCUIT
ADC
16-BIT
BUCK
REGULATOR
FB
PHASE
LOAD
Rsen + Rdcr
(EQ. 22)
Xcf() 1
jf()CXLf() jf()L
(EQ. 23)
Vdcr f() R
dcr jf()L
iL
(EQ. 24)
Vcf()
jf()LRdcr

1jf()Csen
Rsen
Rdcr
1jf()L

Rdcr
1jf()Csen
Rsen
iL
(EQ. 25)
L
Rdcr
Csen Rsen
ISL28025
FN8388 Rev.5.00 Page 49 of 52
Nov 9, 2017
If Equation 25 holds true, the numerator and denominator of the
fraction in Equation 24 cancels out, reducing the voltage across
the capacitor to the equation represented in Equation 26.
Most inductor datasheets will specify the average value of the
Rdcr for the inductor. Rdcr values are usually below 1mΩ with a
tolerance averaging 8%. Common chip capacitor tolerances
average to 10%.
Inductors are constructed out of metal, which has a high
temperature coefficient. The temperature drift of the inductor
value could cause the DCR circuit to be untuned. An untuned
circuit results in inaccurate current measurements along with a
chop signal bleeding into the measurement. To counter the
temperature variance, a temperature sensor may be incorporated
into the design to track the change in component values.
A DCR circuit is good for gross current measurements. As
discussed, inductors and capacitors have high tolerances and are
temperature dependent, which will result in less than accurate
current measurements.
In Figure 93, there is a resistor in series with the ISL28025
negative shunt terminal, VINM, with the value of Rsen + Rdcr. The
resistor’s purpose is to counter the effects of the bias current
from creating a voltage offset at the input of the ADC.
(EQ. 26)
VcRdcr iL
FN8388 Rev.5.00 Page 50 of 52
Nov 9, 2017
ISL28025
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit the website to ensure you
have the latest version.
DATE REVISION CHANGE
Nov 9, 2017 FN8388.5 Added ISL28025FR12Z, 20 lead QFN Quad Flat No-Lead Plastic Package 12V version.
Updated the Related Literature section on page 1.
Added Note 4 to the Ordering Information table.
Added ISL28025FR12 to the VBUS entry in the Absolute Maximum Ratings table.
Feb 19, 2016 FN8388.4 Changed the Polarity of the CNVR bit from HIGH to LOW when the ADC is making a conversion. See “CNVR:
Conversion Ready D[1]” on page 28.
Updated “Ordering Information” table on page 3 by adding Tape and Reel option column.
Figure 73 on page 40, removed 0s from Address Byte and changed last “ACK” to “NACK”.
Figure 74 on page 41 added “NACK” before “STOP”
Figure 76 on page 42, changed “signals from the ISL28025” to “signals to the ISL28025” added “NACK” to the
diagram before the repeat start and changed last “ACK” to “NACK”.
Jun 17, 2015 FN8388.3 Added Related Literature section on page 1.
Added DPM Portfolio Comparison table on page 5.
Removed Typical Applications section (which included Figure 102) and made into an appnote (AN1955).
Feb 17, 2015 FN8388.2 Changed Reference of ZL9050 in Figure 102 on page 51 to ISL8272M.
Oct 24,2014 FN8388.1 “Vbus_OV_OT_Set D[5:0]” on page 31, changed step size from “1.95°” to “5.71°C” and added “The
mathematical range is -144°C to +221.4.°C”.
Updated Table 23 on page 31 by adding column OT THRESHOLD VALUE.
Changed title of Table 29 on page 32 from “Vbus_OV_OT_Set BITS DEFINED” to “Vshunt_OC_Set BITS
DEFINED”.
Jun 30, 2014 FN8388.0 Initial release
ISL28025
FN8388 Rev.5.00 Page 51 of 52
Nov 9, 2017
Package Outline Drawing WLCSP
W4x4.16C (WLCSP 0.5mm PITCH)
WAFER LEVEL CHIP SCALE PACKAGE
Rev 1, 05/14
BOTTOM VIEW
RECOMMENDED LAND PATTERN
SIDE VIEW
Ø0.10
Ø0.05
Z
Z
XYM
M
1234
A
B
C
D
0.250
Z
0.600 ±0.06mm
0.240 ±0.030
0.320 ±0.030
0.330
TOP VIEW
0.05 Z
NSMD refers to non-solder mask defined pad design per Intersil Techbrief TB451.
Dimension and tolerance per ASMEY 14.5M-1994,
3.
2.
All dimensions are in millimeters.1.
NOTES:
and JESD 95-1 SPP-010.
PIN 1
(A1 CORNER)
2.160 ±0.030
2.160 ±0.030
YX
0.10
(4X)
1.500
0.500
0.330
16x 0.320 ±0.030
0.280
0.500
0.330
NSMD3
PACKAGE
OUTLINE
SEATING PLANE
For the most recent package outline drawing, see W4x4.16C
ISL28025
FN8388 Rev.5.00 Page 52 of 52
Nov 9, 2017
Package Outline Drawing
L20.4x4J
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/16
0 . 90 ± 0 . 1
5
C0 . 2 REF
TYPICAL RECOMMENDED LAND PATTERN
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
( 24X 0 . 25 )
0 . 00 MIN.
( 20X 0 . 5 )
( 2 . 50 )
SIDE VIEW
( 3 . 8 TYP )
BASE PLANE
4
TOP VIEW
BOTTOM VIEW
712
24X 0 . 4 ± 0 . 1
13
4.00
PIN 1
18
INDEX AREA
24
19
4.00
2.5
0.50
20X
4X
SEE DETAIL "X"
- 0 . 05
+ 0 . 07
24X 0 . 23
2.45 (+ 0.10mm)
PIN #1 CORNER
(C 0 . 25)
1
SEATING PLANE
0.08 C
0.10 C
C
0.10 M C A B
A
B
(4X) 0.15
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
(- 0.15mm)
For the most recent package outline drawing, see L20.4x4J
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