0.047
[1.2]
0.047
1.2
0.043
[1.1]
0.100
[2.54]
0.043
[1.1]
0.025
[0.64]
0.047
1.2
0.050
1.27
0.033 ±0.002
0.85 ±0.05
0.197 ±0.002
5 ±0.05
0.126 ±0.002
3.2 ±0.05
456
1 2 3
0.039 ±0.002
1 ±0.05
0.025 ±0.002
0.64 ±0.05
0.047
1.2
REF
0.050
1.270
456
13 2
Recommended Land Pattern for LVPECL, LVDS, HCSL
Note: Recommend using an approximately
0.01uF bypass capacitor between PIN 6 and 3.
Via to Power Layer
Recommended Land Pattern FOR CMOS
Via to GND Layer
6
1 2
5
3
4
*
Pin
Function
1
Tri-state
2
NC
3
GND
4
Output
5
NC (CMOS)
Output (LVPECL, LVDS,
HCSL)
6
Vdd
-
ASFLMP
XXXXXX
XXXXXX
WEIGHT:
A3
SHEET 1 OF 1
SCALE:12:1
DWG NO.
TITLE:
REVISION
DO NOT SCALE DRAWING
MATERIAL:
DATE
SIGNATURE
NAME
DEBUR AND
BREAK SHARP
EDGES
FINISH:
UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE IN INCH(MM)
SURFACE FINISH:
TOLERANCES:
LINEAR:
ANGULAR:
Q.A
MFG
APPV'D
CHK'D
DRAWN
30332 Esperanza, Rancho Santa margarita, California 92688
Oscillator
TOP PACKAGE MARKING IS
FOR ILLUSTRATION PURPOSES ONLY
