G D S
Gate Drain Source
Target Applications
Wireless charging
Adapter
Telecom
Base part number Package Type Standard Pack
Form Quantity
IRL80HS120 PQFN 2mm x 2mm Tape and Reel 4000 IRL80HS120
Orderable Part Number
VDSS VGS
80V min. ± 20V max
Qg tot Qgd
4.7nC 1.8nC
RDS(on) (max.)
32m@ 10V
Vgs(th)
1.7V
Final Datasheet Please read the important Notice and Warnings at the end of this document V1.3
www.infineon.com 2017-06-20
IRL80HS120
Figure 1 Typical On-Resistance vs. Gate Voltage Figure 2 Typical On-Resistance vs. Drain Current
Typical values (unless otherwise specified)
PQFN 2 mm x 2 mm
Top View
G 3 S
D2
D1
4S
5D
6D
D
Benefits
Higher power density designs
Higher switching frequency
IR MOSFET — Uses OptiMOSTM5 Chip
Reduced parts count wherever 5V
supplies are available
Driven directly from microcontrollers
(slow switching)
System cost reductions
010 20 30 40
ID, Drain Current (A)
10
20
30
40
50
60
70
80
90
100
Typical RDS(on) (m)
VGS = 4.0V
VGS = 4.5V
VGS = 5.0V
VGS = 6.0V
VGS = 7.0V
VGS = 10V
2345678910 11 12
VGS, Gate -to -Source Voltage (V)
10
20
30
40
50
60
70
80
90
100
110
120
RDS(on), Drain-to -Source On Resistance (m )
ID = 7.5A
TJ = 25°C
TJ = 125°C
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2
Table of Contents
Table of Contents
Target Applications …..……..……..………………………………………………………………………...……1
Benefits …..………………………………………………………………………...……………..…………….1
Ordering Table ….……………………………………………………………………………………………………1
Table of Contents ….………………………………………………………………………………………………...2
1 Parameters ………………………………………………………………………………………………3
2 Maximum ratings, Thermal, and Avalanche characteristics ………………………………………4
3 Electrical characteristics ………………………………………………………………………………5
4 Electrical characteristic diagrams ……………………………………………………………………6
Package Information ………………………………………………………………………………………………12
Qualification Information ……………………………………………………………………………………………14
Revision History …………………………………………………………………………………………..…………15
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3
1 Parameters
Table1 Key performance parameters
Parameter Values Units
VDS 80 V
RDS(on) max 32 m
ID @ TC = 25°C 12.5 A
ID @ TA = 25°C 6.0 A
Parameters
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4
Table 2 Maximum ratings (at TJ = 25°C, unless otherwise specified)
Parameter Symbol Conditions Values Unit
Continuous Drain Current (Silicon Limited) ID TC (Bottom) = 25°C, VGS @ 10V 12.5
A
Continuous Drain Current (Silicon Limited) ID TC (Bottom) = 100°C, VGS @ 10V 9.0
Continuous Drain Current (Silicon Limited)
(Source Bonding Technologies Limited) ID TC (Bottom) = 25°C, VGS @ 10V 10.2
Continuous Drain Current (Silicon Limited) ID TA= 25°C, VGS @ 10V 6.0
Pulsed Drain Current IDM TC (Bottom) = 25°C 41
Maximum Power Dissipation PD TC (Bottom) = 25°C 11.5
W
Maximum Power Dissipation PD TC (Bottom) = 100°C 5.8
Maximum Power Dissipation PD TA = 25°C 2.5
Gate-to-Source Voltage VGS - ± 20 V
Peak Soldering Temperature TP - 270
°C
Operating Junction and TJ ,TSTG -55 to + 175
Storage Temperature Range -
Table 4 Avalanche characteristics
Parameter Symbol Values Unit
Single Pulse Avalanche Energy EAS 22 mJ
Avalanche Current IAR 7.5 A
Table 3 Thermal characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit
Junction-to-Case (Bottom) RJC - - - 13
°C/W
Junction-to-Case (Top) RJC - - - 90
Junction-to-Ambient RJA - - - 60
Junction-to-Ambient RJA (<10s) - - - 42
2 Maximum ratings and thermal characteristics
Maximum ratings and thermal characteristics
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.8mH, RG = 50
, IAS = 7.5A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
R
is measured at TJ of approximately 90°C.
When mounted on a 1 inch square PCB (FR-4). Please refer to AN-994 for more details.
Calculated continuous current based on maximum allowable junction temperature.
Current is limited to 10.2A by source bonding technology.
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IRL80HS120
5
D
S
G
Table 6 Dynamic characteristics
Parameter Symbol Conditions Values Unit
Min. Typ. Max.
Forward Trans conductance gfs VDS = 10V, ID = 7.5A 14 - - S
Total Gate Charge Qg
ID = 7.5A
VDS = 40V
VGS = 4.5V
See Fig.8
- 4.7 7.0
nC
Pre-Vth Gate-to-Source Charge Qgs1 - 1.3 -
Post-Vth Gate-to-Source Charge Qgs2 - 0.6 -
Gate-to-Drain Charge Qgd - 1.8 -
Gate Charge Overdrive Qgodr - 1.0 -
Switch Charge (Qgs2 + Qgd) Qsw - 2.4 -
Output Charge Qoss VDS = 40V ,VGS = 0V - 9.2 - nC
Turn-On Delay Time td(on) VDD = 40V - 7.6 -
Rise Time tr ID = 7.5A - 22 -
Turn-O Delay Time td(o) RG = 2.7 - 9.2 -
Fall Time tf VGS = 4.5V - 10 -
Input Capacitance Ciss VGS = 0V - 540 -
pF
Output Capacitance Coss VDS = 25V - 150 -
Reverse Transfer Capacitance Crss ƒ = 1.0MHz - 12 -
Output Capacitance Coss VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz - 410 -
Output Capacitance Coss VGS = 0V, VDS = 64V, ƒ = 1.0MHz - 70 -
ns
Table 7 Reverse Diode
Parameter Symbol Conditions Values Unit
Min. Typ. Max.
Continuous Source Current IS MOSFET symbol - - 12.5
A
(Body Diode) showing the
Pulsed Source Current ISM integral reverse - - 41
(Body Diode) p-n junction diode.
Diode Forward Voltage VSD TJ = 25°C, IS = 7.5A,VGS = 0V - - 1.2 V
Reverse Recovery Time trr TJ = 25°C, IF = 7.5A, VDD = 40V - 26 - ns
Reverse Recovery Charge Qrr di/dt = 100A/µs - 21 - nC
Table 5 Static characteristics
Parameter Symbol Conditions Values Unit
Min. Typ. Max.
Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA 80 - - V
Breakdown Voltage Temp. Coeicient V(BR)DSS/TJ Reference to 25°C, ID = 1mA - 38 - mV/°C
Static Drain-to-Source On-Resistance VGS = 10V, ID = 7.5A - 25 32 m
VGS = 4.5V, ID = 3.8A - 32 42
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 10µA
1.1 1.7 2.3 V
Gate Threshold Voltage Temp. Coeicient VGS(th)/TJ - -6.4 - mV°/C
Drain-to-Source Leakage Current IDSS VDS = 64V, VGS = 0V - - 1.0 µA
Gate-to-Source Forward Leakage IGSS VGS = 20V - - 100 nA
IGSS VGS = -20V - - 100
Gate Resistance RG - - 1.1 -
RDS(on)
3 Electrical characteristics
Electrical characteristics
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Electrical characteristic diagrams
4 Electrical characteristic diagrams
Figure 3 Typical Output Characteristics Figure 4 Typical Output Characteristics
Figure 5 Typical Transfer Characteristics Figure 6 Normalized On-Resistance vs. Temperature
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.4
0.8
1.2
1.6
2.0
2.4
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 7.5A
VGS = 10V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
VGS
TOP 12V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
60µs PULSE WIDTH
Tj = 25°C
2.7V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
VGS
TOP 12V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
60µs PULSE WIDTH
Tj = 175°C
2.7V
2 3 4 5
VGS, Gate-to-Source Voltage (V)
1
10
100
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 25V
60µs PULSE WIDTH
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7
Electrical characteristic diagrams
Figure 7 Typical Capacitance vs. Drain-to-Source
Voltage
Figure 8 Typical Gate Charge vs. Gate-to-Source
Voltage
Figure 9 Typical Source-Drain Diode Forward
Voltage
Figure 10 Maximum Safe Operating Area
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
024681012
QG, Total Gate Charge (nC)
0
2
4
6
8
10
12
14
VGS, Gate-to-Source Voltage (V)
VDS= 64V
VDS= 40V
VDS= 16V
ID = 7.5A
0.4 0.6 0.8 1.0 1.2 1.4
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0.1 1 10 100
VDS, Drain-toSource Voltage (V)
0.01
0.1
1
10
100
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA LIMITED BY RDS (on)
100µsec
DC
LIMITED BY PACKAGE
Final Datasheet V1.3
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8
Electrical characteristic diagrams
Figure 11 Maximum Drain Current vs. Case
Temperature Figure 12 Typical Threshold Voltage vs. Junction
Temperature
Figure 13 Maximum Avalanche Energy vs. Drain Current
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
2
4
6
8
10
12
14
ID, Drain Current (A)
LIMITED BY PACKAGE
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
VGS(th), Gate threshold Voltage (V)
ID = 10µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 1.4A
2.2A
BOTTOM 7.5A
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9
Electrical characteristic diagrams
Figure 14 Typical Avalanche Current vs. Pulse Width
Figure 15 Maximum Eective Transient Thermal Impedance, Junction-to-Case
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.01
0.1
1
10
100
Avalanche Current (A)
0.05
Single Pulse
0.10
Allowed avalanche Current vs avalanche pulsewidth,
tav, assuming Tj =25°C and Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche pulsewidth, tav,
assuming Tj = 150°C and Tstart =25°C (Single Pulse)
Final Datasheet V1.3
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10
Electrical characteristic diagrams
Figure 16 Peak Diode Recovery dv/dt Test Circuit for N-Channel Power MOSFETs
Figure 17a Gate Charge Test Circuit Figure 17b Gate Charge Waveform
Final Datasheet V1.3
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11
Electrical characteristic diagrams
Figure 18a Unclamped Inductive Test Circuit Figure 18b Unclamped Inductive Waveforms
Figure 19a Switching Time Test Circuit Figure 19b Switching Time Waveforms
Final Datasheet V1.3
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IRL80HS120
12
Package Information
5 Package Information
PQFN 2 x 2 Outline Package Details
Note: For the most current drawing please refer to website at : www.irf.com/package/
PQFN 2 x 2 Part Marking
80HS120
For more information on board mounting, including footprint and stencil recommendation, please refer to application note
AN-1136: http://www.infineon.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.infineon.com/technical-info/appnotes/an-1154.pdf
Final Datasheet V1.3
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IRL80HS120
14
† Applicable version of JEDEC standard at the time of product release.
Qualification Information
Qualification Level Industrial
(per JEDEC JESD47F) †
Moisture Sensitivity Level PQFN 2 mm x 2 mm MSL1
(per JEDEC J-STD-020D)†
RoHS Compliant Yes
Qualification Information
6 Qualification Information
Final Datasheet V1.3
2017-06-20
IRL80HS120
15
Revision History
Revision History
Major changes since the last revision
Page or Reference Revision
Date Description of changes
All pages 1.0 2016-09-21 First release data sheet as Provisional.
All pages 1.2 2017-03-29
Parts tested as Unique datasheet with revised current and all other tests
Updated datasheet in new Infineon Template
Datasheet completed and removed “Approved (Not Released)” from
page 1.
All pages 1.1 2016-10-17 Added Switch Time test data.
Datasheet released as Provisional.
All pages 1.3 2017-06-20 Table 5— Idss—Corrected typo error for Vds from 48V to 64V—page 5
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IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
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In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
The data contained in this document is exclusively
intended for technically trained sta. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies oice
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WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies oice.
Except as otherwise explicitly approved by Infineon
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authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
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Edition 2015-05-06
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
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