(MA) MOTOROLA MC6821 PERIPHERAL INTERFACE ADAPTER (PIA) The MC6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the M6800 family of microprocessors. This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be pro- grammed to act as an input or output, and each of the four con- trol/interrupt lines may be programmed for one of several control the interface. @ 8-Bit Bidirectional Data Bus for Communication with the MPU @ Two Bidirectional 8-Bit Buses for Interface to Peripherals @ Two Programmable Control Registers @ Two Programmable Data Direction Registers @ Four Individually-Controlled Interrupt Input Lines; Two Usable as Peripheral Control Outputs @ Handshake Control Logic for Input and Output Peripheral Operation @ High-impedance Three-State and Direct Transistor Drive Peripheral Lines @ Program Controlled Interrupt and Interrupt Disable Capability @ CMOS Drive Capability on Side A Peripheral Lines @ Two TTL Drive Capability on All A and B Side Buffers @ TTL-Compatible @ Static Operation MOS (N-CHANNEL, SILICON-GATE, DEPLETION LOAD) PERIPHERAL INTERFACE ADAPTER modes. This allows a high degree of flexibility in the overall operation of ..-... L SUFFIX CERAMIC PACKAGE CASE 715 S SUFFIX CERDIP PACKAGE CASE 734 P SUFFIX PLASTIC PACKAGE CASE 711 ORDERING INFORMATION Frequency Package Type (MHz) Temperature Order Number Ceramic 1.0 0C to 70C MC6821L L Suffix 1.0 - 40C to 85C MC6821CL 1.5 0C to 70C MC68A21L 1.5 ~ 40C to 85C MCE6BA2ZTCL 2.0 OC to 70C MC68B21L Cerdip 1.0 0C to 70C MC6821S S Suffix 1.0 ~ 40C to 85C MC6821CS 15 0C to 70C MC68A21S 15 - 40C to 85C MC68A21CS 2.0 OC to 70C MC68B21S Plastic 1.0 OC to 70C MC6821P P Suffix 1.0 ~ 40C to 85C MC6821CP 1.5 0C. to 70C MC68A21P 15 - 40C to 85C MC68A21CP 2.0 0C to 70C MC68B21P PIN ASSIGNMENT Vssqie@ \~ 40f] cai PAOL] 2 39 [}cA2 PAID 38 fiRQA PA2C 4 37 piras PA3}5 36f1RSO PA4Q6 35RS1 PASY] 7 PRESET pag 8 33/1 D0 PA7D9 3201 PBOf}I0 3102 Peign 301D3 P8212 29f]04 PB3f}13 28 [JOS Pe4{}14 27 [106 pesgis 261] D7 PB6 G16 25f1E PB7Q17 24f1CS1 ceif}1s 23[CS2 cp2Q19 22f] cso VecH 20 2pR/wMC6821 MAXIMUM RATINGS Characteristics Symbol Value Unit This device contains circuitry to protect the Supply Voltage Vec -0.3 to +7.0 Vv inputs against damage due to high static Input Voltage Vin ~0.3to +70 V vena ee or electric fields; powewer r is ad- - vised that normal precautions be taken to ore ioe. ces821 Ta ot te a c avoid applications of any voltage higher than MC6821C, MCBBA21C -~40 to +85 meximem rated voages to this high- impedance circuit. For proper operation it is Storage Temperature Range Tstg__ | ~ 58 to + 150 C recommended that Vin and Vout be con- Strained to the range GNDs(Vin_ or THERMAL CHARACTERISTICS Vout) S Vcc. Characteristic Symbo! Value Unit Unused inputs must always be tied to an Thermal Resistance appropriate logic voltage level (e.g., either Ceramic 50 GND or Vcc). Plastic GA 100 C/W Cerdip 6 POWER CONSIDERATIONS The average chip-junction temperature, Ty, in C can be obtained from: Ty=Tat(Ppe6ja) (1) Where: , Tas Ambient Temperature, 65 = Package Thermal Resistance, Junction-to-Ambient, C/W Po=PINT + PPORT PiNT#ICC x Vcc, Watts Chip Internal Power PPORT# Port Power Dissipation, Watts User Determined For most applications PpoRT<PinT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between Pp and Ty (if PpoRT is neglected) is: Pp=K+(Ty+273C) (2) Solving equations 1 and 2 for K gives: K=Ppe(Ta + 273C) +6 jasPp2 (3) Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Pp (at equilibrium) for a known Ta. Using this value of K the values of PD and Ty can be obtained by solving equations (1) and (2) iteratively for any value of Ta. DC ELECTRICAL CHARACTERISTICS (Vcc =5.0 Vde +5%, Vss=0, Ta=TL to TH unless otherwise noted). L_ Characteristic | Symbot- [7 Min | Typ | Max | Unit | BUS CONTROL INPUTS (R/W, Enable, RESET, RSO, RS1, CSO, CS1, CS2) Input High Voltage ViH Vsg+2.0 J = Vec vo, Input Low Voltage " VIL Vss-0.3] - | Vss+08] V Input Leakage Current (Vin =0 to 5.25 V) lin - 1.0 25 pA L. Capacitance {Vin=0, Ta = 25C, f= 1.0 MHz) Cin - - 7.5 pF INTERRUPT OUTPUTS (IRGA, IROB) Output Low Voltage (I_oag= 1.6 mA) VOL - - | Vss+04] V Hi-Z Output Leakage Current loz - 1.0 10 BA Capacitance (Vin =0, Ta = 25C, f= 1.0 MHz) Cout - - 5.0 pF DATA BUS (D0-07) Input High Voltage ViH Vss+2.0] Vec Vv Input Low Voltage VIL Vsgg-03]} - |Vsg+08] Vv Hi-Z Input Leakage Current {Vin =0.4 to 2.4 V) lz - 2.0 10 BA Output High Voltage lILoag= - 205 nA Von |Vss+24] = = V 4 Output Low Voltage {ILgag= 1.6 mAl VOL = ~ |Vss+04f Vv a4 Capacitance (Vin =0, Ta = 25C, f= 1.0 MHz) Cin a _ 125 pF 4DC ELECTRICAL CHARACTERISTICS (Continued) [. Characteristic [ Symbol [ Min | Typ | Max | Unit 4} PERIPHERAL BUS (PAO-PA7, PBO-PB7, CA1, CA2, CB1, CB2) Input Leakage Current R/W, RESET, RSO, RS1, CSO, CS1, C52, CAl,] lin _ 10 26 uA (Vin=0 to 5.25 V) CB1, Enable Hi-Z Input Leakage Current (Vip, =0.4 to 2.4 V) PBO-PB7, CB2 \z -_ 2.0 10 BA Input High Current (Vj}4 = 2.4 V) PAO-PA7, CA2 WH - 200 - 400 ~ pA Darlington Drive Current (Vo = 1.5 V) PBO-PB7, CB2 lOH -1.0 ~ -10 mA input Low Current (Vj, = 0.4 V) PAO-PA7, CA2 We - -1.3 -2.4 mA Output High Voltage (ILoad = 200 pA) PAO-PA7, PBO-PB7, CA2,CB2| VoH Vsst24j) | - Vv (Loag= 104A) PAO-PA7, CA2 Vec-10] - - Output Low Voltage (It ogg =3.2 mA) VOL _ - Vgg+04 Vv Capacitance (Vi, =0, Ta = 25C, f=1.0 MHz) Cin - - 10 pF POWER REQUIREMENTS [ Internal Power Dissipation (Measured at T, =0C) | Pint - |[- | 550 mw | BUS TIMING CHARACTERISTICS (See Notes 1 and 2) Number Character Symbol [nine Mac Min: [Max] Mis Rac] UT 1 Cycle Time teye 1.0 | 10 {0.67 | 10 105 | 10 | us 2 Pulse Width, E Low PWe_ | 430 | - | 280 [ [210 | ns 3 Pulse Width, E High PWer | 450 | | 280 [| - | 220 7 ns 4 Clock Rise and Fall Time tr, tf ~ 2a - 3 - 20 | ns 9 Address Hold Time tAH 10 - 10 - 10 - ns 13 Address Setup Time Before E tas & - 60 - 4 - ns 14 Chip Select Setup Time Before E tes 80 - 60 - 40 - ns 18 Chip Select Hold Time tCH 10 - 10 - 10 _ ns 18 Read Data Hold Time toHR | 20 | 5047 20 | 50] 20 | 50] ns 21 Write Data Hold Time toHw | 10 - 10 - 10 Jf - ns 3 Output Data Delay Time toDR -~ | 2] - | 18 | | 150T ns 31 Input Data Setup Time tosw | 165} 80 - 60 - ns The data bus output buffers are no longer sourcing or sinking current by topRmax (High Impedance). FIGURE 1 BUS TIMING 1 R/W, Address {Non-Muxed) cs Read Data MPU Read Data Non-Muxed Non-Muxed Write Data MPU Write Data Non-Muxed Non-Muxed Notes: 1. Voltage levels shown are V_ $0.4 V, Vy22.4 V, unless otherwise specified. 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. 3-309MC6821 PERIPHERAL TIMING CHARACTERISTICS (Vcc =5.0 V +5%. Vgs=0 V, Ta=TL to TH unless otherwise specified) Mi 1 ., | Ref Characteristic Symbol Min Max Nera eT Unit Fig. No. Data Setup Time tpps | 200 | 136 | - 100}; ns 6 Data Hoid Time tPDH 0 - 0 - 0 - ns 6 Delay Time, Enable Negative Transition to CA2 Negative Transition 1CA2 - 1.0 10.670} |0.500] us| 3.7.8 Delay Time, Enable Negative Transition to CA2 Positive Transition Trsj - 1.0} {0.670} 1|0,500 | us 3,7 Rise and Fall Times for CA1 and CA2 input Signals tre, tf - 1.0 - 1.0 - 1.0 | us 8 Delay Time from CA1 Active Transition to CA2 Positive Transition tRS2 - 7420] - | 135] - 1.0 | ws 3,8 Delay Time, Enable Negative Transition to Data Valid tPpW - 1.0 - |0.670| 05 | ws} 3,9, 10 Delay Time, Enable Negative Transition to CMOS Data Valid PAO-PA7, CA2 tcmos | 2.0 - $1.35] 1.0 | ws | 4,9 Delay Time, Enable Positive Transition to CB2 Negative Transition tcB2 - 10] |0.670; - | 0.5 | ws | 3, 11, 12 Delay Time, Data Valid to CB2 Negative Transition toc 20 - 20 - 20 - ns 3, 10 Delay Time, Enable Positive Transition to CB2 Positive Transition tRS1 - 1.0 - |0670) 0.5 | us 3,11 Control Output Pulse Width, CA2/CB2 PWct | 500] - | 375] | 250] - ns 3, 11 Rise and Fal! Time for CB1 and CB2 Input Signals tr, te - 1.0 - 1.0 - 1.0 u 12 Delay Time, CB1 Active Transition to CB2 Positive Transition tRSs2 - |20] - {135} - | 1.0 | us 3, 12 Interrupt Release Time, IROA and iROB tIR - |1.60] | 1.10] - | 085 | ws} 5,14 Interrupt Response Time tRS3 - 1.0 - 1.0 _ 1.0 | us 5, 13 Interrupt input Pulse Time PW) 500 - 500 - 500 - ns 13 RESET Low Time tRL 1.0 - |066] - 0.5 - us 15 *The RESET line must be high a minimum of 1.0 us before addressing the PIA. FIGURE 2 T ; FIGURE 3 TTL EQUIVALENT GURE 2 BUS TIMING TEST LOADS TEST LOAD (00-D7} 5.0V (PAO-PA?, PBOPB7, CA2, CB2) Ry =2.4 kQ 5.0V Test Point MMD6150 Ry = 1.25 kO or Equiv. 7 Test Point MMD6150 Cc Vv or Equiv. 130 pF MMD7000 | or Equiv. c R MMD7000 = = or Equiv. C=30 pF, R=12k FIGURE 4 CMOS EQUIVALENT FIGURE 5 NMOS EQUIVALENT TEST LOAD TEST LOAD (FRO Only) (PAO-PA7, CA2) 5.0 V Test Point ~~] , 1.5 kQ 30 pF [ Test Point = 100 pF IST BR REE EIEN I FTN, hemp sym aren FIGURE 6 PERIPHERAL DATA SETUP AND HOLD TIMES (Read Mode) PAQ-PA7 PBO-PB7 1 'Pps ee tp Oy Enable FIGURE 8 CA2 DELAY TIME (Read Mode; CRA-5= 1, CRA-3= CRA-4=0)} Enabie t | hk wis Ye | pw ty te Ae CcA1 od ha af he TCA? tRS2 CA2 FIGURE 10 PERIPHERAL DATA AND CB2 DELAY TIMES (Write Mode; CRB-5= CRB-3= 1, CRB-4= 0) teow PBO-PB7 ie TOC cB2* *ce2 goes low asa result of the positive transition of Enable. i FIGURE 12 CB2 DELAY TIME (Write Mode; CRB-5= 1, CRB-3= CRB-4=0} fh | itt AF ce: N IL. PLA tcB2 TRS 2 tel cB2 4 * Assumes part was deselected during any previous E pulse. FIGURE 7 CA2 DELAY TIME (Read Mode; CRA-5= CRA3= 1, CRA-4=0) Enabie tCA2 fcc po trst PWert CA2 * Assumes part was deselected during the previous E pulse. FIGURE 9 PERIPHERAL CMOS DATA DELAY TIMES (Write Mode; CRA-5= CRA-3= 1, CRA-4=0) erate / \ 'CMOS-34 fe POW hee torn tre Veo -30% Vcc PAO-PA7, CA2 FIGURE 11 CB2 DELAY TIME (Write Mode; CR8-5= CRB-3= 1, CRB-4=0) Enable trsi* Assumes part was deselected during the previous E pulse. FIGURE 13 INTERRUPT PULSE WIDTH AND IRO RESPONSE ht CA1, 2 cB1,2 LL _ { TRQA/B \ trs3 { * Assumes interrupt Enable Bits are set. Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.MC6821 FIGURE 14 IRQ RELEASE TIME FIGURE 15 RESET LOW TIME i TRL . Enable | RESET \ V _ iR-~ TRO The RESET line must be a Vit for a minimum of 1.0 ws before addressing the PIA. Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. FIGURE 16 EXPANDED BLOCK DIAGRAM 38 40 CAI interrupt Status Control A 39 CA2 Controt Register A D0 33 (CRA) O1 32 Data Direction D2 31 Register 4 (ODRA) 03 30 D4 29 Output Bus O05 28 O06 27 2 PAO Db? 26 Reman 3 PAI Tv (ORA) 4 PA2 Peripheral S PA3 Interface 6 PAG A 4 7 PAS Bus Input 2 Register 3 8 PAG (BER) o 9 PA? Vec Pin 20 10 PBO Vv Pin 1 ss 0! Outpur 11 PBI Register 8 ORB) 12 PB2 cso 22 -~ Peripheral 13 PB3 cs1 24 ~e inrerrace 14 PBA cSt 23 e Chip 15 PBS RSO 36 e{ Select 16 PBE RS1 35. ~ Rw 17 PB? RW 21 Controt Enable 25 -m RESET 34 m Data Direction Control Register B Register B (DORB) (CRB) 18 CBI interrupt Status iRGB 37 Control B 19 CB2PIA INTERFACE SIGNALS FOR MPU The PIA interfaces to the M6800 bus with an 8-bit bidirec- tional data bus, three chip select lines, two register select lines, two interrupt request lines, a read/write line, an enable line and a reset line. To ensure Proper operation with the MC6800, MC6802, or MCBB08 microprocessors, VMA should be used as an active Part of the address decoding. Bidirectional Data (DO-D7) The bidirectional data Jines (D0-D7) allow the transfer of data between the MPU and the PIA. The data bus output drivers are three-state devices that remain in the high-impedance (off) State except when the MPU performs a PIA read Operation. The read/write line is in the read (high) state when the PIA is selected for a read operation. Enable (E) The enable Pulse, E, is the only timing signal that is supplied to the PIA. Timing of all other signais is referenced to the leading and trailing edges of the E pulse. Read/Write (R/W) This signal is generated by the MPU to control the direction of data transfers on the data bus. A iow state on the PIA read/write line enables the input buffers and data is transferred from the MPU to the PIA on the E signal if the device has been selected. A high on the read/write line sets up the PIA for a transfer of data to the bus. The PIA output buffers are enabled when the proper ad- dress and the enable pulse E are present. RESET The active low RESET line is used to reset all register bits in the PIA toa logical zero (low). This line can be used as a power-on reset and as @ master reset during system operation. Chip Selects (CSO, CS1, and CS2) ~ These three input Signals are used to select the PIA. CSO and CS1 must be high and CSZ must be low for selection of the device. Data transfers are then performed under the control of the enable and read/write signals. The chip select lines must be stable for the duration of the E pulse. The device is deselected when any of the chip selects are in the inactive State. Register Selects (RSO and RS1) The two register Select lines are used to select the various registers inside the PIA. These two lines are used in conjunction with internal Control Registers to select a Particular register that is to be written or read. The register and chip select lines should be stable for the duration of the E pulse while in the read or write cycle. Interrupt Request {IRQA and IROB) The active low In- terrupt Request lines (ROA and iROB) act to interrupt the MPU either directly or through interrupt Priority circuitry, These lines are open drain (no load device on the chip). This permits all interrupt request lines to be tied together in a wire-OR configuration, Each Interrupt Request line has two internal interrupt flag bits that can cause the Interrupt Request line to go low. Each flag bit is associated with a particular peripheral interrupt line. Also, four interrupt enable bits are provided in the PIA which may be used to inhibit 4 Particular interrupt from a peripheral device. Servicing an interrupt by the MPU may be accomplished by a software routine that, ona prioritized basis, sequentially reads and tests the two control registers in each PIA for in- terrupt flag bits that are set. The interrupt flags are cleared (zeroed) as a result of an MPU Read Peripheral Data Operation of the corresponding data register. After being cleared, the interrupt flag bit can- not be enabled to be set until the PIA is deselected during an E pulse. The E pulse is used to condition the interrupt control lines (CA1, CA2, CB1, CB2). When these lines are used as interrupt inputs, at least one E pulse. must occur from the in- active edge to the active edge of the interrupt input signal to condition the edge sense network. If the interrupt flag has been enabled and the edge sense circuit has been properly conditioned, the interrupt flag will be set on the next active transition of the interrupt input pin. PIA PERIPHERAL INTERFACE LINES The PIA provides two 8-bit bidirectional data buses and four interrupt/control lines for interfacing to peripheral devices. Section A Peripheral Data (PAO-PA7) Each of the peripheral data lines can be Programmed to act as an input or output. This is accomplished by setting a 1" in the cor- responding Data Direction Register bit for those lines which are to be outputs. A 0 in a bit of the Data Direction Register causes the Corresponding peripheral data line to act as an input. During an MPU Read Peripheral Data Operation, the data on peripheral lines Programmed to act as inputs ap- pears directly on the corresponding MPU Data Bus lines. tn the input mode, the internal pullup resistor on these lines represents a maximum of 1.5 standard TTL loads. The data in Output Register A will appear on the data lines that are programmed to be outputs. A logical 1" written in- to the register will cause a high on the corresponding data line while a 0 results in a low. Data in Output Register A may be read by an MPU Read Peripheral Data A Operation when the corresponding lines are Programmed as outputs. This data will be read properly if the voltage on the peripheral data lines is greater than 2.0 volts for a logic "1" Outputand less than 0.8 volt fora logic 0 output. Loading the output lines such that the voltage on these lines does not reach full voltage causes the data transferred into the MPU on a Read operation to differ from that contained in the respective bit of Output Register A. Section B Peripheral Data (PBO-PB7) The peripheral data lines in the B Section of the PIA can be programmed to act as either inputs or Outputs in a similar manner to PAO- PA7. They have three-state Capabiity, allowing them to enter a high-impedance state when the peripheral data line is used aS an input. In addition, data on the peripheral data linesMC6821 PBO-PB7 will be read properly from those lines programmed as Outputs even if the voltages are below 2.0 volts for a high or above 0.8 V for a low. As outputs, these lines are compatible with standard TTL and may also be used as a source of at least 1 milliampere at 1.5 volts to directly drive the base of a transistor switch. Interrupt Input (CA1 and CB1) Peripheral input lines CA and CB1 are input only lines that set the interrupt flags of the control registers. .The active transition for these signals is also programmed by the two control registers. Peripheral Control (CA2) The peripheral control line CA2 can be programmed to act as an interrupt input or as a peripheral control output. As an output, this line is compati- ble with standard TTL; as an input the internal pullup resistor on this line represents 1.5 standard TTL loads. The function of this signal line is programmed with Control Register A. Peripheral Control (CB2) Peripheral Contro! line CB2 may also be prograrnmed to act as an interrupt input or peripheral control output. As an input, this line has high in- Put impedance and is compatible with standard TTL. As an output it is compatible with standard TTL and may also be used as a source of up to 1 milliampere at 1.5 volts to directly drive the base of a transistor switch. This line is programmed by Control Register B. INTERNAL CONTROLS INITIALIZATION A RESET has the effect of zeroing all PIA registers. This will set PAO-PA7, PBO-PB7, CA2 and CB2 as inputs, and all interrupts disabled. The PIA must be configured during the restart program which follows the reset. There are six locations within the PIA accessible to the MPU data bus: two Peripheral Registers, two Data Direction Registers, and two Control Registers. Selection of these locations is controlled by the RSO and RS1 inputs together with bit 2 in the Control Register, as shown in Table 1. Details of possible configurations of the Data Direction and Control Register are as follows: TABLE 1 - INTERNAL AODRESSING Control Register Bit RS1| RSO | CRA-.2 | CRB-2 Location Selected 0 0 1 x Peripheral Register A 0 0 0 xX Data Direction Register A 0 1 x x Control Register A 1 0 x 1 Peripheral Register 8 1 0 x 0 Data Direction Register 8 1 1 x x Control Register 8 X = Dont Care PORT A-B HARDWARE CHARACTERISTICS As shown in Figure 17, the MC6821 has a pair of I/O ports whose characteristics differ greatly. The A side is designed to drive CMOS logic to normal 30% to 70% levels, and incor- porates an internal pullup device that remains connected even in the input mode. Because of this, the A side requires more drive current in the input mode than Port 8. In con- trast, the B side uses a normal three-state NMOS buffer which cannot pullup to CMOS tevels without external resistors. The B side can drive extra loads such as Darl- ingtons without problem. When the PIA comes out of reset, the A port represents inputs with pullup resistors, whereas the B side (input mode also) will float high or low, depending upon the load connected to it. Notice the differences between a Port A and Port B read operation when in the output mode. When reading Port A, the actual pin is read, whereas the B side read comes from an output latch, ahead of the actual pin. CONTROL REGISTERS (CRA and CRB) The two Control Registers (CRA and CRB) allow the MPU to control the operation of the four peripheral control lines CA1, CA2, CB1, and CB2. In addition they allow the MPU to enable the interrupt lines and monitor the status of the inter- rupt flags. Bits 0 through 5 of the two registers may be writ- ten or read by the MPU when the proper chip select and register select signals are applied. Bits 6 and 7 of the two registers are read only and are modified by external interrupts occurring on control lines CA1, CA2, CB1, or CB2. The for- mat of the control words is shown in Figure 18. DATA DIRECTION ACCESS CONTROL BIT (CRA-2 and CRB-2) Bit 2, in each Control Register (CRA and CRB), deter- mines selection of either a Peripheral Output Register or the corresponding Data Direction E Register when the proper register select signals are applied to RSO and RS1. A'1" in bit 2 allows access of the Peripheral Interface Register, while a "0" causes the Data Direction Register to be addressed. Interrupt Flags (CRA-6, CRA-7, CRB-6, and CRB-7) The four interrupt flag bits are set by active transitions of signals on the four Interrupt and Peripheral Control lines when those lines are programmed to be inputs. These bits cannot be set directly from the MPU Data Bus and are reset indirectly by a Read Peripheral Data Operation on the ap- propriate section. Control of CA2 and CB2 Peripheral Control Lines (CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, and CRB-5) Bits 3, 4, and 5 of the two control registers are used to control the CA2 and CB2 Peripheral Control lines. These bits determine if the con- trol lines will be an interrupt input or an output control signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2) is an interrupt input line similar to CA1 (CB1}. When CRA-5 (CRB-5) is high, CA2 (CB2) becomes an output signal that may be used to control peripheral data transfers. When in the output mode, CA2 and CB2 have slightly different loading characteristics.Control of CA1 and CB1 Interrupt Input Lines (CRA-O, enable the MPU interrupt signals TROA and IROB, respec- CRB-0, CRA-1, and CRB-1) ~ The two lowest-order bits of tively. Bits CRA-1 and CRB-1 determine the active transition the control registers are used to control the interrupt input of the interrupt input signals CA1 and CB1. lines CA1 and CB1. Bits CRA-O and CRB-O are used to FIGURE 17 ~ PORT A AND PORT B EQUIVALENT CIRCUITS PortA Port B Voc Vcc DATA + Port Pin Data Direction Port Pin Data j DATA Direction (1-eOutput Pin) Data Direction (O-einput Pin) {0 input Pin) (1-Output Pin) Read of 8 Data When in Output Mode Read A Data To External in Input or Bus Output Mode 1 - Internal PIA Bus) ORDERING INFORMATION . Read of B Data when in Input Mode MC68A21CP Motorola Integrated Circuit _ | M6800 Family Blanks= 1.0 MHz A=1,5 MHz B=2.0 MHz Device Designation In M6800 Family Temperature Range Blank = 0 + 70C C= 40 + 85C Package P = Plastic $= Cerdip L= Ceramic BETTER PROGRAM Better program processing is available on all types listed. Add suffix letters to part number. Level taddS Level2 add "D" ~ Level 3.add DS Level 1 S"'=10 Temp Cycles (- 26 to 180C): Hi Temp testing at Ta max. Level 2 'D' = 168 Hour Burn-in at 125C Level 3 OS = Combination of Level 1 and 2.MC6821 Determine Active CA1 (CB1) Transition for Setting Interrupt Flag ROA(B)1 (bit 7) bi=0: IRQA(B)1 set by high-to-low transition on CAI (CB1} bl=1: IRQA(B)1 set by low-to-high transition on CA1 (CBI). IRQA(8) 1 Interrupt Fiag (bit 7) Goes high on active transition of CA} (CB1); Automa- tically cleared by MPU Read of Output Register A(B). May also be cleared by hardware Reset. I FIGURE 18 ~ CONTROL WORD FORMAT CA1 (CB1) Interrupt Request Enable/Disable bO=0: Disables IRQA(B) MPU Interrupt by CA1 (CB1) active transition. bO=1: Enable ROA(B} MPU interrupt by CA1 (CB1) active transition. 1. IRQA(B) will oceur on next (MPU generated) positive transition of b0 if CA1 (CB1) active transition oc- curred while interrupt was disabled. i_ a ee b7 b6 b5 b4 b3 b2 b1 | b0 Control Register [agaipit | IROA(BI2 CA2 (CB2) DDR CA1 (CB1) Flag Flag Control Access Control IRQA(8)2 interrupt Flag (bit 6) When CA2 (CB2) is an input, IROA(B) goes high on ac- tive transition CA2 (CB2): Automatically cleared by MPU Read of Output Register A(B). May also be cleared by hardware Reset. CA2 (CB2) Established as Output (b5= 1): IRQAIB) 2=0, not affected by CA2 (CB2) transitions. Determines Whether Data Direction Register Or Output Register is Addressed b2=0: Data Direction Register selected. b2=1: Output Register selected. | 4 CA2 (CB2) Established as Output by b5=1 (Note that operation of CA2 and CB2 output b5 b4 b3 functions are not identical) CA2 1 0 b3=0: Read Strobe with CA1 Restore CA2 goes low on first high-to-low E transition following an MPU read of Output Register A; returned high by next active CA1 transition, as specified by bit 1. b3= 1: Read Strobe with E Restore CA2 goes low on first high-to-low E transition following an MPU read of Output Register A; returned high by next high-to-low E transition dur- ing a deselect. j> CB2 b3=0: Write Strobe with CB1 Restore CB2 goes low on first low-to-high E transition following an MPU write into Output Register 8; returned high by the next active CB1 transi- tion as specified by bit 1. CRB-b7 must first be cleared by a read of data. b3=1: Write Strobe with E Restore CB2 goes low on first low-to-high E transition following an MPU write into Output Register B: returned bS b4 b3 high by the next low-to-high E tran- sition following an E pulse which occurred while the part was de- selected. 11 Set/Reset CA2 (CB2) CA2 (CB2) goes low as MPU writes b3=0 into Control Register. CA2 (CB2) goes high as MPU writes b3= 1 into Control Register. CA2 (CB2) Established as Input by b5=0 5 b4 b3 0 L CA2 (CB2) Interrupt Request Enable/Disable b3=0: Disables IROA(B) MPU Interrupt by CA2 (CB2) active transition. * b3=1: Enables IROA(B) MPU Interrupt by CA2 (CB2) active transition. *IRQA(B) will occur on next (MPU generat- ted) positive transition of b3 if CA2 (CB2) active transition occurred while interrupt was disabled. Determines Active CA2 (C82) Transition for Setting Interrupt Fiag IROA(B)2 (Bit b6) b4=0: IRQA(B)2 set by high-to-low transi- tion on CA2 (CB2). b4=1: IRQA(B)2 set by low-to-high transi- tion on CA2 (CB2).