Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
ADCMP606/ADCMP607
Rev. A
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FEATURES
Fully specified rail to rail at VCCI = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCCI + 0.2 V
CML-compatible output stage
1.25 ns propagation delay
50 mW @ 2.5 V power supply
Shutdown pin
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP606 and ADCMP607 are very fast comparators
fabricated on XFCB2, an Analog Devices, Inc., proprietary
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from VEE − 0.5 V to
VCCI + 0.2 V, low noise, CML-compatible output drivers, and
TTL-/CMOS-compatible latch inputs with adjustable hysteresis
and/or shutdown inputs.
The devices offer 1.25 ns propagation delay with 2.5 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.7 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to
support a wide input signal range with independent output
swing control and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, latch and programmable hysteresis features are
also provided with a unique single-pin control option.
The ADCMP606 is available in a 6-lead SC70 package and the
ADCMP607 is available in a 12-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
N
INVERTING
INPUT
S
DN
INPUT (ADCMP607 ONLY)
V
CCI
V
CCO
(ADCMP607 ONLY)
Q OUTPUT
Q OUTPUT
LE/HYS INPUT (ADCMP607 ONLY)
ADCMP606/
ADCMP607
CML
05917-001
Figure 1.
ADCMP606/ADCMP607
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Information ..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Application Information................................................................ 10
Power/Ground Layout and Bypassing..................................... 10
CML-Compatible Output Stage ............................................... 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 10
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Points................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
8/07—Rev. 0 to Rev. A
Changes to Specifications Section.................................................. 3
Changes to Table 3............................................................................ 6
Changes to Ordering Guide .......................................................... 14
10/06—Revision 0: Initial Version
ADCMP606/ADCMP607
Rev. A | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = −40°C to +125°C, typical at TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range VP, VN V
CCI = 2.5 V to 5.5 V −0.5 VCCI + 0.2 V
Common-Mode Range VCCI = 2.5 V to 5.5 V −0.2 VCCI + 0.2 V
Differential Voltage VCCI = 2.5 V to 5.5 V VCCI V
Offset Voltage VOS −5.0 +5.0 mV
Bias Current IP, IN −5.0 ±2 +5.0 µA
Offset Current −2.0 2.0 µA
Capacitance CP, CN 1 pF
Resistance, Differential Mode −0.1 V to VCCI 200 700 kΩ
Resistance, Common Mode −0.5 V to VCCI + 0.5 V 100 350 kΩ
Active Gain AV 85 dB
VCCI = 2.5 V, VCCO = 2.5 V,
VCM = −0.2 V to +2.7 V
50 dB Common-Mode Rejection Ratio CMRR
VCCI = 2..5 V, VCCO = 5.5 V 50 dB
Hysteresis RHYS = ∞ <0.1 mV
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP607 Only)
VIH Hysteresis is shut off 2.0 VCCO V
VIL Latch mode guaranteed −0.2 +0.4 +0.8 V
IIH V
IH = VCCO −6 +6 µA
IIL V
IL = 0.4 V −0.1 +0.1 mA
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage Current sink 0 A 1.145 1.25 1.35 V
Minimum Resistor Value Hysteresis = 120 mV 55 75 110 kΩ
Latch Setup Time tS V
OD = 50 mV −1.5 ns
Latch Hold Time tH V
OD = 50 mV 2.3 ns
Latch-to-Output Delay tPLOH, tPLOL V
OD = 50 mV 30 ns
Latch Minimum Pulse Width tPL V
OD = 50 mV 25 ns
SHUTDOWN PIN CHARACTERISTICS
(ADCMP607 Only)
VIH Comparator is operating 2.0 VCCO V
VIL Shutdown guaranteed −0.2 +0.4 +0.6 V
IIH V
IH = VCCO −6 +6 µA
IIL V
IL = 0 V −0.1 mA
Sleep Time tSD 10% output swing <1 ns
Wake-Up Time tH V
OD = 100 mV, output valid 35 ns
DC OUTPUT CHARACTERISTICS VCCO = 2.5 V to 5.5 V
Output Voltage High Level VOH 50 Ω terminate to VCCO VCCO − 0.1 VCCO − 0.05 VCCO V
Output Voltage Low Level VOL 50 Ω terminate to VCCO V
CCO − 0.6 VCCO − 0.45 VCCO − 0.3 V
Output Voltage Differential 50 Ω terminate to VCCO 300 400 500 mV
ADCMP606/ADCMP607
Rev. A | Page 4 of 16
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE1
Rise Time/Fall time tR/tF 10% to 90%,
VCCI = VCCO = 2.5 V to 5.5 V
160 ps
Propagation Delay tPD VCCI = VCCO = 2.5 V to 5.5 V,
VOD = 50 mV
1.2 ns
VCCI = VCCO = 2.5 V,
VOD = 10 mV
2.1 ns
Propagation Delay Skew—Rising to
Falling Transition
TPINSKEW VOD = 50 mV 40 ps
Overdrive Dispersion 10 mV < VOD < 125 mV 2.3 ns
Common-Mode Dispersion −0.2 V < VCM < VCC + 0.2 V 150 ps
Input Stage Bandwidth 750 MHz
RMS Random Jitter RJ VOD = 200 mV, 0.5 V/ns 2 ps
Minimum Pulse Width PWMIN VCCI = VCCO = 5.5 V,
PWOUT = 90% of PWIN
1.1 ns
Output Skew Q to QTDIFFSKEW 50% 20 ps
POWER SUPPLY
Input Supply Voltage Range VCCI 2.5 5.5 V
Output Supply Voltage Range VCCO 2.5 5.5 V
Positive Supply Differential (ADCMP607) VCCI − VCCO Operating −3.0 +3.0 V
V
CCI − VCCO Nonoperating −6 +6 V
Positive Supply Current (ADCMP606) IVCCI/VCCO V
CCI = VCCO = 2.5 V 11 17.5 21 mA
V
CCI = VCCO = 5.5 V 16 20.5 26 mA
Input Section Supply Current (ADCMP607) IVCCI V
CCI = 2.5 V 0.5 1.1 1.5 mA
Output Section Supply Current (ADCMP607) IVCCO V
CCO = 2.5 V 10 15.8 18 mA
I
VCCO V
CCO= 5.5 V 16 18 25 mA
Power Dissipation PD V
CCI = VCCO = 2.5 V 30 46 55 mW
P
D V
CCI = VCCO = 5.5 V 90 110 150 mW
Power Supply Rejection Ratio PSRR VCCI = 2.5 V to 5 V −50 dB
Shutdown Mode ICCI VCCI = VCCO = 2.5 V to 5 V 200 240 800 µA
Shutdown Mode ICCO V
CCI = VCCO = 2.5 V to 5 V −30 30 µA
1 VIN = 100 mV square input at 50 MHz, VCM = 2.5 V, VCCI = VCCO = 2.5 V, unless otherwise noted.
ADCMP606/ADCMP607
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
V
N
± V
OS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
t
H
t
PDL
t
PLOH
t
F
V
IN
V
OD
t
S
t
PL
50%
Q OUTPUT
t
PDH
t
PLOL
t
R
05917-025
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol Timing Description
tF Output fall time Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
tH Minimum hold time Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPDH Input to output high delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL Input to output low delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPL Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal
change.
tPLOH Latch enable to output high delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL Latch enable to output low delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tR Output rise time Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
tS Minimum setup time Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
VOD Voltage overdrive Difference between the input voltages VA and VB.
ADCMP606/ADCMP607
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltages
Input Supply Voltage (VCCI to GND) −0.5 V to +6.0 V
Output Supply Voltage
(VCCO to GND)
−0.5 V to +6.0 V
Positive Supply Differential
(VCCI − VCCO)
−6.0 V to +6.0 V
Input Voltages
Input Voltage −0.5 V to VCCI + 0.5 V
Differential Input Voltage ±(VCCI + 0.5 V)
Maximum Input/Output Current ±50 mA
Shutdown Control Pin
Applied Voltage (SDN to GND) −0.5 V to VCCO + 0.5 V
Maximum Input/Output Current ±50 mA
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND) −0.5 V to VCCO + 0.5 V
Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA1 Unit
ADCMP606 6-Lead SC70 426 °C/W
ADCMP607 12-Lead LFCSP 62 °C/W
1 Measurement in still air.
ESD CAUTION
ADCMP606/ADCMP607
Rev. A | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Q
1
V
EE 2
V
P3
Q
6
V
CCI
/V
CCO
5
V
N
4
ADCMP606
TOP VIEW
(Not to Scale)
05917-002
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADCMP607
V
CCO
1
V
CCI
2
V
EE
3
V
P
4
V
EE
5
V
N
6
9 V
EE
8 LE/HYS
7 S
DN
12 Q
11 V
EE
10 Q
05917-003
Figure 3. ADCMP606 Pin Configuration Figure 4. ADCMP607 Pin Configuration
Table 5. ADCMP606 (6-Lead SC70) Pin Function Descriptions
Pin No. Mnemonic Description
1 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN.
2 VEE Negative Supply Voltage.
3 VP Noninverting Analog Input.
4 VN Inverting Analog Input.
5 VCCI/VCCO Input Section Supply/Output Section Supply. Shared pin.
6 QInverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VIN.
Table 6. ADCMP607 (12-Lead LFCSP) Pin Function Descriptions
Pin No. Mnemonic Description
1 VCCO Output Section Supply.
2 VCCI Input Section Supply.
3 VEE Negative Supply Voltage.
4 VP Noninverting Analog Input.
5 VEE Negative Supply Voltage.
6 VN Inverting Analog Input.
7 SDN Shutdown. Drive this pin low to shut down the device.
8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
9 VEE Negative Supply Voltage.
10 QInverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, if the comparator is in compare mode.
11 VEE Negative Supply Voltage.
12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, if the comparator is in compare mode.
Heat Sink
Paddle
VEE The metallic back surface of the package is electrically connected to VEE. It can be left floating because
Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the
application board if improved thermal and/or mechanical stability is desired.
ADCMP606/ADCMP607
Rev. A | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
CURRENT (µA)
–800
–600
–400
–200
0
200
400
600
800
LE/HYS PIN (V)
–101 23456 7
05917-026
VCC = 5.5VVCC = 2.5V
Figure 5. LE/HYS Pin Current vs. Voltage
CURRENT (µA)
SDN PIN (V)
–150
–100
–50
0
50
100
150
200
–1 0 1 2 3 4 5 6 7
VCC = 5.5VVCC = 2.5V
05917-007
Figure 6. SDN Pin Current vs. Voltage
I
B
(µA)
V
CM
AT V
CC
= 2.5V
–10
–8
–6
–4
–2
0
2
4
6
8
10
+125°C
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
05917-006
–40°C
+25°C
Figure 7. Input Bias Current vs. Input Common-Mode Voltage
0
50
100
150
200
250
HYSTERESIS (mV)
0 –2 –4 –6 –8 –10 –12 –14 –16 –18
LE/HYS PIN CURRENT (µA)
+25°C
+125°C
–40°C
05917-004
Figure 8. Hysteresis vs. LE/HYS Pin Current
HYSTERESIS (mV)
HYS RESISTOR (kΩ)
0
50
100
150
200
250
300
350
400
50 100 150 200 250 300 350 400 450 500 550 600 650
VCC = 2.5V
05917-005
Figure 9. Hysteresis vs. Hysteresis Resistor
PROPAGATION DELAY (ns)
OVERDRIVE (mV)
1.0
1.5
2.0
2.5
3.0
3.5
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
PROPAGATION DELAY RISE
PROPAGATION DELAY FALL
05917-009
Figure 10. Propagation Delay vs. Input Overdrive
ADCMP606/ADCMP607
Rev. A | Page 9 of 16
PROPAGATION DELAY (ns)
VCM AT VCC = 2.5V
1.1
1.2
1.3
1.4
–0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0
PROPAGATION DELAY FALL ns
PROPAGATION DELAY RISE ns
05917-010
Figure 11. Propagation Delay vs. Input Common-Mode Voltage
05917-011
2.050V 1.000ns/DIV
2.550V
Q
Q
Figure 12 .Output Waveform at VCC = 2.5 V
0
5917-012
Q
Q
5.050V 1.000ns/DIV
5.550V
Figure 13. Output Waveform at VCC = 5.5 V
ADCMP606/ADCMP607
Rev. A | Page 10 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP606/ADCMP607 comparators are very high speed
devices. Despite the low noise output stage, it is essential to use
proper high speed design techniques to achieve the specified
performance. Because comparators are uncompensated amplifiers,
feedback in any phase relationship is likely to cause oscillations
or undesired hysteresis. Of critical importance is the use of low
impedance supply planes, particularly the output supply plane
(VCCO) and the ground plane (GND). Individual supply planes
are recommended as part of a multilayer board. Providing the
lowest inductance return path for switching currents ensures
the best possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the VCCI and VCCO pins. High frequency bypass capacitors
should be carefully selected for minimum inductance and ESR.
Parasitic layout inductance should also be strictly controlled to
maximize the effectiveness of the bypass at high frequencies.
CML-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved by using proper transmission line terminations. The
outputs of the ADCMP606 and ADCMP607 are designed to drive
400 mV directly into a 50 Ω cable or into transmission lines
terminated using either microstrip or strip line techniques with
50 Ω referenced to VCCO. The CML output stage is shown in the
simplified schematic diagram in Figure 14. Each output is back-
terminated with 50 Ω for best transmission line matching.
Q
16mA
50Ω
Q
V
CCO
GND
05917-013
Figure 14. Simplified Schematic Diagram of
CML-Compatible Output Stage
If these high speed signals must be routed more than a centimeter,
then either microstrip or strip line techniques are required to
ensure proper transition times and to prevent excessive output
ringing and pulse width dependent propagation delay
dispersion.
It is also possible to operate the outputs with the internal
termination only if greater output swing is desired. This can be
especially useful for driving inputs on CMOS devices intended
for full swing ECL and PECL, or for generating pseudo PECL
levels. To avoid deep saturation of the outputs and resulting
pulse dispersion, VCCO must be kept above the specified
minimum output low level (see the Electrical Characteristics
section). The line length driven should be kept as short as
possible.
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can
safely be left floating or it can be driven low by any standard
TTL/CMOS device as a high speed latch.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 70 kΩ. This allows the comparator hysteresis to
be easily controlled by either a resistor or an inexpensive CMOS
DAC. Driving this pin high or floating the pin removes all
hysteresis.
Hysteresis control and latch mode can be used together if an
open-drain, an open-collector, or a three-state driver is con-
nected parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of VCCO.
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.
ADCMP606/ADCMP607
Rev. A | Page 11 of 16
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP606/ADCMP607 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to VCCI − 1 V. Propagation delay dispersion is the
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (that is, how far or how fast the
input signal exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 15
and Figure 16).
The device dispersion is typically 2.3 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both
positive and negative signals because each device has very closely
matched delays for positive-going and negative-going inputs as
well as very low output skews.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
10mV OVERDRIVE
DISPERSION
V
N
± V
OS
05917-014
Figure 15. Propagation Delay—Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
05917-015
Figure 16. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in
a noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 17 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0 V, in this example) from below the
threshold region in a positive direction, the comparator switches
from low to high when the input crosses +VH/2, and the new
switching threshold becomes −VH/2. The comparator remains in
the high state until the new threshold, −VH/2, is crossed from
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±VH/2.
OUTPUT
INPUT
0
V
OL
V
OH
+V
H
2
–V
H
2
05917-016
Figure 17. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to
the input. One limitation of this approach is that the amount
of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
This ADCMP607 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND, varies the amount of hysteresis
in a predictable, stable manner. Leaving the LE/HYS pin discon-
nected or driving this pin high removes hysteresis. The maximum
hysteresis that can be applied using this pin is approximately
160 mV. Figure 18 illustrates typical hysteresis applied as a
function of the external resistor value, and Figure 7 illustrates
typical hysteresis as a function of the current.
HYSTERESIS (mV)
HYS RESISTOR (kΩ)
0
50
100
150
200
250
300
350
400
50 100 150 200 250 300 350 400 450 500 550 600 650
VCC = 2.5V
05917-017
Figure 18. Hysteresis vs. RHYS Control Resistor
ADCMP606/ADCMP607
Rev. A | Page 12 of 16
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis in
this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the LE/HYS pin because it
impairs the latch function and often degrades the jitter perform-
ance of the device. As described in the Using/Disabling the
Latch Feature section, hysteresis control need not compromise
the latch function.
CROSSOVER BIAS POINTS
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCCI rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCCI/2, the direction of the bias current
reverses and the measured offset voltages and currents change.
The ADCMP606/ADCMP607 comparators slightly elaborate
on this scheme. Crossover points are found at approximately
0.6 V and 1.6 V common mode.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or poor
bypassing, oscillation is observed. This oscillation is due to the
high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PC board. In many
applications, chattering is not harmful.
ADCMP606/ADCMP607
Rev. A | Page 13 of 16
TYPICAL APPLICATION CIRCUITS
ADCMP606
CML
OUTPUT
0.1µF
2.5V TO 5
V
0.1µF
2kΩ
2kΩ
INPUT
50Ω50Ω
05917-018
Figure 19. Self-Biased, 50% Slicer
ADCMP606
100Ω
50Ω50Ω
LVDS CML
OUTPUT
3.3
V
05917-019
Figure 20. LVDS to CML
LE/HYS
ADCMP607
5
V
82pF
10kΩ
10kΩ
10kΩ
C
ONTROL
CURRENT
CML
OUTPUT
50Ω50Ω
05917-020
Figure 21. Current-Controlled Oscillator
ADCMP607
100Ω
50Ω50Ω
LVDS 3.3V
PECL
VCCO
1N4001
VCCI
3.3
05917-021
Figure 22. Fake PECL Levels Using a Series Diode
INPUT
2.5V
REF
INPUT
2.5V
±
50m
V
LE/HYS
ADCMP601
150pF
10kΩ
10kΩ
100kΩ
10kΩ
ADCMP606
5
V
CML
PWM
OUTPUT
50Ω50Ω
05917-022
Figure 23. Oscillator and Pulse-Width Modulator
150kΩ
150kΩ
LE/HYS
DIGITAL
INPUT
CONTROL
VOLTAGE
0V TO 2.5
V
74 VHC
1G07
ADCMP607
50Ω50Ω
2.5V TO 5
V
05917-023
Figure 24. Hysteresis Adjustment with Latch
ADCMP607
50Ω50Ω
OUTPUT
V
CCO
+2.5V – 3
V
V
CCI
–2.5V
V
EE
05917-024
Figure 25. Ground-Referenced CML with ±3 V Input Range
ADCMP606/ADCMP607
Rev. A | Page 14 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AB
0.22
0.08
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
4 5 6
3 2 1
PIN 1
0.65 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
0.40
0.10
1.10
0.80
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
0.46
0.36
0.26
Figure 26. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
1
0.50
BSC
0.60 MAX PIN 1
INDICATOR
0.75
0.55
0.35
0.25 MIN
0.45
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
*1.45
1.30 SQ
1.15
12
4
10
6
7
9
3
2.75
BSC SQ
3.00
BSC SQ
2
5
8
11
COPLANARITY
0.08
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
Figure 27. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description
Package
Option Branding
ADCMP606BKSZ-R21−40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0S
ADCMP606BKSZ-RL1−40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0S
ADCMP606BKSZ-REEL71−40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0S
ADCMP607BCPZ-R21−40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0H
ADCMP607BCPZ-R71−40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0H
ADCMP607BCPZ-WP1−40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0H
1 Z = RoHS Compliant Part.
ADCMP606/ADCMP607
Rev. A | Page 15 of 16
NOTES
ADCMP606/ADCMP607
Rev. A | Page 16 of 16
NOTES
©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05917-0-8/07(A)