DS90CR215/DS90CR 216 Link - 66 MHz General Description The DS80CR?15 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTLdata are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Lang distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With ihe Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces con- nestor physical size and cost, and reduces shielding require- ments due to the cables smaller form factor. March 1998 National Semiconductor +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control. Features Single +3.3V supply Chipset (Tx + Rx) power consumption <250 mW (typ) Power-down mode (<0.5 mW total) Up to 173 Megabytes/sec bandwidth Up to 1.386 Gbps data throughput Narrow bus reduces cable size 290 mV swing LVDS devices for low EMI +1V common mode range (around +1.2V) PLL requires no external components Low profile 481ead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard ESD Rating > 7 kV Block Diagrams DS90CR215 DATA (LYDS) w a = 2 o . . r (140 To 462 Mait/s SMOS/TTL _ a On Each LYDS INPUTS a Channel) * a a 7 2 Ee clock {LVDS} TRANSMIT CIOCK IN (20 Ta 66 KHz) (20 To 66 MHz) POWFR DOWN 080129081 Order Number DS90CR215MTD See NS Package Number MTD48 TRI-STATE is a registered trademark of National Semiconductor Corporation. DS90CR216 bata (LYDS) 4 (140 To 482 Mbis/ 3 , Res a 21 On bach LYDS _| = 7 cos /TTL Caan asl} 7 OUTPUTS 4 = 7 wn 4 3 bat (2a to ee 7] i RECEIVER CLOCK OUT PH POWER GOWN Dso12s027 Order Number DS90CR216MTD See NS Package Number MTD48 1998 National Semiconductor Corporation Dsoi2909 www.national.com ZHW 99-4Ul7 J@UUBYD IG-LZ SCAT eqous Beg eBpyz Bulsiy Age+ 91ZHOOGSAC/SLZHDOESGPin Diagrams TxIN4 Vee TxINS TxIN6 GND TxIN? TxIN& Yoo TxING TxIN 10 CND TxIN 11 TxIN 1 2 Yoo TxIN13 TxIN 14 GND TRIN TS IxIN18 TxIN 17 Yoo TxIN 13 TxlIN19 GND TTL PARALLEL-TO-LYDS 27 DS90CR215 Typical Application TX DS9OCR215 TxIN cMos/ hoe Owe TxCLK PWR DWN TxIN3 TxIN2 GND TxIN1 TxINO N/C LVDS GND TxOUTO TxOUTO+ TxOUT I= TXOUT 1 + LYDS , LYDS GND TxOUT2 - TxOUT2 + TxCLK OUTS TxCLK OUTH LVDS GND PLL GND PLL oe PLL GND TxCLK IN TxIN2O DS01290821 LDS Cable {media dependent) SHIELD RxOUT17 RxOUT 18 GND RXOUT 19 RxOUT20 n/c LVDS GND RxlINO- RxINO + Ral 1 - RxiN1 + LYDS og LVDS GND RxIN2= RxINZ + RxCLK IN- RxCLK IN+ LVDS GND PLL GND PLL PLL GND PWR DWN RxCLK QUT RxOUTO DaTA (LYDS) CLOCK {LDS} 1 fray a xt ue = a 4 l Q i ' wn a = 3 DS90CR216 RX DS9OCR216 B sc ReOUT16 RxOUT15 RxOUT 14 GND RxOUT13 Voc RxOUT12 ROUT 11 RxOUT10 GND RxQUTS cc RrOUTS RKOUTT RxOUT6 GND RxOUTS RxOUT4 RxOUTS Yor RxOUT2 Rx OUT 1 GND 0801290822 RxOUT| Q RxCLK DS012908-23, www.national.comAbsolute Maximum Ratings (Note 1) DS9OCR215 1.98 W lf Milltary/Aerospace speclfled devices are requlred, DS90CR216 1.89 W please contact the Natlonal Semiconductor Sales Offlce/ Package Derating Distributors for avallablilty and specifications. DS90C R215 16 mWFC above +25C Supply Voltage (Voc) _03V to 44 DSg90C R216 15 mWFC above +25C CMOS/TTL Input Voltage -0.3V 10 (Vg + 0.3V) ESD Rating CMOS/TTL Output Voltage -0.3 to (Voo + 0.3V) (HBM, 1.5 ki, 100 pF) > 7K LVDS Receiver Input Voltage -0.3V to (Voc + 0.3V' LVDS Driver Output Voltage -0.3 to en + oa Recommended Operating LVDS Output Short Conditions Circuit Duration Continuous Min Nom Max Units Junction Temperature +150C Supply Voltage (Veg) 30 33 36 Vv Storage Temperature Range -65C to +150C Operating Free Air Lead Temperature Temperature (T,) -10 +25 +70 CS (Soldering, 4 sec.) +260C Receiver Input Range 9 24 Vv Maximum Package Power Dissipation @ +25C Supply Noise Voltage (Voc) 400 mVep MTD48 (TSSOP) Package: Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol | Parameter Conditlons | MIn | Typ | Max [units CMOS/TTL DC SPECIFICATIONS Vin High Level Input Voltage 2.0 Veco Vv Viv Low Level Input Voltage GND 0.8 Vv Vou High Level Output Voltage loy = -0.4 mA 27 3.3 Vv VoL Low Level Output Voltage lop =2 mA 0.06 0.3 Vv Vet Input Clamp Voltage le. =-18mA 0.79 -1.5 ling Input Current Von = Vee, GND, 45.1 +10 pA 2.5V or 0.4V los Output Short Circuit Current V out = OV -60 -120 mA LVDS DRIVER DC SPECIFICATIONS Voo Differential Output Voltage R_ = 1008 250 290 450 mv AVop Change in gp between 35 m Complimentary Cutput States Vos Offset Voltage (Note 4) 1.125 1.25 1.375 Vv AVos Change in V ogbetween 35 mv Complimentary Cutput States log Output Short Circuit Current V out = OV, 3.5 5 mA R, = 1000 loz Output TRI-STATE Current PWR DWN = OV, 4H +10 pA V our = OV oF Veg LVDS RECEIVER DC SPECIFICATIONS Vou Differential Input High Threshold Vicm =+1.2V +100 mv VoL Differential Input Low Threshold 100 mV lin Input Current Vin = +2 4V, Voo = 3.6V 10 pA Vin = OV, Voo = 3.6V +10 pA TRANSMITTER SUPPLY CURRENT lectw Transmitter Supply Current R, = 1000, f = 32.5 MHz 31 45 mA Worst Gase (with Loads) GC. = 5 pF, Worst Case f= 37.5 MHz 32 50 mA (Fines 12 f= 66 MHz 37 55 mA www.national.comElectrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol | Parameter | Conditlons | MIn | Typ | Max [units TRANSMITTER SUPPLY CURRENT leetz Transmitter Supply Current PWR DWN = Low Power Down Driver Outputs in TRI-STATE 10 55 HA under Powerdown Made RECEIVER SUPPLY CURRENT lecrw Receiver Supply Gurrent Worst C_ =8 pF, f= 32.5 MHz 49 65 mA Case Worst Gase {= 37.5 MHz 53 70 mA Pattem (Figures 1, 3) ft = 66 MHz 78 105 mA leerz Receiver Supply Gurrent Power PWR DWN = Low 10 55 pA Down Receiver Outputs Stay Low during Powerdown Mode Note 2: Typical values are given for Veg = 3.3V and Ta = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci- fied (except Vap and AVop) Note 4: Vog previously referred as Von Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Note 1: "Absolute Maximum Ratings" are those values beyond which the satety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation Symbol Parameter MIn Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 2) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 2) 0.75 1.5 ns TOIT TxGLK IN Transition Time (Figure 4) 5 ns TGCS TxOUT Ghannel-to-CGhannel Skew (Figure 5) 250 ps TPPaso Transmitter Output Pulse Position for 1 = 66 MHz 0.4 0 0.3 ns BitO (Figure 76) TPPos1 Transmitter Output Pulse Position for 1.8 22 2.5 ns Bitt TPPos2 Transmitter Output Pulse Position for 4.0 44 47 ns Bit2 TPPos3 Transmitter Output Pulse Position for 6.2 6.6 6.9 ns Bits TPPas4. Transmitter Output Pulse Position for 84 8.8 3.1 ns Bita TPPoas5 Transmitter Output Pulse Position for 10.6 11.0 11.3 ns Bit TPPas6 Transmitter Output Pulse Position for 12.8 13.2 13.5 ns Bit TCIP TxCLK IN Period (Figure 6) 15 T 50 ns TGIH TxGLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns TGIL TxGLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns TSTG TxIN Setup to TxCLK IN (Figure 6) 2.5 ns THIG TxIN Hold to TxCLK IN (Figure 6) 0 ns TCCD TxGLK IN to TxCLK OUT Delay @ 25C Ve=3.3V 3 5.5 ns (Figure 8) TPLLS Transmitter Phase Lock Loop Set (Figure 70) 10 ms TPDD Transmitter Powerdown Delay (Figure 74) 100 ns www.national.comReceiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter MIn Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time (Figure 3) 2.2 5 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 3) 2.2 5 ns RSPosod Receiver Input Strobe Position for Bit 0 (Figure 17) 1=66 MHz 0.7 1.1 14 ns RSPos1 Receiver Input Strobe Position for Bit 1 1=66 MHz 2.9 3.3 3.6 ns RSPos?2 Receiver Input Strobe Position for Bit 2 1=66 MHz 5.1 5.5 5.8 ns RSPos3 Receiver Input Strobe Position for Bit 3 1=66 MHz 7.3 77 8.0 ns RSPas4. Receiver Input Strobe Position for Bit 4 1=66 MHz 9.5 9.9 10.2 ns RSPos5 Receiver Input Strobe Position for Bit 5 1 = 66 MHz 1.7 124 12.4 ns RSPos6 Receiver Input Strobe Position for Bit 6 1=66 MHz 13.9 14.3 14.6 ns RSKM RxIN Skew Margin (Note 5) Vee = 3.3V, T, = 25C 1=66 MHz 400 ps (Figure 18) RGOP RxCLK OUT Period (Figure 7) 15 T 50 ns RCGOH RxCLK OUT High Time (Figure 7) 1=66 MHz 4.75 49 ns RGOL RxCLK OUT Low Time (Figure 7) 6.5 6.6 ns RSRC RxOUT Setup to RxCLK OUT (Figure 7) 2.5 6.9 ns RHRG RxOUT Hold to RxCLK OUT (Figure 7) 2.5 57 ns RCGCD RxGLK IN to RxGLK OUT Delay @ 25C, Voc = 3.3 (Figure 9) 5 7 9 ns RPLLS Receiver Phase Lock Loop Set (Figure 77) 10 ms RPDD Receiver Powerdown Delay (Figure 74) 1 ys Note : Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes inte account for transmitter pulse pasitions (min and max) and the receiver input setup and hold time (internal data sampling window}. This margin allows LYDS interconnect skew, intersymbol interference (both dependent on type/length of cable}, and clock jitter less than 250 ps) AC Timing Diagrams TaCLk IN? R&CLK OUT ODD TxIN/RxOUT EVEN TxIN/RxOUT OS01290a.2 FIGURE 1. Worst Case Test Pattern TxOUT+ L, Wdif? = {TeOUT+}-(Tx9JT-} yon TxOUT= waite 080129093 Osoi2o084 FIGURE 2. DS90CR215 (Transmitter) LVDS Output Load and Transition Times 5 www.national.comAC Timing Diagrams (Continved) CMOS/TIL OUTPUT OS90CR216 8 pF CMOS /TTL OUTPUT D801 2508-5 050120096 TXELE IN TCIT Ds 2808-7 FIGURE 4. D599CR215 (Transmitter) Input Clock Transition Time TOOs wt} be vere YOO TxOUT 1 TxOUT2 } TxCLkK OUT i i ee i a, TIME -- pso12908-8 Note & Measurements at Vojep = OV Note 7 TCCS measured between earliest and latest LYDS edges Note & TxCLK Differential Low-High Edge FIGURE 5. D590CR215 (Transmitter) Channel-to-Channel Skew Sample on L~H Edge aN | TxCLK IN TxIN 0:20 1.5 Setup Hald 1.5 OSo1 2000-9 FIGURE 6. D590CR215 (Transmitter) Setup/Hold and High/Low Times www.national.com 8AC Timing Diagrams (Continued) RxCLK OUT RxOUT 0:20 0801280810 FIGURE 7. D590CR216 (Recelver) Setup/Hold and High/Low Times TxCLK IN TxCLkK OUT RxCLK IN RxCLK OUT OS01290212 FIGURE 9. D590CR 216 (Recelver) Clack In to Clock Out Delay BV ra POWER DOWN 3V we Voc TPLLS. 3,6V TELE IN LJ \S WS XE TxfLK OUTS A RxCLK IN 0801280813 FIGURE 10. DS90CR 215 (Transmltter) Phase Lock Loop Set Time www.national.comAC Timing Diagrams (Continved) POWER DOWN + RPLLS +] neve out XY VS 0S012908-14 FIGURE 11. DS90CR216 (Recelver) Phase Lock Loop Set Time TxCLK QUT RxCLK IN T 1/7 mat XXX XXX D301 2000-15 FIGURE 12. Seven Bits of LYDS In Once Clock Cycle TxOLK OUT RxCLK IN Previous Cycle Next Cycle ran Kiawis-X vie TxIN20 x TxIN19 x TxIN18 x TxIN1? x TxIN16 x TxIN15 xX TxIN1 4 x TOUT / rane=1 X nan7=1 TxiN13 xX TxIN12 x TxIN1 1 x TxIN10 x TxiNg x TxINS xX TxIN7 RxIN 1 A TxOUTO/ raini=i X nano=1 TxINS xX TxINS xX TxIN4 xX TxING xX THIN? x TxIN1 4 TxIN@ RxlNO / DS01250818 FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LYDS Outputs (DS90CR215) PWR DWN 1.5 TxCLk IN TxOUT Tri-State Os012506-17 FIGURE 14. Transmitter Powerdown Delay www.national.com 8AC Timing Diagrams (Continued) POWER DOWN 1.5 oN me YOOOARA >= RPDD+| RxOlT Low osoi2s0c.18 FIGURE 15. Recelver Powerdown Delay ToL ' 1 TxCLK OUT | (Differential) ' : . I Previous Cycle I bot : Next Cycle, TxOUT2/ Kawase Kiana X TxIN20 x TxIN 18 x TIN 18 x TxIN17 x TxIN16 x TxIN15 4 TAIN 14 x (Single ended} | fi : ! : : : : / TxOUT1 / Means X rans X Tent MO Txin12 YX tena X ritito x TxiNg x TxIN8 x TxIN? X (Single ended} | #: ; : : : : : / TxOUTO/ Krenn X rane 1X TxING x TxINS x TxIN4 x TxIN3 x TxIN2 xX TxIM4 xX TxINO X (Single ended} 1 : t : ' : / ea '" TPPos : : : $+ : : : : : | TPPost ' : ' : : +: : : | TRPos? i : : pot : TPPos3 : i | TRRas4 , | TPPasS TPPos6 Oso12900-19 FIGURE 16. Transmitter LVDS Output Pulse Positlon Measurement g www.national.comAC Timing Diagrams (Continved) Tok ' RxCLK IN (Differential) | Previous Cyle Next Cycle RxINO RxIN1 775 3 773 I TIF ad TIF 555 5 RxIN2 See RSposd min: : t : : : t ' : t : ' ' mm FG EE EE EE EO Rspas0 max ' : : : : : : : : : : ' ; Repost min | ; ; ; Rspos1 max : ; : ; Rspos2 min ; Rspos2 max : ; ; ; Rspes3 min ; ; ' Rspos3 max . Rspos4 min | ; | : Rspos4 max Rspess min ; : Rsposs max . Rspos6 min Rspos may Osoizece.28 FIGURE 17. Recelver LVDS Input Strobe Position www.national.com 10AC Timing Diagrams (Continued) in ra Tpposn min max Tpposn+1 Rsposn psa12e08-26 CSetup and Hold Time (Internal data sampling window) defined by Repos (receiver input strobe position) min and max TpposTransmitter uiput pulse position (min and max) RSKM 2 Cable Skew (type, length} + Source Clock Jitter (cycle to cycle} (Note 9) + IS! (Inter-symbol interference) (Note 10) Cable Skewtypically 10 ps40 ps per foot, media dependent Note 9: Cycle-to-cycle jitter is less than 250 ps Note 1% |S is dependent on interconnect length: may be zero FIGURE 18. Recelver LVDS Input Skew Margin Applications Information The DS90CR215 and D90CR216 are backward compatible 2. Transmitter input and control inputs except 3.3V TTL/ with the existing 5V Channel Link transmitter/receiver pair CMOS levels. They are not 5V tolerant. (DS90C R213, DS90CR214). To upgrade from a5V to a3.3 3. The receiver powerdown feature when enabled will lock system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the Voc, Ideal Strobe Position RxIN+ or RxIN- ~ 1.44 RxIN- or RxINt LVDS Vee and PLL V oc. powerdown occurred. DS$s0CR215 Pin Description Channel Link Transmitter receiver output to a logic low. However, the 5V/66 MHz receiver maintain the outputs in the previous state when Pin Name Vo No. Deseriptlon TxIN I 21 TTL level input. TxOQUT+ 0 3 Positive LVDS differential data output. TxOUT- 0 3 Negative LVDS differential data output. TxGLk IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCGLK IN. TxGLK GUT+ 0 1 Positive LVDS differential clock output. TxCLK OUT- 0 1 Negative LVDS differential clock output. PWR DWN I 1 TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power down. Veeco I 4 Power supply pins for TTL inputs. GND I 5 Ground pins for TTL inputs. PLLV cc I 1 Power supply pins for PLL. PLL GND I 2 Ground pins for PLL. LVDS Vice I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. DS90CR 216 Pin Description Channel Link Receiver Pin Name Vo No. Description RxIN+ I Positive LVDS differential data inputs. RxIN- I 3 Negative LVDS differential data inputs. RxOUT Go 2 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN I 1 Negative LVDS differential clock input. www.national.comApplications Information (Continved) DS90CR 216 Pin Description Channel Link Receiver (Continued) Pin Name Vo No. Deserlption RxGLK OUT oO 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT. PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. Voc I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL V cc I 1 Power supply for PLL. PLL GND 1 2 Ground pin for PLL. LVDS V ec I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For ex- ample, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is less criti- cal. For higher speed/long distance applications the media's performance becomes more critical. Certain cable construc- tions provide tighter skew (matched electrical length be- tween the conductors and pairs). Twin-coax for example, has been demonstrated at distances as great as 5 meters and with the maximum data transfer of 1.38 Gbit/s. Additional ap- plications information can be found in the following National Interface Application Notes: AN = #### Tople AN-1041 Introduction to Ghannel Link AN-1035 PCB Design Guidelines for LVDS and Link Devices AN-806 Transmission Line Theory AN-905 Transmission Line Calculations and Differential Impedance AN-916 Cable Information CABLES: A cable interface between the transmitter and re- ceiver needs to support the differential LYDS pairs. The 21- bit CHANNEL LINK chipset (DS90CR215/216) requires four pairs of signal wires and the 28-bit CHANNEL LINK chipset (DS90CR285/286) requires five pairs of signal wires. The ideal cable/connector interface would have a constant 1000 differential impedance throughout the path. It is also recom- mended that cable skew remain below 150 ps ( 66 MHz clock rate) to maintain a sufficient data sampling window at the receiver. In addition to the tour or five cable pairs that carry data and clock, it is recommended to provide at least one additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance ground pro- vides a common mode retum path for the two devices. Same of the more commonly used cable types for point-to-point ap- plications include flat ribbon, flex, twisted pair and Twin- Coax. All are available in a variety of configurations and op- tions. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while Twin- Coax is good for short and long applications. When using rib- bon cable, itis recommended to place aground line belween each differential pair to act as a barrier to noise coupling be- tween adjacent pairs. For Twin-Goax cable applications, it is recommended to utilize a shield on each cable pair. All ex- tended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type. This overall shield results in improved transmis- sion parameters such as faster attainable speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI. The high-speed transport of LVDS signals has been demon- strated on several types of cables with excellent results. However, the best overall performance has been seen when using Twin-Goax cable. Twin-Coax has very low cable skew and EMI due to its construction and double shielding. All of ihe design considerations discussed here and listed in the supplemental application notes provide the subsystem com- munications designer with many useful guidelines. It is rec- ommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. BOARD LAYOUT To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid io the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise can- celing of the differential signals. The board designer should also try to maintain equal length on signal traces for a given differential pair. As with any high speed design, the imped- ance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinui- ties which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken ta ensure that the differential trace impedance match the differ- ential impedance of the selected physical media (this imped- ance should also match the value of the termination resistor that is connected across the differential pair at the receiver's input). Finally, the location of the CHANNEL LINK TxQUT/ RxIN pins should be as close as possible to the board edge 80 as to eliminate excessive pcb runs. All of these consider- ations will limit reflections and crosstalk which adversely et- fect high frequency performance and EMI. UNUSED INPUTS: All unused inputs at the TxIN inputs of ihe transmitter must be tied to ground. All unused outputs at the RxOUT outputs of the receiver must then be left floating. TERMINATION: Use of current mode drivers requires a ter- minating resistor across the receiver inputs. The CHANNEL LINK chipset will normally require a single 100 resistor be- tween the true and complement lines on each differential pair of the receiver input. The actual value of the termination resistor should be selected to match the differential mode characteristic impedance (900 to 120 typical) of the cable. www.national.comApplications Information (Continved) Figure 19 shows an example. No additional pull-up or pull- down resistors are necessary as with some other differential technologies such as PEGL. Surface mount resistors are recommended to avoid the additional inductance that ac- companies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to re- duce stubs and effectively terminate the differential lines. FIGURE 19. LYDS Serlallzed Link TermInatlon DECOUPLING CAPACITORS: Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ge- ramic type in surface mount form factor) between each Veg and the ground plane(s) are recommended. The three ca- pacitor values are 0.1 UF, 0.01pF and 0.001 pF. An example is shown in Figure 20. The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the number of bypass capacitors, the PLL Vee should receive ihe most filtering/bypassing. Next would be the LVDS Vee pins and finally the logic Vcc pins. Voc 0.001 pF | 0.01 pF] 0.1 uF CHANNEL LINK D801 2808-25 FIGURE 20. CHANNEL LINK Decoupling Configuration CLOCK JITTER: The GHANNEL LINK devices employ a PLLto generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 66 MHz clock has a period of 15 ns which results in a data bit width of 2.16 ns. Differential skew (At within one differential TxOUT+ RxINt LYDS INTERFACE Oto 10 meters 1000 {media dependent) TxOUT RxIN- D801 2808-24 pair), interconnect skew (At of one differential pair to an- other) and clock jitter will all reduce the available window tor sampling the LVDS serial data streams. Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each V,. to ground will minimize the noise passed on to the PLL, thus creating a low jitter LYDS clock. These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget. COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR- GIN: The typical signal swing for LVDS is 300 m centered at +1.2V. The GHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately 200 mV of differ- ential noise margin. Common mode protection is of more im- portance to the systems operation due to the differential data transmission. LYDS supports an input voltage range of Ground to +2.4V. This allows for a 1.0V shifting of the cen- ter point due to ground potential differences and common mode noise. POWER SEQUENCING AND POWERDOWN MODE: Out puts of the CNANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after Vc_ has reached 3V and the Powerdown pin is above 1.5V. Either device may be placed into a powerdown mode at any time by asserting the Power- down pin (active low). Total power dissipation for each de- vice will decrease to 5 UW (typical). The GHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or re- ceiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs (RxOUT) re- tain the states they were in when the clocks stopped. When the receiver board loses power, the receiver inputs are shorted to V ec through an intemal diode. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the potential for latchup when powering the device. www.national.comApplications Information (Continued) +1.25V [vCM) ie: TxOUT+ = Your SWITCHING INPUT S50n ~ SQUARE WAVE Tx t TM yop Z50n * O ry TxOUT- 0 Vouta GND = Measured Parameter Your Your* GND +244 OD = (Vourt} > our7) Rx OY Diff. Input (+#1.25) Range (not drawn to scale} Guo Dao 2808-26 FIGURE 21. Single-Ended and Differentlal Waveforms www.national.com 14Ph ysical Dimensions inches (millimeters) unless otherwise noted 12.5 + 0.4 ,GAGE PLANE f seating PLANE +018 ad j~_+| 0.60 DETAIL A TYPICAL Lejo.2[c[e [A] ALL LEAD TIPS for DETAIL A (8.90) va [- : | Yt ~ 0.09-6.20 ret i 1.1 MAX XN 0.10 0.05 TYP 0.17 - 0.27 TYP Order Number DS90CR215MTD or DS90CR216MTD NS Package Number MTD48 M7D48 {TLV A} LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or sysiems are devices or sys- iems which, (a) are intended for surgical implant into ihe body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury io the user. 2. A critical component in any component of a life support device or sysiem whose failure to periorm can be rea- sonably expecied to cause the failure of the life support device or sysiem, or to affect iis safety or effectiveness. National Semiconductor National Semiconductor National Semiconductor Natlonal Semiconductor DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz Corp oration Europe Agia Pacific Custom er Japan Lid. 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