54F299DMQB. - NATIONAL SEMICONDUCTOR

54F299,74F299

54F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins

Literature Number: SNOS185A

TL/F/9515

54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins

May 1995

54F/74F299 Octal Universal Shift/Storage Register

with Common Parallel I/O Pins

General Description

The ’F299 is an 8-bit universal shift/storage register with

TRI-STATEÉoutputs. Four modes of operation are possi-

ble: hold (store), shift left, shift right and load data. The par-

allel load inputs and flip-flop outputs are multiplexed to re-

duce the total number of package pins. Additional outputs,

Q0–Q7, are provided to allow easy serial cascading. A sep-

arate active LOW Master Reset is used to reset the register.

Features

YCommon parallel I/O for reduced pin count

YAdditional serial inputs and outputs for expansion

YFour operating modes: shift left, shift right, load and

store

YTRI-STATE outputs for bus-oriented applications

YGuaranteed 4000V minimum ESD protection

Commercial Military Package Package Description

Number

74F299PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line

54F299DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line

74F299SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC

74F299SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F299FM (Note 2) W20A 20-Lead Cerpack

54F299LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffix eSCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix eDMQB, FMQB and LMQB.

Logic Symbols

TL/F/9515–1

IEEE/IEC

TL/F/9515–4

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Obsolete

Connection Diagrams

Pin Assignment

for DIP, SOIC and Flatpak

TL/F/9515–2

Pin Assignment

for LCC

TL/F/9515–3

Unit Loading/Fan Out

54F/74F

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA

DS0Serial Data Input for Right Shift 1.0/1.0 20 mA/b0.6 mA

DS7Serial Data Input for Left Shift 1.0/1.0 20 mA/b0.6 mA

S0,S

1Mode Select Inputs 1.0/2.0 20 mA/b1.2 mA

MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

OE1,OE

2TRI-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 mA/b0.6 mA

I/O0–I/O7Parallel Data Inputs or 3.5/1.083 70 mA/b0.65 mA

TRI-STATE Parallel Outputs 150/40(33.3) b3 mA/24 mA (20 mA)

Q0,Q

7Serial Outputs 50/33.3 b1 mA/20 mA

Functional Description

The ’F299 contains eight edge-triggered D-type flip-flops

and the interstage logic necessary to perform synchronous

shift left, shift right, parallel load and hold operations. The

type of operation is determined by S0and S1, as shown in

the Mode Select Table. All flip-flop outputs are brought out

through TRI-STATE buffers to separate I/O pins that also

serve as data inputs in the parallel load mode. Q0and Q7

are also brought out on other pins for expansion in serial

shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs

and resets the flip-flops. All other state changes are initiated

by the rising edge of the clock. Inputs can change when the

clock is in either state provided only that the recommended

setup and hold times, relative to the rising edge of CP, are

observed.

A HIGH signal on either OE1or OE2disables the TRI-

STATE buffers and puts the I/O pins in the high impedance

state. In this condition the shift, hold, load and reset opera-

tions can still occur. The TRI-STATE outputs are also dis-

abled by HIGH signals on both S0and S1in preparation for

a parallel load operation.

Mode Select Table

Inputs Response

MR S1S0CP

L X X X Asynchronous Reset; Q0–Q7eLOW

HHHLParallel Load; I/On

HLHLShift Right; DS0

Q0,Q

, etc.

HHLLShift Left; DS7

Q7,Q

, etc.

H L L X Hold

HeHIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

LeLOW-to-HIGH Clock Transition

Obsolete

Logic Diagram

TL/F/9515–5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Obsolete

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

ESD Last Passing Voltage (Min) 4000V

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Voltage Applied to Output

in HIGH State (with VCC e0V)

Standard Output b0.5V to VCC

TRI-STATE Output b0.5V to a5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Recommended Operating

Conditions

Free Air Ambient Temperature

Military b55§Ctoa

125§C

Commercial 0§Ctoa

70§C

Supply Voltage

Military a4.5V to a5.5V

Commercial a4.5V to a5.5V

DC Electrical Characteristics

Symbol Parameter 54F/74F Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage b1.2 V Min IIN eb

18 mA

VOH Output HIGH 54F 10% VCC 2.5 IOH eb

1mA(Q

, I/On)

Voltage 54F 10% VCC 2.4 IOH eb

3 mA (I/On)

74F 10% VCC 2.5 V Min IOH eb

1mA(Q

, I/On)

74F 10% VCC 2.4 IOH eb

3 mA (I/On)

74F 5% VCC 2.7 IOH eb

1mA(Q

, I/On)

74F 5% VCC 2.7 IOH eb

3 mA (I/On)

VOL Output LOW 54 10% VCC 0.5 IOL e20 mA

Voltage 74 10% VCC 0.5 V Min IOL e20 mA (Q0,Q

)

74 10% VCC 0.5 IOL e24 mA (I/On)

IIH Input HIGH 54F 20.0 mA Max VIN e2.7V (CP, DS0,DS

Current 74F 5.0 MR,OE

,OE

)

BVI Input HIGH Current 54F 100 mA Max VIN e7.0V (CP, DS0,DS

Breakdown Test 74F 7.0 MR,OE

,OE

)

BVIT Input HIGH Current 54F 1.0 mA Max VIN e5.5V (I/On)

Breakdown Test (I/O) 74F 0.5

ICEX Output HIGH 54F 250 mA Max VOUT eVCC

Leakage Current 74F 50

VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA

Test All Other Pins Grounded

IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current b0.6 mA Max VIN e0.5V (CP, DS0,DS

,MR,OE

,OE

)

1.2 VIN e0.5V (S0,S

)

IHaOutput Leakage Current 70 mA Max VI/O e2.7V (I/On)

IOZH

IILaOutput Leakage Current b650 mA Max VI/O e0.5V (I/On)

IOZL

IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V

IZZ Bus Drainage Test 500 mA 0.0V VOUT e5.25V

ICCH Power Supply Current 68 95 mA Max VOeHIGH

ICCL Power Supply Current 68 95 mA Max VOeLOW

ICCZ Power Supply Current 68 95 mA Max VOeHIGH Z

Obsolete

AC Electrical Characteristics

74F 54F 74F

TAea

25§CTA,V

CC eMil TA,V

CC eCom

Symbol Parameter VCC ea

5.0V CLe50 pF CLe50 pF Units

CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Input Frequency 70 100 85 70 MHz

tPLH Propagation Delay 4.0 7.0 8.0 4.0 9.0 4.0 8.5

tPHL CP to Q0or Q74.5 6.5 8.0 4.5 9.5 4.5 8.5 ns

tPLH Propagation Delay 3.5 7.0 9.0 3.5 10.0 3.5 10.0

tPHL CP to I/On4.0 8.5 9.0 4.0 11.0 4.0 10.0

tPHL Propagation Delay 5.5 7.5 9.5 5.5 12.5 5.5 10.5

MR to Q0or Q7ns

tPHL Propagation Delay 5.5 11.0 10.0 5.5 12.0 5.5 10.5

MR to I/On

tPZH Output Enable Time 3.5 6.0 8.0 3.0 9.5 3.5 9.0

tPZL OE to I/On4.0 7.0 10.0 4.0 13.0 4.0 11.0 ns

tPHZ Output Disable Time 2.0 4.5 6.0 1.5 7.0 2.0 7.0

tPLZ OE to I/On1.0 4.0 5.5 1.0 6.5 1.0 6.5

tPZH Output Enable Time 3.5 9.0 3.0 10.5 3.5 10.0 ns

tPZL Snto I/On4.0 10.0 4.0 13.0 4.0 11.0

tPHZ Output Disable Time 2.5 6.0 1.5 7.0 2.5 7.0 ns

tPLZ Snto I/On1.5 5.5 1.0 6.5 1.5 6.5

AC Operating Requirements

74F 54F 74F

Symbol Parameter TAea

25§CTA,V

CC eMil TA,V

CC eCom Units

VCC ea

5.0V

Min Max Min Max Min Max

ts(H) Setup Time, HIGH or LOW 8.5 10.0 8.5

ts(L) S0or S1to CP 8.5 7.5 8.5 ns

th(H) Hold Time, HIGH or LOW 0 0 0

th(L) S0or S1to CP 0 0 0

ts(H) Setup Time, HIGH or LOW 5.0 5.0 5.0

ts(L) I/On,DS

0or DS7to CP 5.0 5.0 5.0 ns

th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0

th(L) I/On,DS

0or DS7to CP 2.0 2.0 2.0

tw(H) CP Pulse Width 5.0 5.0 5.0 ns

tw(L) HIGH or LOW 5.0 5.0 5.0

tw(L) MR Pulse Width, LOW 5.0 6.0 5.0 ns

trec Recovery Time, MR to CP 7.0 12.0 7.0 ns

Obsolete

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74F 299 S C X

Temperature Range Family Special Variations

74F eCommercial QB eMilitary grade device with

54F eMilitary environmental and burn-in

processing

Device Type XeDevices shipped in 13×reel

Package Code Temperature Range

PePlastic DIP CeCommercial (0§Ctoa

70§C)

DeCeramic DIP MeMilitary (b55§Ctoa

125§C)

SeSmall Outline SOIC JEDEC

SJ eSmall Outline SOIC EIAJ

FeFlatpak

LeLeadless Chip Carrier (LCC)

Physical Dimensions inches (millimeters)

20-Lead Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

Obsolete

Physical Dimensions inches (millimeters) (Continued)

20-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

20-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)

NS Package Number M20B

Obsolete

Physical Dimensions inches (millimeters) (Continued)

20-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)

NS Package Number MD20D

20-Lead (0.300×Wide) Molded Dual-In-Line Package (P)

NS Package Number N20A

Obsolete

54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins

Physical Dimensions inches (millimeters) (Continued)

20-Lead Cerpack

NS Package Number W20A

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Obsolete

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