Precision Edge(R) 2.5GHz ANY DIFF. IN-TO-LVPECL (R) SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES Precision Edge(R) Two matched-delay outputs: * Bank A: undivided pass-through (QA) * Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1) Matched delay: all outputs have matched delay, independent of divider setting Guaranteed AC performance: * >2.5GHz fMAX * <250ps tr/tf * <670ps tpd (matched delay) * <15ps within-device skew Low jitter design * <1psRMS cycle-to-cycle jitter * <10psPP total jitter Power supply 3.3V or 2.5V Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) TTL/CMOS inputs for select and reset 100K EP compatible LVPECL outputs Parallel programming capability Wide operating temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) MLF(R) package DESCRIPTION The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting. All support documentation can be found on Micrel's web site at: www.micrel.com. APPLICATIONS OC-3 to OC-192 SONET/SDH applications Transponders Oscillators SONET/SDH line cards FUNCTIONAL BLOCK DIAGRAM TYPICAL PERFORMANCE QA QA@622MHz and QB@155.5MHz /QA VREF-AC QA QB0 IN Divided by 2, 4, 8 or 16 50 VT 50 622MHz Output /QB0 /QA QB1 /IN QB0 /QB1 S0 155.5MHz Output Decoder /4 S1 /QB0 /RESET Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 Rev.: F 1 Amendment: /0 Issue Date: August 2007 Precision Edge(R) SY89871U Micrel, Inc. S0 S1 VCC GND PACKAGE/ORDERING INFORMATION 16 15 14 13 Ordering Information 11 VT QB1 3 10 VREF-AC /QB1 4 9 6 7 8 VCC IN /RESET 12 2 /QA 1 QA QB0 /QB0 5 Package Operating Type Range Part Number Package Marking Lead Finish SY89871UMI MLF-16 Industrial 871U Sn-Pb SY89871UMITR(1) MLF-16 Industrial 871U Sn-Pb SY89871UMG(2) MLF-16 Industrial 871U with Pb-Free bar line indicator NiPdAu Pb-Free SY89871UMGTR(1, 2) MLF-16 Industrial 871U with Pb-Free bar line indicator NiPdAu Pb-Free /IN Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 16-Pin MLF(R) (MLF-16) PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2, 3, 4 QB0, /QB0 QB1, /QB1 Differential Buffered Output Clocks: This differential output is a divided-down version of the input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16. See "Truth Table." Unused output pairs may be left floating. 5, 6 QA, /QA 7, 14 VCC 8 /RESET 12, 9 IN, /IN 10 VREF-AC 11 VT 13 GND 15, 16 S1, S0 Differential Buffered Undivided Output Clock. Positive Power Supply: Bypass with 0.1FTMTM0.01F low ESR capacitors. Output Reset: Internal 25ky pull-up. Logic LOW will reset the divider select. See "Truth Table." Input threshold is VCC/2. Differential Input: Internal 50y termination resistors to VT input. See "Input Interface Applications" section. Reference Voltage: Equal to VCC-1.4V (approx.), and used for AC-coupled applications. For DC-coupled applications, VREF-AC is normally left floating. Maximum sink/source current is 0.5mA. See "Input Interface Applications" section. Input Termination Center-Tap: Each side of differential input pair terminates to this pin. The VT pin provides a center tap to a termination network for maximum interface flexibilty. For CML and LVDS inputs, leave this pin floating. See "Input Interface Application" section. Ground. Select Pins: See "Truth Table." LVTTL/CMOS logic levels. Internal 25ky pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2. TRUTH TABLE /RESET S1 S0 Bank A Output Bank B Outputs 1 0 0 Input Clock Input Clock /2 1 0 1 Input Clock Input Clock /4 1 1 0 Input Clock Input Clock /8 1 1 1 Input Clock Input Clock /16 0 X X Input Clock QB = LOW, /QB = HIGH M9999-082407 hbwhelp@micrel.com or (408) 955-1690 2 Precision Edge(R) SY89871U Micrel, Inc. Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ................................... -0.5V to +4.0V Input Voltage (VIN) ............................... -0.5V to VCC +0.3V PECL Output Current (IOUT) Continuous .......................................................... 50mA Surge .................................................................100mA VT Current (IVT) ...................................................... 100mA Input Current IN, /IN (IIN) .......................................... 50mA VREF-AC Sink/Source Current (IVREF-AC) .................... 2mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ........................ -65C to +150C Supply Voltage (VCC) ............................. +2.375V to +3.63V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air ............................................................. 60C/W 500lfpm ........................................................... 54C/W MLF(R) (JB) Junction-to-board ............................................ 38C/W DC ELECTRICAL CHARACTERISTICS(4) TA = -40C to +85C, unless otherwise stated. Symbol Parameter Condition Min VCC Power Supply Voltage ICC Power Supply Current RIN Differential Input Resistance, (IN-to-/IN) 90 VIH Input HIGH Voltage, (IN, /IN) VIL Input LOW Voltage, (IN, /IN) VIN Input Voltage Swing VDIFF_IN Typ Max Units 3.60 V 50 75 mA 100 110 y 0.1 VCC+0.3 V -0.3 VIH-0.1 V Notes 5 0.1 VCC V Differential Input Voltage Swing Notes 5, 6 0.2 |IIN| Input Current, (IN, /IN) Note 7 VREF-AC Reference Voltage 2.37 No load, max VCC. V 45 VCC-1.525 VCC-1.425 VCC-1.325 mA V Notes: 1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. See "Timing Diagram" for VIN definition. VIN (max.) is specified when VT is floating. 6. See "Typical Operating Characteristics" section for VDIFF definition. 7. Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! M9999-082407 hbwhelp@micrel.com or (408) 955-1690 3 Precision Edge(R) SY89871U Micrel, Inc. (100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(8) VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C, RL = 50y to VCC -2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage VCC-1.145 VCC-1.020 VCC-0.895 V VOL Output LOW Voltage VCC-1.945 VCC-1.820 VCC-1.695 V VOUT Output Voltage Swing 550 800 1050 mV VDIFF_OUT Differential Output Voltage Swing 1.10 1.6 2.1 V LVTTL/LVCMOS DC ELECTRICAL CHARACTERISTICS(8) VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Condition Min Typ Max 2.0 -125 Units V 0.8 V 20 A -300 A Note: 8. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameters are for VCC = 2.5V. They vary 1:1 with VCC. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 4 Precision Edge(R) SY89871U Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(9) VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Output Toggle Frequency Output Swing 400mV 2.5 GHz Maximum Input Frequency Note 10 3.2 GHz Differential Propagation Delay Input Swing < 400mV 460 580 710 ps IN-to-QA or QB Input Swing 400mV 420 550 670 ps Within-Device Skew (Differential) QB0-to-QB1 Note 11 7 15 ps Within-Device Skew (Differential) QA-to-QB Note 11 12 30 ps Part-to-Part Skew (Differential) Note 11 250 ps Cycle-to-Cycle Jitter Note 12 1 psRMS Total Jitter Note 13 10 psPP tPD tSKEW tJITTER tRR Reset Recovery Time 600 tr, tf Output Rise/Fall Times (20% to 80%) 70 Typ Max Units ps 150 250 ps Notes: 9. Measured with 400mV input signal, 50% duty cycle, all loading with 50y to VCC-2V, unless otherwise stated. 10. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output /2, /4, /8, /16) can accept an input frequency >3GHz, while Bank A will be slew rate limited. 11. Skew is measured between outputs under identical transitions. 12. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_cc =Tn-Tn+1, where T is the time between rising edges of the output signal. 13. Total jitter definition: with an ideal clock input, of frequency - fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. TIMING DIAGRAM VCC/2 /RESET tRR IN /IN VIN Swing tPD /QB VOUT Swing QB QA /QA M9999-082407 hbwhelp@micrel.com or (408) 955-1690 5 Precision Edge(R) SY89871U Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, VIN = 400mV, TA = 25C, RL = 50y to VCC-2V, unless otherwise stated. IN to Q Propagation Delay vs. Input Swing QA Output Amplitude vs. Frequency 900 700 600 500 400 300 200 800 700 600 500 400 300 200 100 0 3500 3000 2500 2000 1500 1000 0 0 500 100 700 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 800 QA AMPLITUDE (mV) IN to Q Propagation Delay vs. Temperature 900 0 200 400 600 800 1000 1200 INPUT SWING (mV) 600 500 400 300 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) FREQUENCY (MHz) QA@622MHz and QB@155.5MHz 622MHz Output 1.25GHz Output QA /Q QB0 Output Swing (100mV/div.) Output Swing (200mV/div.) /QA 155.5MHz Output /4 Q /QB0 TIME (1ns/div.) TIME (100ps/div.) 2.5GHz Output Output Swing (100mV/div.) /Q Q TIME (100ps/div.) M9999-082407 hbwhelp@micrel.com or (408) 955-1690 6 Precision Edge(R) SY89871U Micrel, Inc. DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING VIN, VOUT VDIFF_IN, VDIFF_OUT 800mV (typical) 1600mV (typical) Figure 1a. Single-Ended Swing Figure 1b. Differential Swing INPUT BUFFER STRUCTURE VCC VCC 1.86k 1.86k 25k R S0 S1 /RESET 1.86k 1.86k R IN 50 SY89871U VT 50 GND GND /IN Figure 2a. Simplified Differential Input Buffer M9999-082407 hbwhelp@micrel.com or (408) 955-1690 Figure 2b. Simplified TTL/CMOS Input Buffer 7 Precision Edge(R) SY89871U Micrel, Inc. INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC VCC VCC IN PECL /IN IN IN VCC CML CML GND VCC NC VT NC VREF-AC VREF-AC NC 0.01F VCC Rpd VT VREF-AC Figure 3a. DC-Coupled CML Input Interface VT SY89871U SY89871U GND SY89871U 0.01F GND /IN /IN Figure 3b. AC-Coupled CML Input Interface Note: For 3.3V, Rpd = 50. For 2.5V, Rpd = 19. Figure 3c. DC-Coupled PECL Input Interface VCC IN VCC VCC VCC VCC PECL /IN Rpd Rpd VCC GND GND SY89871U Figure 3d. AC-Coupled PECL Input Interface /IN /IN SY89871U SY89871U VREF-AC Note: For 3.3V, Rpd = 100. For 2.5V, Rpd = 50. HSTL LVDS VT 0.01F IN IN GND GND NC VT NC VREF-AC VT NC VREF-AC GND Figure 3e. LVDS Input Interface Figure 3f. HSTL Input Interface RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89874U 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider and 1:2 Fanout Buffer w/Internal Termination http://www.micrel.com/product-info/products/sy89874u.shtml MLF(R) Application Note http://www.amkor.com/products/notes_papers/mlf_appnote.pdf HBW Solutions New Products and Applications M9999-082407 hbwhelp@micrel.com or (408) 955-1690 http://www.micrel.com/product-info/products/solutions.shtml 8 Precision Edge(R) SY89871U Micrel, Inc. LVPECL OUTPUT TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50 R1 130 R1 130 R2 82 R2 82 +3.3V ZO = 50 Vt = VCC --2V Figure 4a. Parallel Termination-Thevenin Equivalent Note: 1. For +2.5V systems: R1 = 250y, R2 = 62.5y. +3.3V +3.3V Z = 50 Z = 50 50 50 "destination" "source" VCC 50 Rb C1 (optional) 0.01F Figure 4b. Three-Resistor "Y-Termination" Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. For +3.3V systems Rb = 46y to 50y. For +2.5V systems Rb = 19y. 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. +3.3V +3.3V Q +3.3V R1 130 R1 130 Vt = VCC --1.3V R3 +3.3V 1k ZO = 50 /Q R4 1.6k Vt = VCC --2V R2 82 R2 82 Figure 4d. Terminating Unused I/O Notes: 1. Unused output (/Q) must be terminated to balance the output. 2. For +2.5V systems: R1 = 250y, R2 = 62.5y, R3 = 1.25ky, R4 = 1.2ky. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 9 Precision Edge(R) SY89871U Micrel, Inc. 16-PIN MicroLeadFrame(R) (MLF-16) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 10