1
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
Two matched-delay outputs:
• Bank A: undivided pass-through (QA)
• Bank B: programmable divide by
2, 4, 8, 16 (QB0, QB1)
Matched delay: all outputs have matched delay,
independent of divider setting
Guaranteed AC performance:
• >2.5GHz fMAX
• <250ps tr/tf
• <670ps tpd (matched delay)
• <15ps within-device skew
Low jitter design
• <1psRMS cycle-to-cycle jitter
• <10psPP total jitter
Power supply 3.3V or 2.5V
Unique patent-pending input termination and VT pin
for DC- and AC-coupled inputs: any differential
inputs (LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: –40°C to +85°C
Available in 16-pin (3mm x 3mm) MLF® package
FEATURES
APPLICATIONS
OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards
1Rev.: F Amendment: /0
Issue Date: August 2007
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output
banks. Bank A (QA) is a frequency-matched copy of the
input. Bank B (QB0, QB1) is a divided down output of the
input frequency. Bank A and Bank B maintain a matched
delay independent of the divider setting.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
Precision Edge®
Precision Edge®
SY89871U
2.5GHz ANY DIFF. IN-TO-LVPECL
PROGRAMMABLE CLOCK DIVIDER/
FANOUT BUFFER W/INTERNAL TERMINATION
TYPICAL PERFORMANCE
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
IN50Ω
50Ω
/IN
S0
S1
QB
1
/QB
1
QB
0
/QB
0
QA
/QA
/
RESET
V
T
V
REF-AC
Divided
by
2, 4, 8
or 16
Decoder
/QB0
QB0
/QA
QA
QA@622MHz and QB@155.5MHz
÷4
622MHz
Output
155.5MHz
Output
2
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Pin Number Pin Name Pin Function
1, 2, 3, 4 QB0, /QB0 Differential Buffered Output Clocks: This differential output is a divided-down version of
QB1, /QB1 the input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16.
See “Truth Table.” Unused output pairs may be left floating.
5, 6 QA, /QA Differential Buffered Undivided Output Clock.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF™™0.01µF low ESR capacitors.
8 /RESET Output Reset: Internal 25ký pull-up. Logic LOW will reset the divider select. See “Truth
Table.” Input threshold is VCC/2.
12, 9 IN, /IN Differential Input: Internal 50ý termination resistors to VT input. See “Input Interface
Applications” section.
10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications.
For DC-coupled applications, VREF-AC is normally left floating. Maximum sink/source
current is 0.5mA. See “Input Interface Applications” section.
11 VT Input Termination Center-Tap: Each side of differential input pair terminates to this pin.
The VT pin provides a center tap to a termination network for maximum interface flexibilty.
For CML and LVDS inputs, leave this pin floating. See “Input Interface Application” section.
13 GND Ground.
15, 16 S1, S0 Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25ký pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
PIN DESCRIPTION
13141516
12
11
10
9
1
2
3
4
8765
QB0
/
QB0
QB1
/
QB1
IN
VT
VREF-A
C
/IN
S0
S1
VC
C
GN
D
QA
/QA
VCC
/
RESET
16-Pin MLF® (MLF-16)
/RESET S1 S0 Bank A Output Bank B Outputs
1 0 0 Input Clock Input Clock ÷2
1 0 1 Input Clock Input Clock ÷4
1 1 0 Input Clock Input Clock ÷8
1 1 1 Input Clock Input Clock ÷16
0 X X Input Clock QB = LOW, /QB = HIGH
TRUTH TABLE
Ordering Information
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89871UMI MLF-16 Industrial 871U Sn-Pb
SY89871UMITR(1) MLF-16 Industrial 871U Sn-Pb
SY89871UMG(2) MLF-16 Industrial 871U with NiPdAu
Pb-Free bar line indicator Pb-Free
SY89871UMGTR(1, 2) MLF-16 Industrial 871U with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
3
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC)...................................–0.5V to +4.0V
Input Voltage (VIN) ............................... –0.5V to VCC +0.3V
PECL Output Current (IOUT)
Continuous..........................................................50mA
Surge.................................................................100mA
VT Current (IVT)...................................................... ±100mA
Input Current IN, /IN (IIN) ..........................................±50mA
VREF-AC Sink/Source Current (IVREF-AC) ....................±2mA
Lead Temperature (soldering, 20 sec.) ..................... 260°C
Storage Temperature (TS) ........................–65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC).............................+2.375V to +3.63V
Ambient Temperature (TA) .........................–40°C to +85°C
Package Thermal Resistance(3)
MLF® (θJA)
Still-Air............................................................. 60°C/W
500lfpm ........................................................... 54°C/W
MLF® (ψJB)
Junction-to-board ............................................ 38°C/W
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage 2.37 3.60 V
ICC Power Supply Current No load, max VCC.5075mA
RIN Differential Input Resistance, 90 100 110 ý
(IN-to-/IN)
VIH Input HIGH Voltage, (IN, /IN) 0.1 VCC+0.3 V
VIL Input LOW Voltage, (IN, /IN) –0.3 VIH–0.1 V
VIN Input Voltage Swing Notes 5 0.1 VCC V
VDIFF_IN Differential Input Voltage Swing Notes 5, 6 0.2 V
|IIN| Input Current, (IN, /IN) Note 7 45 mA
VREF-AC Reference Voltage VCC–1.525 VCC–1.425 VCC–1.325 V
Notes:
1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional
operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. See “Timing Diagram” for VIN definition. VIN (max.) is specified when VT is floating.
6. See “Typical Operating Characteristics” section for VDIFF definition.
7. Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do
not apply a combination of voltages that causes the input current to exceed the maximum limit!
DC ELECTRICAL CHARACTERISTICS(4)
4
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IIH Input HIGH Current –125 20 µA
IIL Input LOW Current –300 µA
Note:
8. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameters are for
VCC = 2.5V. They vary 1:1 with VCC.
LVTTL/LVCMOS DC ELECTRICAL CHARACTERISTICS(8)
VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50ý to VCC –2V, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage VCC–1.145 VCC–1.020 VCC–0.895 V
VOL Output LOW Voltage VCC–1.945 VCC–1.820 VCC–1.695 V
VOUT Output Voltage Swing 550 800 1050 mV
VDIFF_OUT Differential Output Voltage Swing 1.10 1.6 2.1 V
(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(8)
5
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAM
V
IN
Swing
/
RESET
IN
/IN
/QB
QB
QA
/QA
t
PD
t
RR
V
CC/2
V
OUT
Swin
g
VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Output Toggle Frequency Output Swing ž 400mV 2.5 GHz
Maximum Input Frequency Note 10 3.2 GHz
tPD Differential Propagation Delay Input Swing < 400mV 460 580 710 ps
IN-to-QA or QB Input Swing ž 400mV 420 550 670 ps
tSKEW Within-Device Skew (Differential) Note 11 715 ps
QB0-to-QB1
Within-Device Skew (Differential) Note 11 12 30 ps
QA-to-QB
Part-to-Part Skew (Differential) Note 11 250 ps
tJITTER Cycle-to-Cycle Jitter Note 12 1ps
RMS
Total Jitter Note 13 10 psPP
tRR Reset Recovery Time 600 ps
tr, tfOutput Rise/Fall Times 70 150 250 ps
(20% to 80%)
Notes:
9. Measured with 400mV input signal, 50% duty cycle, all loading with 50ý to VCC–2V, unless otherwise stated.
10. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
11. Skew is measured between outputs under identical transitions.
12. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_cc =Tn–Tn+1,
where T is the time between rising edges of the output signal.
13. Total jitter definition: with an ideal clock input, of frequency - fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(9)
6
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, VIN = 400mV, TA = 25°C, RL = 50ý to VCC–2V, unless otherwise stated.
0
100
200
300
400
500
600
700
800
900
0
500
1000
1500
2000
2500
3000
3500
QA AMPLITUDE (mV)
FREQUENCY (MHz)
QA Output Amplitude
vs. Frequency
0
100
200
300
400
500
600
700
800
900
0 200 400 600 800 1000 1200
PROPAGATION DELAY (ps)
INPUT SWING (mV)
IN to Q Propagation Delay
vs. Input Swing
300
400
500
600
700
-40 -20 0 20 40 60 80 100 120
PROPAGATION DELAY (ps)
TEMPERATURE (°C)
IN to Q Propagation Delay
vs. Temperature
1.25GHz Output
TIME (100ps/div.)
Output Swing
(100mV/div.)
/Q
Q
2.5GHz Output
TIME (100ps/div.)
Output Swing
(100mV/div.)
/Q
Q
622MHz Output
TIME (1ns/div.)
Output Swing
(200mV/div.)
/QB0
QB0
/QA
QA
155.5MHz Output
QA@622MHz and QB@155.5MHz
÷4
7
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
INPUT BUFFER STRUCTURE
V
CC
GND
50Ω
50Ω
IN
V
T
/
IN
1.86kΩ
1.86kΩ1.86kΩ
1.86kΩ
Figure 2a. Simplified Differential Input Buffer
SY89871U
VCC
GND
S0
S1
/RESET
R25kΩ
R
Figure 2b. Simplified TTL/CMOS Input Buffer
V
IN,
V
OU
T
800mV
(typica
l)
1600mV (typica
l)
V
DIFF_IN
,
V
DIFF_OU
T
Figure 1a. Single-Ended Swing Figure 1b. Differential Swing
8
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
INPUT INTERFACE APPLICATIONS
CML IN
/IN
VTNC
ND
SY89871
VCC VCC
VREF-AC
NC
Figure 3a. DC-Coupled CML
Input Interface
CML IN
/IN
VT
G
ND
SY89871
U
V
CC
V
CC
V
REF-AC
V
CC
0.01µF
Figure 3b. AC-Coupled CML
Input Interface
PECL
IN
/IN
VT
GND
SY89871U
VCC VCC
VREF-AC
NC
0.01µF
VCC
Note:
For 3.3V, R
pd
= 50Ω.
For 2.5V, R
pd
= 19Ω.
R
pd
Figure 3c. DC-Coupled PECL
Input Interface
V
CC
0.01µF
PECL IN
/IN
V
T
G
ND
SY89871
U
V
CC
V
CC
GND V
REF-AC
R
pd
R
pd
N
ote:
F
or 3.3V, R
pd
= 100Ω.
F
or 2.5V, R
pd
= 50Ω.
Figure 3d. AC-Coupled PECL
Input Interface
LVDS IN
/IN
VTNC
G
ND
SY89871
U
V
CC
V
CC
V
REF-AC
NC
Figure 3e. LVDS
Input Interface
HSTL IN
/IN
VT
ND
SY89871
V
CC
V
CC
GND
NC V
REF-AC
Figure 3f. HSTL
Input Interface
Part Number Function Data Sheet Link
SY89874U 2.5GHz Any Diff. In-to-LVPECL Programmable http://www.micrel.com/product-info/products/sy89874u.shtml
Clock Divider and 1:2 Fanout Buffer
w/Internal Termination
MLF® Application Note http://www.amkor.com/products/notes_papers/mlf_appnote.pdf
HBW Solutions New Products and Applications http://www.micrel.com/product-info/products/solutions.shtml
RELATED PRODUCT AND SUPPORT DOCUMENTATION
9
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
LVPECL OUTPUT TERMINATION RECOMMENDATIONS
R2
82Ω
R2
82Ω
Z
O
= 50Ω
Z
O
= 50Ω
+3.3V +3.3V
V
t
= V
CC
—2
V
R1
130ΩR1
130Ω
+3.3V
Figure 4a. Parallel Termination–Thevenin Equivalent
Note:
1. For +2.5V systems: R1 = 250ý, R2 = 62.5ý.
Z = 50Ω
Z = 50Ω
50Ω50Ω
50Ω
+3.3V +3.3V
“source” “destination”
R
b
C1 (optional)
0.01µF
V
CC
Figure 4b. Three-Resistor “Y–Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to VT. For +3.3V systems Rb = 46ý to 50ý. For +2.5V systems Rb = 19ý.
4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.
+3.3V +3.3V
Z
O
= 50Ω
R2
82Ω
+3.3V +3.3V
R1
130ΩR1
130Ω
R2
82Ω
V
t
= V
CC
—2V
Q
/Q
R3
1kΩ
R4
1.6kΩ
V
t
= V
CC
—1.3V
Figure 4d. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. For +2.5V systems: R1 = 250ý, R2 = 62.5ý, R3 = 1.25ký, R4 = 1.2ký.
10
Precision Edge®
SY89871U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
16-PIN MicroLeadFrame® (MLF-16)
Package
EP- Exposed Pa
d
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
VEE
VEE
Heat Dissipation
PCB Thermal Consideration for 16-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form.
2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.