256-/1024-Position, Digital Potentiometers with
Maximum ±1% R-Tolerance Error and 20-TP Memory
AD5291/AD5292
Rev. D
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
Single-channel, 256-/1024-position resolution
20 kΩ, 50 kΩ, and 100 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error (resistor
performance mode)
20-times programmable wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+9 V to +33 V single-supply operation
±9 V to ±16.5 V dual-supply operation
SPI-compatible serial interface
Wiper setting readback
Power-on refreshed from 20-TP memory
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
FUNCTIONAL BLOCK DIAGRAM
A
W
B
RDAC
REGISTER
DATA
SERIAL
INTERFACE
SYNC
SCLK
DIN
POWER-ON
RESET
OTP
MEMORY
BLOCK
VLOGIC
SDO
EXT_CAP
V
DD
VSS GND
AD5291/
AD5292
RESET
RDY
07674-001
Figure 1.
GENERAL DESCRIPTION
The AD5291 and AD5292 are single-channel, 256-/1024-
position digital potentiometers1 that combine industry leading
variable resistor performance with nonvolatile memory (NVM)
in a compact package. These devices are capable of operating
across a wide voltage range, supporting both dual supply
operation at ±10.5 V to ±16.5 V and single supply operation at
+21 V to +33 V, while ensuring less than 1% end-to-end resistor
tolerance error and offering 20-time programmable (20-TP)
memory.
The guaranteed industry leading low resistor tolerance error
feature simplifies open-loop applications as well as precision
calibration and tolerance matching applications.
1 The terms digital potentiometer and RDAC are used interchangeably.
The AD5291 and AD5292 device wiper settings are controllable
through the SPI digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
20-TP memory. The AD5291 and AD5292 do not require any
external voltage supply to facilitate fuse blow, and there are 20
opportunities for permanent programming. During 20-TP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
The AD5291 and AD5292 are available in a compact 14-lead
TSSOP package. The part is guaranteed to operate over the
extended industrial temperature range of −40°C to +105°C.
AD5291/AD5292
Rev. D | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5291 .......................................... 3
Resistor Performance Mode Code Range ................................. 4
Electrical Characteristics—AD5292 .......................................... 6
Resistor Performance Mode Code Range ................................. 7
Interface Timing Specifications.................................................. 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 21
Theory of Operation ...................................................................... 22
Serial Data Interface................................................................... 22
Shift Register ............................................................................... 22
RDAC Register............................................................................ 22
20-TP Memory ........................................................................... 23
Write Protection ......................................................................... 23
Basic Operation .......................................................................... 24
20-TP Readback and Spare Memory Status ........................... 24
Shutdown Mode ......................................................................... 24
Resistor Performance Mode...................................................... 25
Reset ............................................................................................. 25
SDO Pin and Daisy-Chain Operation..................................... 25
RDAC Architecture.................................................................... 25
Programming the Variable Resistor......................................... 26
Programming the Potentiometer Divider............................... 26
EXT_CAP Capacitor.................................................................. 27
Terminal Voltage Operating Range ......................................... 27
Applications Information.............................................................. 28
High Voltage DAC...................................................................... 28
Programmable Voltage Source with Boosted Output ........... 28
High Accuracy DAC .................................................................. 28
Variable Gain Instrumentation Amplifier .............................. 28
Audio Volume Control .............................................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
9/10—Rev. C to Rev. D
Changes to SDO Pin and Daisy-Chain Operation Section....... 25
3/10—Rev. B to Rev. C
Changes to Revision History........................................................... 2
Changes to Figure 3 and Figure 4 Captions .................................. 9
3/10—Rev. A to Rev. B
Changes to Data Sheet Title ............................................................ 1
Changes to General Description Section ...................................... 1
Changes to Theory of Operation Section.................................... 22
12/09—Rev. 0 to Rev. A
Added 50 kΩ and 100 kΩ specifications .........................Universal
Changes to Features Section............................................................ 1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Added Table 3 ....................................................................................5
Changes to Table 4.............................................................................6
Changes to Table 5.............................................................................7
Added Table 6 ....................................................................................8
Change to Table 7 ..............................................................................8
Changes to Absolute Maximum Rating Section ........................ 10
Changes Table 9 .............................................................................. 11
Changes to Typical Performance Characteristics Section ........ 12
Changes to Ordering Guide.......................................................... 30
4/09—Revision 0: Initial Version
AD5291/AD5292
Rev. D | Page 3 of 32
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5291
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 8 Bits
Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL −1 +1 LSB
Nominal Resistor Tolerance (R-Perf Mode)3 ∆RAB/RAB See Table 2, Table 3 −1 ±0.5 +1 %
Nominal Resistor Tolerance (Normal Mode) ∆RAB/RAB ±7 %
Resistance Temperature Coefficient4 (∆RAB/RAB)/∆T × 106 Code = full-scale; See Figure 38 35 ppm/°C
Wiper Resistance RW Code= zero scale 60 100 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution N 8 Bits
Differential Nonlinearity5 DNL −0.5 +0.5 LSB
Integral Nonlinearity5 INL −0.5 +0.5 LSB
Voltage Divider Temperature Coefficient4 (∆VW/VW)/∆T × 106 Code = half-scale; See Figure 41 1.5 ppm/°C
Full-Scale Error VWFSE Code = full scale −2 +0.25 LSB
Zero-Scale Error VWZSE Code = zero scale 0 2 LSB
RESISTOR TERMINALS
Terminal Voltage Range6 V
A, VB, VW V
SS V
DD V
Capacitance A, Capacitance B4 CA, CB f = 1 MHz, measured to GND,
code = half-scale
85 pF
Capacitance W4 CW f = 1 MHz, measured to GND,
code = half-scale
65 pF
Common-Mode Leakage Current4 ICM V
A = VB = VW ±1 nA
DIGITAL INPUTS JEDEC compliant
Input Logic High4 VIH V
LOGIC = 2.7 V to 5.5 V 2.0 V
Input Logic Low4 VIL V
LOGIC = 2.7 V to 5.5 V 0.8 V
Input Current IIL V
IN = 0 V or VLOGIC ±1 μA
Input Capacitance4 CIL 5 pF
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4 VOH R
PULL_UP = 2.2 kΩ to VLOGIC V
LOGIC − 0.4 V
Output Low Voltage4 VOL R
PULL_UP = 2.2 kΩ to VLOGIC GND + 0.4 V V
Three-State Leakage Current −1 +1 μA
Output Capacitance4 COL 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD V
SS = 0 V 9 33 V
Dual-Supply Power Range VDD/VSS ±9 ±16.5 V
Positive Supply Current IDD V
DD/VSS = ±16.5 V 0.1 2 μA
Negative Supply Current ISS V
DD/VSS = ±16.5 V −2 −0.1 μA
Logic Supply Range VLOGIC 2.7 5.5 V
Logic Supply Current ILOGIC V
LOGIC = 5 V; VIH = 5 V or VIL = GND 1 10 μA
OTP Store Current4, 7 ILOGIC_PROG VIH = 5 V or VIL = GND 25 mA
OTP Read Current4, 8 ILOGIC_FUSE_READ VIH = 5 V or VIL = GND 25 mA
Power Dissipation9 P
DISS V
IH = 5 V or VIL = GND 8 110 μW
Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = ±15 V ± 10% %/%
R
AB = 20 kΩ 0.103
R
AB = 50 kΩ 0.039
R
AB = 100 kΩ 0.021
AD5291/AD5292
Rev. D | Page 4 of 32
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS5, 10
Bandwidth BW −3 dB, code = half-scale kHz
R
AB = 20 kΩ 520
R
AB = 50 kΩ 210
R
AB = 100 kΩ 105
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz dB
R
AB = 20 kΩ −93
R
AB = 50 kΩ −101
R
AB = 100 kΩ −106
VW Settling Time tS V
A = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale,
board capacitance = 170 pF
Code = full-scale, normal mode 750 ns
Code = full-scale, R-Perf mode 2.5 μs
Code = half-scale, normal mode μs
R
AB = 20 kΩ 2.5
R
AB = 50 kΩ 7
R
AB = 100 kΩ 14
Code = half-scale, R-Perf mode μs
R
AB = 20 kΩ 5
R
AB = 50 kΩ 9
R
AB = 100 kΩ 16
Resistor Noise Density eN_WB Code = half-scale, TA = 25°C, 0 kHz
to 200 kHz
nV/√Hz
R
AB = 20 kΩ 10
R
AB = 50 kΩ 18
R
AB = 100 kΩ 27
1 Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x02 to code 0xFF or between RWA at code 0xFD to
code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4 Guaranteed by design and characterization, not subject to production test.
5 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
7 Different from operating current; supply current for fuse program lasts approximately 550 μs.
8 Different from operating current; supply current for fuse read lasts approximately 550 μs.
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10 All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
RESISTOR PERFORMANCE MODE CODE RANGE
Table 2.
RAB = 20 kΩ
|VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V
Resistor
Tolerance per
Code RWB R
WA R
WB R
WA R
WB R
WA R
WB R
WA
1% R-Tolerance From 0x5A
to 0xFF
From 0x00
to 0xA5
From 0x7D
to 0xFF
From 0x00
to 0x82
From 0x7D
to 0xFF
From 0x00
to 0x82
N/A N/A
2% R-Tolerance From 0x23
to 0xFF
From 0x00
to 0xDC
From 0x2D
to 0xFF
From 0x00
to 0xD2
From 0x23
to 0xFF
From 0x00
to 0xDC
From 0x23
to 0xFF
From 0x00
to 0xDC
3% R-Tolerance From 0x1E
to 0xFF
From 0x00
to 0xE1
From 0x19
to 0xFF
From 0x00
to 0xE6
From 0x17
to 0xFF
From 0x00
to 0xE8
From 0x17
to 0xFF
From 0x00
to 0xE8
AD5291/AD5292
Rev. D | Page 5 of 32
Table 3.
RAB = 50 kΩ RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
Resistor Tolerance
per Code RWB R
WA R
WB R
WA R
WB R
WA R
WB R
WA
1% R-Tolerance From 0x2A
to 0xFF
From 0x00
to 0xD5
From 0x37
to 0xFF
From 0x00
to 0xC8
From 0x1E
to 0xFF
From 0x00
to 0xE1
From 0x14
to 0xFF
From 0x00
to 0xEB
2% R-Tolerance From 0x11
to 0xFF
From 0x00
to 0xEE
From 0x16
to 0xFF
From 0x00
to 0xE9
From 0x0A
to 0xFF
From 0x00
to 0xF5
From 0x0A
to 0xFF
From 0x00
to 0xF5
3% R-Tolerance From 0x0A
to 0xFF
From 0x00
to 0xF5
From 0x0D
to 0xFF
From 0x00
to 0xF2
From 0x07
to 0xFF
From 0x00
to 0xF8
From 0x07
to 0xFF
From 0x00
to 0xF8
AD5291/AD5292
Rev. D | Page 6 of 32
ELECTRICAL CHARACTERISTICS—AD5292
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 10 Bits
Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RAB =50 kΩ, 100 kΩ −2 +2 LSB
R-INL RAB =20 kΩ , |VDD − VSS| = 26 V to 33 V −2 +2 LSB
R-INL RAB =20 kΩ , |VDD − VSS| = 21 V to 26 V −3 +3 LSB
Nominal Resistor Tolerance (R-Perf Mode)3 ∆RAB/RAB See Table 5 and Table 6 −1 ±0.5 +1 %
Nominal Resistor Tolerance (Normal
Mode)4
∆RAB/RAB ±7 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 Code = full scale; See Figure 38 35 ppm/°C
Wiper Resistance RW Code= zero scale 60 100 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution N 10 Bits
Differential Nonlinearity5 DNL −1 +1 LSB
Integral Nonlinearity5 INL −1.5 +1.5 LSB
Voltage Divider Temperature Coefficient4 (∆VW/VW)/∆T × 106 Code = half scale; See Figure 41 5 ppm/°C
Full-Scale Error VWFSE Code = full scale −8 +1 LSB
Zero-Scale Error VWZSE Code = zero scale 0 8 LSB
RESISTOR TERMINALS
Terminal Voltage Range4 VA, VB, VW V
SS V
DD V
Capacitance A, Capacitance B6 C
A, CB f = 1 MHz, measured to GND,
code = half scale
85 pF
Capacitance W5 CW f = 1 MHz, measured to GND,
code = half scale
65 pF
Common-Mode Leakage Current4 ICM V
A = VB = VW ±1 nA
DIGITAL INPUTS JEDEC compliant
Input Logic High4 VIH V
LOGIC = 2.7 V to 5.5 V 2.0 V
Input Logic Low4 VIL V
LOGIC = 2.7 V to 5.5 V 0.8 V
Input Current IIL V
IN = 0 V or VLOGIC ±1 μA
Input Capacitance4 CIL 5 pF
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4 VOH R
PULL_UP = 2.2 kΩ to VLOGIC V
LOGIC − 0.4 V
Output Low Voltage4 VOL R
PULL_UP = 2.2 kΩ to VLOGIC GND + 0.4 V
Three-State Leakage Current −1 +1 μA
Output Capacitance4 COL 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD V
SS = 0 V 9 33 V
Dual-Supply Power Range VDD/VSS ±9 ±16.5 V
Positive Supply Current IDD V
DD/VSS = ±16.5 V 0.1 2 μA
Negative Supply Current ISS V
DD/VSS = ±16.5 V −2 −0.1 μA
Logic Supply Range VLOGIC 2.7 5.5 V
Logic Supply Current ILOGIC V
LOGIC = 5 V; VIH = 5 V or VIL = GND 1 10 μA
OTP Store Current6, 7 ILOGIC_PROG VIH = 5 V or VIL = GND 25 mA
OTP Read Current6, 8 ILOGIC_FUSE_READ VIH = 5 V or VIL = GND 25 mA
Power Dissipation9 P
DISS V
IH = 5 V or VIL = GND 8 110 μW
Power Supply Rejection Ratio6 PSSR ∆VDD/∆VSS = ±15 V ± 10% %/%
R
AB = 20 kΩ 0.103
R
AB = 50 kΩ 0.039
R
AB = 100 kΩ 0.021
AD5291/AD5292
Rev. D | Page 7 of 32
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS5, 10
Bandwidth BW −3 dB kHz
R
AB = 20 kΩ 520
R
AB = 50 kΩ 210
R
AB = 100 kΩ 105
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz dB
R
AB = 20 kΩ −93
R
AB = 50 kΩ −101
R
AB = 100 kΩ −106
VW Settling Time tS V
A = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale, board
capacitance = 170 pF
Code = full-scale, normal mode 750 ns
Code = full-scale, R-Perf mode 2.5 μs
Code = half-scale, normal mode μs
R
AB = 20 kΩ 2.5
R
AB = 50 kΩ 7
R
AB = 100 kΩ 14
Code = half-scale, R-Perf mode μs
R
AB = 20 kΩ 5
R
AB = 50 kΩ 9
R
AB = 100 kΩ 16
Resistor Noise Density eN_WB Code = half-scale, TA = 25°C, 0 kHz to
200 kHz
nV/√Hz
R
AB = 20 kΩ 10
R
AB = 50 kΩ 18
R
AB = 100 kΩ 27
1 Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x00B to code 0x3FF or between RWA at code 0x3F3 to
code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4 Guaranteed by design and characterization, not subject to production test.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
7 Different from operating current; supply current for fuse program lasts approximately 550 μs.
8 Different from operating current; supply current for fuse read lasts approximately 550 μs.
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10 All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
RESISTOR PERFORMANCE MODE CODE RANGE
Table 5.
RAB = 20 kΩ
|VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V
Resistor
Tolerance per
Code RWB R
WA R
WB R
WA R
WB R
WA R
WB R
WA
1% R-Tolerance From 0x15E
to 0x3FF
From 0x000
to 0x2A1
From 0x1F4
to 0x3FF
From 0x000
to 0x20B
From 0x1F4
to 0x3FF
From 0x000
to 0x20B
N/A N/A
2% R-Tolerance From 0x8C
to 0x3FF
From 0x000
to 0x373
From 0xB4
to 0x3FF
From 0x000
to 0x34B
From 0xFA
to 0x3FF
From 0x000
to 0x305
From 0xFA
to 0x3FF
From 0x000
to 0x305
3% R-Tolerance From 0x5A
to 0x3FF
From 0x000
to 0x3A5
From 0x64
to 0x3FF
From 0x000
to 0x39B
From 0x78
to 0x3FF
From 0x000
to 0x387
From 0x78
to 0x3FF
From 0x000
to 0x387
AD5291/AD5292
Rev. D | Page 8 of 32
Table 6.
RAB = 50 kΩ RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
Resistor
Tolerance per
Code RWB R
WA R
WB R
WA R
WB R
WA R
WB R
WA
1% R-Tolerance From 0x08C
to 0x3FF
From 0x000
to 0x35F
From 0x0B4
to 0x3FF
From 0x000
to 0x31E
From 0x04B
to 0x3FF
From 0x000
to 0x3B4
From 0x064
to 0x3FF
From 0x000
to 0x39B
2% R-Tolerance From 0X03C
to 0x3FF
From 0x000
to 0x3C3
From 0x050
to 0x3FF
From 0x000
to 0x3AF
From 0x028
to 0x3FF
From 0x000
to 0x3D7
From 0x028
to 0x3FF
From 0x000
to 0x3D7
3% R-Tolerance From 0X028
to 0x3FF
From 0x000
to 0x3D7
From 0x032
to 0x3FF
From 0x000
to 0x3CD
From 0x019
to 0x3FF
From 0x000
to 0x3E6
From 0x019
to 0x3FF
From 0x000
to 0x3E6
INTERFACE TIMING SPECIFICATIONS
VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter Limit1 Unit Description
t12 20 ns min SCLK cycle time
t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 10 ns min
SYNC to SCLK falling edge setup time
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min
SCLK falling edge to SYNC rising edge
t8 4003 ns min
Minimum SYNC high time
t9 14 ns min
SYNC rising edge to next SCLK fall ignore
t104 1 ns min
RDY rising edge to SYNC falling edge
t114 40 ns max
SYNC rising edge to RDY fall time
t124 2.4 μs max RDY low time, RDAC register write command execute time (R-Perf mode)
t124 410 ns max RDY low time, RDAC register write command execute time (normal mode)
t124 8 ms max RDY low time, memory program execute time
t124 1.5 ms min Software/hardware reset
t134 450 ns max RDY low time, RDAC register readback execute time
t134 1.3 ms max RDY low time, memory readback execute time
t144 450 ns max SCLK rising edge to SDO valid
tRESET 20 ns min
Minimum RESET pulse width (asynchronous)
tPOWER-UP5 2 ms max Power-on OTP restore time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 50 MHz.
3 Refer to t12 and t13 for RDAC register and memory commands operations.
4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.
5 Maximum time after VLOGIC is equal to 2.5 V.
DATA BITS
DB9 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BITS
C0C1
C2 D9 D8
C3
00
07674-003
Figure 2. Shift Register Content
AD5291/AD5292
Rev. D | Page 9 of 32
Timing Diagrams
t
4
t
3
t
2
t
5
t
7
t
6
D0D1
X
SYNC
SCLK
t
9
t
1
t
8
DIN
SDO
D6
D7 D2
XC3 C2
RDY
t
12
t
10
t
11
07674-004
RESET
t
RESET
Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1
D0D1
X
SYNC
SCLK
t
9
t
14
t
13
t
11
DIN
SDO
X
D0 X
XC3
RDY
D0
XX
C3
D0D1
C3
07674-005
Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1
AD5291/AD5292
Rev. D | Page 10 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 8.
Parameter Rating
VDD to GND −0.3 V to +35 V
VSS to GND +0.3 V to − 25 V
VLOGIC to GND −0.3 V to + 7 V
VDD to VSS 35 V
VA, VB, VW to GND VSS − 0.3 V, VDD+ 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VLOGIC + 0.3 V
EXT_CAP Voltage to GND −0.3 V to +7 V
IA, IB, IW
Continuous
RAB = 20 kΩ ±3 mA
RAB = 50 kΩ, 100 kΩ ±2mA
Pulsed1
Frequency > 10 kHz MCC2/d3
Frequency ≤ 10 kHz MCC2/√d3
Operating Temperature Range4 −40°C to +105°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.
Table 9. Thermal Resistance
Package Type θJA θ
JC Unit
14-Lead TSSOP 931 20 °C/W
1 JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow).
ESD CAUTION
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Maximum continuous current
3 Pulse duty factor.
4 Includes programming of OTP memory.
AD5291/AD5292
Rev. D | Page 11 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET
V
SS
A
W
RDY
SYNC
V
LOGIC
SCLK
B
V
DD
EXT_CAP
1
2
3
4
5
6
7
DIN
GND
14
13
12
11
10
9
8
AD5291/
AD5292
TOP VIEW
Not to Scale
SDO
07674-006
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1 RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory
default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the
logic high transition. Tie RESET to VLOGIC if not used.
2 VSS Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF
ceramic capacitors and 10 μF capacitors.
3 A Terminal A of RDAC. VSS ≤ VA ≤ VDD.
4 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
5 B Terminal B of RDAC. VSS ≤ VB ≤ VDD.
6 VDD Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
7 EXT_CAP External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
8 VLOGIC Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
9 GND Ground Pin, Logic Ground Reference.
10 DIN Serial Data Input. The AD5291 and AD5292 have a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
11 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 50 MHz.
12 SYNC Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The
selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high
before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the DAC.
13 SDO Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the shift register in daisy-chain mode or in readback mode.
14 RDY Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from
the RDAC register or memory.
AD5291/AD5292
Rev. D | Page 12 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C
+105°C
07674-106
R
AB
= 20k
Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-007
R
AB
= 20k
Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
1.0
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-010
R
AB
= 20k
Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5292)
07674-215
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
07674-211
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
07674-216
1.0
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
AD5291/AD5292
Rev. D | Page 13 of 32
0.15
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-011
R
AB
= 20k
Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292)
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-014
R
AB
= 20k
Figure 13. INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.2
–0.1
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-015
R
AB
= 20k
Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
07674-213
0.15
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
07674-207
0.8
–0.8
–0.6
–0.2
0
0.2
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
07674-203
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
AD5291/AD5292
Rev. D | Page 14 of 32
0.8
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C
+105°C
07674-018
R
AB
= 20k
Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292)
0.10
–0.20
–0.15
–0.10
–0.05
0
0.05
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C
+105°C
07674-019
R
AB
= 20k
Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292)
0.30
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-008
RAB = 20k
Figure 20. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
07674-209
0.8
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
07674-205
0.08
–0.16
–0.12
–0.08
–0.04
0
0.04
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
0.30
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
20k
50k
100k
07674-218
TEMPERATURE = 2 5°C
Figure 23. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
AD5291/AD5292
Rev. D | Page 15 of 32
0.14
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-009
R
AB
= 20k
Figure 24. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.25
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-012
R
AB
= 20k
Figure 25. R-INL in Normal Mode vs. Code vs. Temperature (AD5291)
0.03
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-013
R
AB
= 20k
Figure 26. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291)
07674-212
0.14
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 27. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
07674-217
0.25
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 28. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
07674-214
0.03
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 29. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
AD5291/AD5292
Rev. D | Page 16 of 32
0.25
–0.25
–0.15
–0.05
–0.20
–0.10
0
0.05
0.10
0.15
0.20
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-016
R
AB
= 20k
Figure 30. INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.14
–0.06
–0.02
0.02
–0.04
0
0.04
0.06
0.08
0.10
0.12
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-017
R
AB
= 20k
Figure 31. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0 32 64 96 128 160 192 224 256
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-020
Figure 32. INL in Normal Mode vs. Code vs. Temperature (AD5291)
07674-208
0.25
–0.25
–0.15
–0.05
–0.20
–0.10
0
0.05
0.10
0.15
0.20
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 33. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
07674-204
0.14
–0.06
–0.02
0.02
–0.04
0
0.04
0.06
0.08
0.10
0.12
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 34. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
07674-210
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0 32 64 96 128 160 192 224 255
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 35. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
AD5291/AD5292
Rev. D | Page 17 of 32
0.03
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07674-021
R
AB
= 20k
Figure 36. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
07674-022
450
400
350
300
250
200
150
100
50
0
–50
SUPPLY CURRENT (nA)
TEMPERATURE (°C)
–40–30–20–100 102030405060708090100
ILOGIC
VDD/VSS = ±15V
VLOGIC = +5V
IDD
ISS
Figure 37. Supply Current (IDD, ISS, ILOGIC) vs. Temperature
700
600
500
400
300
200
100
0
RHEOSTAT MODE TEMPCO (ppm/°C)
07674-024
0 256 512 768 1023
0 64 128 192 255
AD5292
AD5291
CODE (Decimal)
50k
20k
100k
V
DD
= 30V,
V
SS
= 0V
Figure 38. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
07674-206
0.03
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0 32 64 96 128 160 192 224 255
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 39. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
07674-031
0.20
0.18
0.16
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY CURRENT I
LOGIC
(mA)
DIGITAL INPUT VOLTAGE (V)
V
DD
= ±15V
Figure 40. Supply Current ILOGIC vs. Digital Input Voltage
700
600
500
400
300
200
100
0
POTENTIOMETER MODE TEMPCO (ppm/°C)
07674-023
0 256 512 768 1023
0 64 128 192 255
AD5292
AD5291
CODE (Decimal)
V
DD
= 30V
V
SS
= 0V
50k
20k
100k
Figure 41. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code
AD5291/AD5292
Rev. D | Page 18 of 32
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
1M100k10k1k10010
07674-025
GAIN (dB)
FREQUENCY (Hz)
AD5292 (AD5291)
0x200 (0x80)
0x100 (0x40)
0x080 (0x20)
0x040 (0x10)
0x020 ( 0x08)
0x010 (0x04)
0x008 (0x02)
0x004 (0x01)
0x002 0x001
Figure 42. 20 kΩ Gain vs. Frequency vs. Code
–50
–40
–30
–10
0
10 1M100k10k1k100
GAIN (dB)
FREQUENCY (Hz)
0x200 (0x80)
0x080 (0x20)
0x020 ( 0x08)
0x010 (0x04)
0x004 (0x01)
0x002 0x001
AD5292 (AD5291)
–20
–60
07674-200
0x040 (0x10)
0x008 (0x02)
0x100 (0x40)
Figure 43. 50 kΩ Gain vs. Frequency vs. Code
07674-027
0
–120
–105
–90
–75
–60
–45
–30
–15
THD + N (dB)
FREQUENCY (Hz)
100 1k 10k 100k
V
DD
/V
SS
= ±15V
CODE = HALF SCALE
V
IN
= 1V rms
Noise BW = 22kHz
50k
20k
100k
Figure 44. THD + Noise vs. Frequency
–65
–60
–50
–45
–40
–35
–30
–25
–15
–10
–5
0
11100k10k1k10010
GAIN (dB)
FREQUENCY (Hz)
M
0x200 (0x80)
0x100 (0x40)
0x080 (0x20)
0x040 (0x10)
0x020 ( 0x08)
0x010 (0x04)
0x008 (0x02)
0x004 (0x01)
0x002
0x001
AD5292 (AD5291)
–20
–55
–67.5
07674-201
Figure 45. 100 kΩ Gain vs. Frequency vs. Code
–70
–60
–50
–40
–30
–20
–10
0
100 1k 10k
FREQUENCY (Hz)
100k 1M
100k
20k
50k
07674-026
PSRR (dB)
Figure 46. Power Supply Rejection Ratio vs. Frequency
–140
–120
–100
–80
–60
–40
–20
0
0.001 0.01 0.1 1 10
THD + N (dB)
AMPLITUDE (V rms)
07674-220
V
DD
/V
SS
= ±15V,
CODE = HALF SCALE
f
IN
= 1kHz
NOISE BW = 22kHz
50k
20k
100k
Figure 47. THD + Noise vs. Amplitude
AD5291/AD5292
Rev. D | Page 19 of 32
0
100,000
200,000
300,000
400,000
500,000
600,000
700,000
BANDWIDTH (Hz)
800,000
900,000
1,000,000
CODE (Decimal)
5120
12864321680
128 2566432168
07674-222
20k – 0pF
20k – 75pF
20k – 150pF
20k – 250pF
50k – 0pF
50k – 75pF
50k – 150pF
50k – 250pF
100k – 0pF
100k – 75pF
100k – 150pF
100k – 250pF
AD5292
AD5291
Figure 48. Bandwidth vs Code vs Net Capacitance
07674-034
35
30
25
–5
20
15
10
5
0
–0.4 1.21.00.80.60.40.20–0.2
SUPPLY CURRENT I
DD
(mA)
TIME (ms)
Figure 49. IDD Waveform While Blowing/Reading Fuse
07674-033
35
–5
0
5
10
15
20
25
30
VOLTAGE (V)
TIME (µs)
VWB
, CODE: FULL SCALE,
NORMAL MODE
SYNC
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDD/VSS = 30V/0V
VLOGIC = 5V
VA = VDD
VB = VSS
VWB, CODE: HALF-SCALE,
NORMAL MODE
VWB, CODE: HALF-SCALE,
R-PERF MODE
20k
50k
100k
20k
50k
100k
VWB
, CODE: FULL SCALE,
R-PERF MODE
Figure 50. 20kΩ Large-Signal Settling Time from Code Zero Scale
8
0
1
2
3
4
5
6
7
0 256 512 768 1023
0 64 128 192 255
AD5292
AD5291
THEORETICAL I
WB_MAX
(mA)
CODE (Decimal)
07674-029
V
DD
/V
SS
= 30V/0V
V
A
= V
DD
V
B
= V
SS
50k
20k
100k
Figure 51. Theoretical Maximum Current vs. Code
07674-035
1.2
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
VOLTAGE (V)
TIME (µs)
–2 0 2 4 6 8 10 12 14 16
V
DD
/V
SS
= ±15V
V
LOGIC
= +5V
V
A
= V
DD
V
B
= V
SS
50k
20k
100k
Figure 52. Maximum Transition Glitch
40
32
24
–40
–32
–24
–16
–8
0
8
16
–0.5 0 5 10 15 20 25 30 35 40 45
VOLTAGE (V)
TIME (µs)
VDD/VSS = ±15V
VA= VDD
VB= VSS
CODE = HALF CODE
07674-032
Figure 53. Digital Feedthrough
AD5291/AD5292
Rev. D | Page 20 of 32
07674-056
NUMBER OF CODES (AD5292)
300
250
200
150
100
50
0
NUMBER OF CODES (AD5291)
75.0
62.5
50.0
37.5
25.0
12.5
0
TEMPERATURE (°C)
–40–30–20–100 102030405060708090100
V
DD
/V
SS
= ±15V
50k
20k
100k
07674-036
6
0
–1
1
2
3
4
5
VOLTAGE (V)
TIME (ms)
V
DD
/V
SS
= ±15V
V
LOGIC
= +5V
–1.0
–0.4
0.2
0.8
1.4
2.0
2.6
3.2
3.8
4.4
5.0
5.6
6.2
6.8
7.4
8.0
8.6
Figure 54. VEXT_CAP Waveform While Reading Fuse Or Calibration Figure 56. Code Range > 1% R-Tolerance Error vs. Temperature
07674-037
8
–2
0
2
3
6
VOLTAGE (V)
TIME (ms)
V
DD
/V
SS
= ±15V
V
LOGIC
= +5V
–2.0
–0.8
0.4
1.6
2.8
4.0
5.2
6.4
7.6
8.8
10.0
11.2
12.4
13.6
14.8
16.0
17.2
20.0
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
21 26 30 33
VOLTAGE VDD/VSS
NUMBER OF CODES (AD5292)
NUMBER OF CODES (AD5291)
80
0
10
20
30
40
50
60
70
07674-219
VA = VDD
VB = VSS
TEMPERATURE = 25°C
50k
20k
100k
Figure 57. Code Range > 1% R-Tolerance Error vs. Voltage
Figure 55. VEXT_CAP Waveform While Writing Fuse
AD5291/AD5292
Rev. D | Page 21 of 32
TEST CIRCUITS
Figure 58 to Figure 63 define the test conditions used in the Specifications section.
A
W
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
07674-041
Figure 58. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
A
W
B
DUT
V
MS
V+
V
+ = V
DD
1LSB = V+/2
N
07674-042
Figure 59. Potentiometer Divider Nonlinearity Error
(INL, DNL)
+
–
DUT
CODE = 0x00
0.1V
V
SS
TO V
DD
R
WB
=0.1
V
I
WB
R
W
= R
WB
2
I
WB
W
B
A = NC
0
7674-043
Figure 60. Wiper Resistance
AW
BV
MS
~
V
A
V
DD
V+
V+ = V
DD
± 10%
V
MS
%
V
DD
%
PSS (%/%) =
PSRR (dB) = 20 log V
MS
V
DD
07674-044
Figure 61. Power Supply Sensitivity (PSS, PSRR)
OFFSET
GND
A
B
DUT
W
+15
V
V
IN
V
OUT
OP42
–15V
2.5V
0
7674-047
Figure 62. Gain vs. Frequency
V
SS
I
CM
W
B
V
DD
DUT
GND
A
NC = NO CONNECT
NC
–15V
GND
+15V
NC
+15
V
+15V –15V
–15V
GND
GND
GND
07674-048
Figure 63. Common-Mode Leakage Current
AD5291/AD5292
Rev. D | Page 22 of 32
THEORY OF OPERATION
The AD5291 and AD5292 digital potentiometers are designed to
operate as true variable resistors for analog signals that remain
within the terminal voltage range of VSS < VTERM < VDD. The
patented ±1% resistor tolerance feature helps to minimize the total
RDAC resistance error, which reduces the overall system error
by offering better absolute matching and improved open-loop
performance. The digital potentiometer wiper position is
determined by the RDAC register contents. The RDAC register
acts as a scratchpad register, allowing as many value changes as
necessary to place the potentiometer wiper in the correct
position. The RDAC register can be programmed with any
position setting using the standard SPI interface by loading the
16-bit data-word. Once a desirable position is found, this value
can be stored in a 20-TP memory register. Thereafter, the wiper
position is always restored to that position for subsequent power-
up. The storing of 20-TP data takes approximately 6 ms; during
this time, the shift register is locked, preventing any changes from
taking place. The RDY pin identifies the completion of this 20-
TP storage.
SERIAL DATA INTERFACE
The AD5291 and AD5292 contain a serial interface (SYNC,
SCLK, DIN and SDO) that is compatible with SPI interface
standards, as well as most DSPs. The part allows writing of data
via the serial interface to every register.
SHIFT REGISTER
The AD5291 and AD5292 shift register is 16 bits wide (see
Figure 2). The 16-bit input word consists of two unused bits
(set to 0), followed by four control bits, and 10 RDAC data bits.
For the AD5291, the lower two RDAC data bits are don’t cares if
the RDAC register is read from or written to. Data is loaded MSB
first (Bit DB15). The four control bits determine the function of
the software command (see Table 11). Figure 3 shows a timing
diagram of a typical AD5291 and AD5292 write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is
loaded from the DIN pin. When SYNC returns high, the serial
data-word is decoded according to the commands in .
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5291 and AD5292 have an
internal counter that counts a multiple of 16 bits (a frame) for
proper operation. For example, AD5291 and AD5292 work with
a 32-bit word but does not work properly with a 31-bit or 33-bit
word. The AD5291 and AD5292 do not require a continuous
SCLK, when
Table 1 1
SYNC is high, and all serial interface pins should
be operated at close to the VLOGIC supply rails to minimize
power consumption in the digital input buffers.
RDAC REGISTER
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with all zeros, the wiper is connected to Terminal B of
the variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
Table 11. Command Operation Truth Table
Command Bits [DB13:DB10] Data Bits [DB9:DB0]1
Command C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X NOP command: do nothing.
1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D12 D02 Write contents of serial data to RDAC.
2 0 0 1 0 X X X X X X X X X X Read RDAC wiper setting from the SDO
output in the next frame.
3 0 0 1 1 X X X X X X X X X X Store wiper setting: store RDAC setting
to 20-TP memory.
4 0 1 0 0 X X X X X X X X X X Reset: refresh RDAC with 20-TP stored
value.
5 0 1 0 1 X X X X X D4 D3 D2 D1 D0 Read contents of 20-TP memory, or
status of 20-TP memory, from the SDO
output in the next frame.
6 0 1 1 0 X X X X X X D3 D2 D1 D0 Write contents of serial data to control
register.
7 0 1 1 1 X X X X X X X X X X Read control register from the SDO
output in the next frame.
8 1 0 0 0 X X X X X X X X X D0 Software shutdown.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown mode).
1 X = don’t care.
2 In the AD5291, this bit is a don’t care.
AD5291/AD5292
Rev. D | Page 23 of 32
20-TP MEMORY
Once a desirable wiper position is found, the contents of the
RDAC register can be saved into a 20-TP memory register
(see Tabl e 12). Thereafter, the wiper position is always set at that
position for any future on-off-on power supply sequence. The
AD5291 and AD5292 have an array of 20 one-time programmable
(OTP) memory registers. When the desired word is programmed
to 20-TP memory, the device automatically verifies that the
program command was successful. The verification process
includes margin testing. Bit C3 of the control register can be
polled to verify that the fuse program command was successful.
Programming data to 20-TP memory consumes approximately
25 mA for 550 µs and takes approximately 8 ms to complete.
During this time, the shift register is locked, preventing any
changes from taking place. The RDY pin can be used to monitor
the completion of the 20-TP memory program and verification.
No change in supply voltage is required to program the 20-TP
memory. However, a 1 µF capacitor on the EXT_CAP pin is
required (see Figure 68). Prior to 20-TP activation, the AD5291
and AD5292 preset to midscale on power-up.
WRITE PROTECTION
On power-up, the shift register write commands for both the
RDAC register and the 20-TP memory register are disabled.
The RDAC write protect bit, C1 of the control register (see
Table 1 3 and Table 14), is set to 0 by default. This disables any
change of the RDAC register content regardless of the software
commands, except that the RDAC register can be refreshed
from the 20-TP memory using the software reset command
(Command 4) or through hardware by the RESET pin. To enable
programming of the variable resistor wiper position (program-
ming the RDAC register), the write protect bit, C1 of the control
register, must first be programmed. This is accomplished by
loading the shift register with Command 6 (see ). To
enable programming of the 20-TP memory block bit, C0 of the
control register (set to 0 by default) must first be set to 1.
Table 1 1
Table 12. Write and Read to RDAC and 20-TP Memory
DIN SDO Action
0x1803 0xXXXX Enable update of wiper position and 20-TP memory contents through digital interface.
0x0500 0x1803 Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.
0x0800 0x0500 Prepare data read from the RDAC register.
0x0C00 0x0100 Stores RDAC register content into 20-TP memory. The 16-bit word appears out of SDO, where the last 10 bits
contain the contents of the RDAC register (0x100).
0x1C00 0x0C00 Prepare data read from the control register.
0x0000 0x000X NOP Instruction 0 sends 16-bit word out of SDO, where the last four bits contain the contents of the control
register. If Bit C3 = 1, the fuse program command is successful.
Table 13. Control Register Bit Map1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X X X X X X C3 C2 C1 C0
1 X = don’t care.
Table 14. Control Register Function
Bit Name Description
C0 20-TP program enable
0 = 20-TP program disabled (default)
1 = enable device for 20-TP program
C1 RDAC register write protect
0 = wiper position frozen to value in memory (default)1
1 = allow update of wiper position through digital Interface
C2 Calibration enable
0 = resistor performance mode enabled (default)
1 = normal mode enabled
C3 20-TP memory program success
0 = fuse program command unsuccessful (default)
1 = fuse program command successful
1 Wiper position frozen to value last programmed in 20-TP memory. Wiper is frozen to midscale if 20-TP memory has not been previously programmed.
AD5291/AD5292
Rev. D | Page 24 of 32
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the shift register with Command 1 (see Table 11) and the desired
wiper position data. When the desired wiper position is deter-
mined, the user can load the shift register with Command 3
(see Tabl e 11), which stores the wiper position data in the 20-TP
memory register. After 6 ms, the wiper position is permanently
stored in the 20-TP memory. The RDY pin can be used to moni-
tor the completion of this 20-TP program. Table 12 provides a
programming example, listing the sequence of serial data input
(DIN) words with the serial data output appearing at the SDO
pin in hexadecimal format.
20-TP READBACK AND SPARE MEMORY STATUS
It is possible to read back the contents of any of the 20-TP
memory registers through SDO by using Command 5 (see
Table 1 1). The lower five LSB bits (D0 to D4) of the data byte
select which memory location is to be read back (see Table 16).
Data from the selected memory location are clocked out of the
SDO pin during the next SPI operation, where the last 10 bits
contain the contents of the specified memory location.
It is also possible to calculate the address of the most recently
programmed memory location by reading back the contents of
read-only Memory Address 0x14 and Memory Address 0x15
using Command 5. The data bytes read back from Memory
Address 0x014 and Memory Address 0x015 are thermometer
encoded versions of the address of the last programmed
memory location.
For the example outlined in Table 15, the address of the last
programmed location is calculated as
(Number of Bits = 1 in Memory Address 0x14) + (Number
of Bits = 1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17
(0x10)
If no memory location has been programmed, then the address
generated is −1.
SHUTDOWN MODE
The AD5291 and AD5292 can be placed in shutdown mode by
executing the software shutdown command, Command 8 (see
Table 1 1), and setting the LSB, D0, to 1. This feature places the
RDAC in a special state in which Terminal A is open-circuited,
and Wiper W is connected to Terminal B. The contents of the
RDAC register are unchanged by entering shutdown mode.
However, all commands listed in Table 11 are supported while
in shutdown mode. Execute Command 8 (see Table 1 1 ), and set
the LSB, D0, to 0 to exit shutdown mode.
Table 15. Example 20-TP Memory Readback
DIN SDO Action
0x1414 0xXXXX Prepares data read from Memory Address 0x14.
0x1415 0x03FF Prepares data read from Memory Address 0x15. Sends 16-bit word out of SDO, where the last 10 bits contain the
contents of Memory Address 0x14.
0x0000 0x00FF NOP Command 0 sends 16-bit word out of SDO, where last 10-bits contain the contents of Memory Address 0x15.
0x1410 0x0000 Prepares data read from memory location 0x10.
0x0000 0xXXXX NOP Instruction 0 sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x10 (17).
Table 16. Memory Map of Command 5
Data Bits [DB9:DB0]1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Register Contents
X X X X X 0 0 0 0 0 1st programmed wiper location (0x00)
X X X X X 0 0 0 0 1 2nd programmed wiper location (0x01)
X X X X X 0 0 0 1 0 3rd programmed wiper location (0x02)
X X X X X 0 0 0 1 1 4th programmed wiper location (0x03)
X X X X X 0 0 1 0 0 5th programmed wiper location (0x04)
… … … … … … … … … … …
X X X X X 0 1 0 0 1 10th programmed wiper location (0x09)
X X X X X 0 1 1 1 0 15th programmed wiper location (0x0E)
X X X X X 1 0 0 1 1 20th programmed wiper location (0x13)
X X X X X 1 0 1 0 0 Programmed memory status (thermometer encoded)2 (0x14)
X X X X X 1 0 1 0 1 Programmed memory status (thermometer encoded)2 (0x15)
1 X = don’t care.
2 Allows the user to calculate the remaining spare memory locations.
AD5291/AD5292
Rev. D | Page 25 of 32
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
that is, code = half scale, RWB = 10 kΩ ± 100 Ω. See Table 2
(AD5291) or Table 5 (AD5292) to check which codes achieve
±1% resistor tolerance. The resistor performance mode is
activated by programming Bit C2 of the control register (see
Table 1 3 and Table 14). The typical settling time is shown in
Figure 50.
RESET
A low-to-high transition of the hardware RESET pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291 and AD5292 can also be
reset through software by executing Command 4 (see ).
If no 20-TP memory location is programmed, then the RDAC
register loads with midscale upon reset. The control register is
restored with default bits; see .
Table 11
Table 1 4
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting, 50-TP values and
control register using Command 2, Command 5 and Command 7,
respectively (see Table 11) or the SDO pin can be used in daisy-
chain mode. Data is clocked out of SDO on the rising edge of
SCLK. The SDO pin contains an open-drain N-channel FET
that requires a pull-up resistor if this pin is used. To place the
pin in high impedance and minimize the power dissipation
when the pin is used, the 0x8001 data word followed by
Command 0 should be sent to the part. Table 17 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 64, users need to
tie the SDO pin of one package to the DIN pin of the next
package. Users may need to increase the clock period, because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices.
When two AD5291 and AD5292 devices are daisy-chained, 32
bits of data are required. The first 16 bits go to U2, and the
second 16 bits go to U1. Hold the SYNC pin low until all 32 bits
are clocked into their respective shift registers. The SYNC pin is
then pulled high to complete the operation.
Keep the SYNC pin low until all 32 bits are clocked into their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
DIN SDO
SCLK SCLK
R
P
2.2k
DIN SDO
U1 U2
AD5291/
AD5292
AD5291/
AD5292
SYNC
V
LOGIC
MICRO-
CONTROLLER
SCLK SS
MOSI
SYNC
07674-050
Figure 64. Daisy-Chain Configuration Using SDO
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5291 and AD5292 employ
a three-stage segmentation approach, as shown in Figure 65.
The AD5291 and AD5292 wiper switches are designed with the
transmission gate CMOS topology and with the gate voltages
derived from VDD and VSS.
R
W
S
W
W
R
W
8-/10-BIT
ADDRESS
DECODER
A
R
L
R
L
R
M
R
M
B
R
M
R
M
R
L
R
L
07674-051
Figure 65. Simplified RDAC Circuit
Table 17. Minimize Power Dissipation at SDO Pin
DIN SDO1 Action
0xXXXX 0xXXXX Last user command sent to the digipot
0x8001 0xXXXX Prepares the SDO pin to be placed in high impedance mode
0x0000 High impedance The SDO pin is placed in high impedance
1 X is don’t care.
AD5291/AD5292
Rev. D | Page 26 of 32
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The AD5291 and AD5292 operate in rheostat mode when only
two terminals are used as a variable resistor. The unused
terminal can be left floating or tied to the W terminal, as shown in
Figure 66.
W
A
B
W
A
B
W
A
B
07674-052
Figure 66. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024
tap points accessed by the wiper terminal. The 8-/10-bit data in
the RDAC latch is decoded to select one of the 256/1024
possible wiper settings. The AD5291 and AD5292 contain an
internal ±1% resistor performance mode that can be disabled or
enabled (this is enabled by default), by programming Bit C2 of
the control register (see Table 13 and Table 14). The digitally
programmed output resistance between the W terminal and the
A terminal, RWA , and between the W terminal and B terminal,
RWB, is internally calibrated to give a maximum of ±1% absolute
resistance error across a wide code range. As a result, the
general equations for determining the digitally programmed
output resistance between the W terminal and B terminal are
AD5291:
AB
WB R
D
DR ×= 256
)( (1)
AD5292:
AB
WB R
D
DR ×= 1024
)( (2)
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W terminal and the A terminal also produces a
digitally controlled complementary resistance, RWA. RWA is also
calibrated to give a maximum of 1% absolute resistance error.
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
AD5291:
ABWA R
D
DR ×
−
=256
256
)( (3)
AD5292:
ABWA R
D
DR ×
−
=1024
1024
)( (4)
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 120 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W
and Terminal B, to the maximum continuous current of ±3 mA or
to the pulse current specified in Table 8 . Otherwise, degradation
or possible destruction of the internal resistors may occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
the wiper to B and at the wiper to A that is proportional to the
input voltage at A to B, as shown in Figure 67. Unlike the polarity
of VDD to GND, which must be positive, voltage across A to B,
W to A, and W to B can be at either polarity.
W
A
B
V
IN
V
OUT
07674-053
Figure 67. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is
equal to the voltage applied across Terminal A and Terminal B,
divided by the 256/1024 positions of the potentiometer divider.
The general equations defining the output voltage at VW with
respect to ground for any valid input voltage applied to Terminal A
and Terminal B are
AD5291:
B
A
WV
D
V
D
DV ×
−
+×= 256
256
256
)( (5)
AD5292:
B
A
WV
D
V
D
DV ×
−
+×= 1024
1024
1024
)( (6)
If using the AD5291 and AD5292 in voltage divider mode as
shown in Figure 67, then the ±1% resistor tolerance calibration
feature reduces the error when matching with discrete resistors.
However, it is recommended to disable the internal ±1% resistor
tolerance calibration feature by programming Bit C2 of the
control register (see Table 13 and Table 14) to optimize wiper
position update rate. In this configuration, the RDAC is ratiome-
tric and resistor tolerance error does not affect performance.
AD5291/AD5292
Rev. D | Page 27 of 32
Operation of the digital potentiometer in the voltage divider
mode results in a more accurate operation over temperature.
Unlike the rheostat mode, the output voltage is dependent
mainly on the ratio of the internal resistors, RWA and RWB, and
not the absolute values. Therefore, the temperature drift reduces
to 5 ppm/°C.
The ground pins of the AD5291 and AD5292 devices are
primarily used as a digital ground reference. To minimize the
digital ground bounce, the AD5291 and AD5292 ground
terminals should be joined remotely to the common ground.
The digital input control signals to the AD5291 and AD5292
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the Specifications section.
EXT_CAP CAPACITOR
Power-Up Sequence
A 1 µF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 68) on power-up and throughout the operation
of the AD5291 and AD5292.
To ensure that the AD5291 and AD5292 power up correctly, a
1 µF capacitor must be connected to the EXT_CAP pin. Because
there are diodes to limit the voltage compliance at Terminal A,
Terminal B, and Terminal W (see Figure 69), it is important to
power VDD and VSS first before applying any voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forward-
biased such that VDD and VSS are powered up unintentionally.
The ideal power-up sequence is GND, VSS, VLOGIC and VDD, the
digital inputs, and then VA, VB, and VW. The order of powering
up VA, VB, VW, and the digital inputs is not important as long as
they are powered after VDD, VSS, and VLOGIC.
AD5291/
AD5292
GND
C1
1µF
OTP
MEMORY
BLOCK
07674-054
EXT_CAP
Figure 68. Hardware Setup for EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE Regardless of the power-up sequence and the ramp rates of the
power supplies, after VLOGIC is powered, the power-on preset
activates, restoring the 20-TP memory value to the RDAC register.
The positive VDD and negative VSS power supplies of the
AD5291 and AD5292 define the boundary conditions for
proper 3-terminal digital potentiometer operation. Supply
signals present on Terminal A, Terminal B, and Terminal W
that exceed VDD or VSS are clamped by the internal forward-
biased diodes (see Figure 69).
V
SS
V
DD
A
W
B
07674-055
Figure 69. Maximum Terminal Voltages Set by VDD and V SS
AD5291/AD5292
Rev. D | Page 28 of 32
APPLICATIONS INFORMATION
HIGH VOLTAGE DAC
The AD5292 can be configured as a high voltage DAC, with
output voltage as high as 33 V. The circuit is shown in Figure 70.
The output is
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+××=
1
2
1V2.1
1024
)( R
RD
DVOUT (7)
where D is the decimal code from 0 to 1023.
07674-153
AD5292
U2
AD8512
V+
V–
AD8512
V
OUT
V
DD
U1B
V
DD
R
BIAS
A
DR512
D1
R
2
R
1
B
20k
U1A
Figure 70. High Voltage DAC
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustments such as a
laser diode or tunable laser, a boosted voltage source can be
considered; see Figure 71.
07674-155
W
SIGNAL
C
C
R
BIAS
LD
V
IN
A
B
V
OUT
U1
AD5292
U3 2N7002
U2 I
L
OP184
Figure 71. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces VOUT to
be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-channel
FET (U3). The N-Channel FET power handling must be adequate
to dissipate (VIN − VOUT) × IL power. This circuit can source a
maximum of 100 mA with a 33 V supply.
HIGH ACCURACY DAC
It is possible to configure the AD5292 as a high accuracy DAC
by optimizing the resolution of the device over a specific
reduced voltage range. This is achieved by placing external
resistors on either side of the RDAC, as shown in Figure 72.
The improved ±1% R-Tolerance specification greatly reduces
error associated with matching to discrete resistors.
3
1024
)1024(
1
1024
3
)(
)(
)( RRR
VRR
DV
AB
D
DD
AB
D
OUT +×+
×
×
+
=− (8)
07674-154
AD5292
U1
V
OUT
B
R
2
20k
R
1
R
3
±1%
OP1177
V+
V–
V
DD
V
DD
U2
Figure 72. Optimizing Resolution
VARIABLE GAIN INSTRUMENTATION AMPLIFIER
The AD8221 in conjunction with the AD5291 and AD5292 and
the ADG1207, as shown in Figure 73, make an excellent
instrumentation amplifier for use in data acquisition systems.
The data acquisition system’s low distortion and low noise
enable it to condition signals in front of a variety of ADCs.
07674-156
AD8221
AD5292
+V
IN1
V
DD
V
OU
T
V
SS
A
DG1207
+V
IN4
–V
IN1
–V
IN4
Figure 73. Data Acquisition System
The gain can be calculated by using Equation 9.
()
AB
RD
DG ×
+= 1024
k4.49
1)( (9)
AD5291/AD5292
Rev. D | Page 29 of 32
AUDIO VOLUME CONTROL
The excellent THD performance and high voltage capability
make the AD5291 and AD5292 ideal for a digital volume
control as an audio attenuator or gain amplifier. A typical
problem in these systems is that a large step change in the
volume level at any arbitrary time can lead to an abrupt
discontinuity of the audio signal causing an audible zipper
noise. To prevent this, a zero-crossing window detector can be
inserted to the SYNC line to delay the device update until the
audio signal crosses the window. Because the input signal can
operate on top of any dc level rather than absolute zero volt
level, zero-crossing in this case means the signal is ac-coupled,
and the dc offset level is the signal zero reference point.
The configuration to reduce zipper noise is shown in Figure 74,
and the results of using this configuration is shown in Figure 75.
The input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B. U6 is
used to establish the signal zero reference. The upper limit of
the comparator is set above its offset and, therefore, the output
pulses high whenever the input falls between 2.502 V and 2.497 V
(or 0.005 V window) in this example. This output is AND’ed
with the SYNC signal such that the AD5291 and AD5292
updates whenever the signal crosses the window. To avoid a
constant update of the device, the SYNC signal should be
programmed as two pulses, rather than as one.
In Figure 75, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
07674-157
R1
100k
R2
200
5V
V
IN
V+
V–
AD8541
5V
U6
R3
100k
R4
90k
R5
10k
C1
1µF
VDD
VSS
SCLK
SDIN
V+
V–
AD5292
20k
+15V
–15V
C3
0.1µF
C2
0.1µF
A
B
W
GND
SDIN
SCLK
U1
VCC
GND
VCC
GND
ADCMP371
ADCMP371
+15V
–15V
+5V
+5V
U3
U2
VOU
T
U5
U4A
U4B
16
2
4
5
7408
7408 SYNC
SYNC
Figure 74. Audio Volume Control with Zipper Noise Reduction
0
7674-158
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
1
2
Figure 75. Zipper Noise Detector
AD5291/AD5292
Rev. D | Page 30 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (kΩ) Resolution Memory Temperature Range Package Description Package Option
AD5291BRUZ-20 20 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5291BRUZ-20-RL7 20 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5291BRUZ-50 50 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5291BRUZ-50-RL7 50 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5291BRUZ-100 100 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5291BRUZ-100-RL7 100 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5292BRUZ-20 20 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5292BRUZ-20-RL7 20 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5292BRUZ-50 50 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5292BRUZ-50-RL7 50 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5292BRUZ-100 100 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
AD5292BRUZ-100-RL7 100 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14
EVAL-AD5292EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD5291/AD5292
Rev. D | Page 31 of 32
NOTES
AD5291/AD5292
Rev. D | Page 32 of 32
NOTES
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07674-0-9/10(D)
