PRELIMINARY CY28SRC01 PCI-Express Clock Generator Features * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * One 100 MHz differential SRC clocks * 3.3V power supply * Low-voltage frequency select input * 16-pin TSSOP package * I2C support with readback capabilities Pin Configuration Block Diagram XIN XOUT XTAL OSC PLL Ref Freq Divider Network PLL VDD_SRC SRCT0,SRCC0 1 2 3 4 5 6 7 8 VSS_SRC VDD_SRC SRCC0 SRCT0 VDD_SRC VSS_SRC IREF VSSA 16 15 14 13 12 11 10 9 VDD_SRC SDATA SCLK XOUT XIN VDD_REF VSS_REF VDDA 16 TSSOP IREF SDATA SCLK I2C Logic Pin Description Pin No. Name Type Description 7 IREF I A precision resistor (475:) attached to this pin is connected to the internal current reference. 14 SCLK I,PU SMBus compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in powerdown. 15 SDATA 3,4 SRC[T/C]0 12 XIN I/O, PU SMBus compatible SDATA.This pin has an internal pull-up, but is tri-stated in powerdown. O, DIF Differential Selectable Serial reference clock. Intel Type-X buffer. Includes overclock support through SMBUS I 14.318-MHz Crystal Input 13 XOUT O 2, 5,16 VDD_SRC PWR 14.318-MHz Crystal Output 1,6 VSS_SRC GND Ground for SRC outputs 9 VDDA PWR 3.3V power supply for PLL 3.3V power supply for SRC outputs 8 VSSA GND Analog Ground 11 VDD_REF PWR Power for Xtal 10 VSS_REF GND Ground for Xtal Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Page 1 of 9 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY28SRC01 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:5) Chip select address, set to `00' to access device (4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 Description Start Block Read Protocol Bit 1 Slave address - 7 bits Write 8:2 9 Description Start Slave address - 7 bits Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code - 8 bits 18:11 Command Code - 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count - 8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N - 8 bits .... Acknowledge from slave .... Stop 27:21 Slave address - 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave - 8 bits .... NOT Acknowledge Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address - 7 bits Byte Read Protocol Bit 1 8:2 Description Start Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave Rev 1.0, November 20, 2006 Page 2 of 9 CY28SRC01 Table 3. Byte Read and Byte Write Protocol 18:11 Command Code - 8 bits 18:11 Command Code - 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Data byte - 8 bits 20 Repeated start 27:20 28 Acknowledge from slave 29 Stop 27:21 28 Slave address - 7 bits Read 29 Acknowledge from slave 37:30 Data from slave - 8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0:Control Register 0 Bit @Pup Name Description 7 0 Reserved Reserved 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC [T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 1: Control Register 1 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 2: Control Register 2 Bit @Pup 7 1 SRCT/C Name Spread Spectrum Selection `0' = -0.35% `1' = -0.50% 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved Rev 1.0, November 20, 2006 Description Page 3 of 9 CY28SRC01 Byte 2: Control Register 2 (continued) Bit @Pup Name Description 3 1 Reserved Reserved 2 0 SRC SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 3: Control Register 3 Bit @Pup 7 1 Reserved Name Reserved Description 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 4: Control Register 4 Bit @Pup 7 0 Reserved Name Reserved Description 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 6: Control Register 6 Bit @Pup Name 7 0 TEST_SEL REF/N or Tri-state Select 1 = REF/N Clock, 0 = Tri-state 6 0 TEST_MODE Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation 5 0 Reserved Reserved Rev 1.0, November 20, 2006 Description Page 4 of 9 CY28SRC01 Byte 6: Control Register 6 Bit @Pup Name Description 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 7: Control Register 7 Bit @Pup Name Description 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 1 Revision Code Bit 1 4 1 Revision Code Bit 0 3 1 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 12pF - 16pF 1mW 7 pF + 50ppm + 50ppm 5 ppm Crystal Recommendations Calculating Load Capacitors The CY28SRC01 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28SRC01 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Clock Chip Ci2 C i1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 27pF Figure 2. Crystal Loading Example Figure 1. Crystal Capacitive Clarification Rev 1.0, November 20, 2006 As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacPage 5 of 9 CY28SRC01 itance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. CL....................................................Crystal load capacitance Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Cs .............................................. Stray capacitance (terraced) Load Capacitance (each side) CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + Rev 1.0, November 20, 2006 1 Ce2 + Cs2 + Ci2 ) Page 6 of 9 CY28SRC01 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage -0.5 4.6 V VDDA Analog Supply Voltage -0.5 4.6 V VIN Input Voltage Relative to VSS -0.5 VDD + 0.5 VDC TS Temperature, Storage Non Functional -65 +150 C TA Temperature, Operating Ambient Functional 0 70 C TJ Temperature, Junction Functional - 150 C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 - V OJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 - 20 C/W OJA Dissipation, Junction to Ambient JEDEC (JESD 51) - 60 C/W UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level V-0 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description VDD_SRC, 3.3V Operating Voltage VDDA Condition 3.3V 5% Min. Max. Unit 3.135 3.465 V VILSMBUS Input Low Voltage SDATA, SCLK - 1.0 V VIHSMBUS Input High Voltage SDATA, SCLK 2.2 - V VDD VIL Input Low Voltage VIH Input High Voltage IIL VSS - 0.3 0.8 V 2.0 VDD + 0.3 V Input Leakage Current Except Pull-ups or Pull downs 0<VIN<VDD -5 5 mA VOL Output Low Voltage IOL = 1 mA - 0.4 V VOH Output High Voltage IOH = 1 mA IOZ High-Impedance Output Current CIN Input Pin Capacitance 3 5 pF Output Pin Capacitance 3 5 pF COUT LIN Pin Inductance VXIH Xin High Voltage VXIL Xin Low Voltage IDD Dynamic Supply Current At max load and frequency IPDD Power Down Supply Current PD asserted, Outputs driven IPDT Power Down Supply Current PD asserted, Outputs Hi-Z Rev 1.0, November 20, 2006 2.4 - V -10 10 PA - 7 nH 0.7*VDD VDD V 0 0.3*VDD V - 400 mA - 70 mA - 2 mA Page 7 of 9 CY28SRC01 AC Electrical Specifications Parameter Description Condition Min. Max. Unit Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % TPERIOD XIN Period When XIN is driven from an external clock source 69.841 71.0 ns T R / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD - 10.0 ns SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODAbs 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX 10.12800 9.872001 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns % TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX - 250 ps TSKEW Any SRCS clock to Any SRCS clock Skew Measured at crossing point VOX - 250 ps TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX - 125 ps LACC SRCT/C Long Term Accuracy Measured at crossing point VOX - 300 ppm T R / TF SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR - TF)/(TR + TF) - 20 % 'TR Rise TimeVariation - 125 ps 'TF Fall Time Variation - 125 ps VHIGH Voltage High Math averages Figure 3 660 850 mv VLOW Voltage Low Math averages Figure 3 -150 - mv VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage - VHIGH + 0.3 V VUDS Minimum Undershoot Voltage -0.3 - V VRB Ring Back Voltage - 0.2 V See Figure 3. Measure SE Test and Measurement Set-up The following diagram shows the test load configuration for the differential SRC outputs. : SRCT : : SRCC IR E F : M e a s u re m e n t P o in t 2pF : : M e a s u re m e n t P o in t 2pF : Figure 3. 0.7V Load Configuration Rev 1.0, November 20, 2006 Page 8 of 9 CY28SRC01 Ordering Information Part Number Package Type Product Flow Lead-free CY28SRC01ZXC 16-pin TSSOP Commercial, 0q to 70qC CY28SRC01ZXCT 16-pin TSSOP - Tape and Reel Commercial, 0q to 70qC Package Diagram 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 9 of 9